RISC-V CPU Datapath, Control Intro

Instructor: Steven Ho
 Review -- SDS and Sequential Logic

7/09/2018 CS61C Su18 - Lecture 11 2

 Review -- Timing

Setup Violation

CLK

FF CL FF

Clk-to-q + longest CL + setup time <= Clk period 3

 Review -- Timing

Hold Time Violation

CLK

FF CL FF

Clk-to-q + shortest CL >= hold time 4

 Review -- SDS and Sequential Logic

Critical Path = Clk-to-q + longest CL + setup time

between ANY two registers

7/09/2018 CS61C Su18 - Lecture 11 5

 Review -- Combinational Logic
• Hardware is permanent. Always do everything
you might want
• Use MUXes to pick from among input
– S input bits selects one of 2S inputs

• Ex: ALU
7/09/2018 CS61C Su18 - Lecture 11 6
 Great Idea #1: Levels of
Representation & Interpretation
Higher-Level Language temp = v[k];
Program (e.g. C) v[k] = v[k+1];
v[k+1] = temp;
Compiler
lw $t0, 0($2)
Assembly Language lw $t1, 4($2)
Program (e.g. RISC-V) sw $t1, 0($2)
sw $t0, 4($2)
Assembler
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language 1010 1111 0101 1000 0000 1001 1100 0110
Program (RISC-V) 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111
Machine
Interpretation We are here
Hardware Architecture Description
(e.g. block diagrams)
Architecture
Implementation
Logic Circuit Description
(Circuit Schematic Diagrams)
7/09/2018 CS61C Su18 - Lecture 11 7
 Agenda
• Datapath Overview
• Assembling the Datapath Part 1
• Administrivia
• Processor Design Process
• Assembling the Datapath Part 2

7/09/2018 CS61C Su18 - Lecture 11 8

 Hardware Design Hierarchy
system
Today

datapath control

code state combinational

multiplexer comparator
register registers logic
s

register logic

switching
networks
7/09/2018 CS61C Su18 - Lecture 11 9
 The Processor
• Processor (CPU): Instruction Set Architecture
(ISA) implemented directly in hardware
– Datapath: part of the processor that contains the
hardware necessary to perform operations
required by the processor (“the brawn”)
– Control: part of the processor (also in hardware)
which tells the datapath what needs to be done
(“the brain”)

7/09/2018 CS61C Su18 - Lecture 11 10

 Executing an Instruction
Very generally, what steps do you take (order
matters!) to figure out the effect/result of the
next RISC-V instruction?
– Get the instruction add s0,t0,t1
– What instruction is it? add
– Gather data read R[t0], R[t1]
– Perform operation calc R[t0]+R[t1]
– Store result save into s0

7/09/2018 CS61C Su18 - Lecture 11 11

 State Required by RV32I ISA
Each instruction reads and updates this state during execution:
• Registers (x0..x31)
− Register file (or regfile) Reg holds 32 registers x 32 bits/register: Reg[0].. Reg[31]
− First register read specified by rs1 field in instruction
− Second register read specified by rs2 field in instruction
− Write register (destination) specified by rd field in instruction
− x0 is always 0 (writes to Reg[0]are ignored)
• Program Counter (PC)
− Holds address of current instruction
• Memory (MEM)
− Holds both instructions & data, in one 32-bit byte-addressed memory space
− We’ll use separate memories for instructions (IMEM) and data (DMEM)
▪ Later we’ll replace these with instruction and data caches
− Instructions are read (fetched) from instruction memory (assume IMEM read-only)
− Load/store instructions access data memory

7/09/2018 CS61C Su18 - Lecture 11 12

 One-Instruction-Per-Cycle RISC-V Machine
• On every tick of the clock,
the computer executes one
instruction
• Current state outputs drive
pc the inputs to the
combinational logic, whose
outputs settles at the values
of the state before the next
clock edge
clock
• At the rising clock edge, all
IMEM the state elements are
Combinational updated with the
Logic combinational logic
outputs, and execution
moves to the next clock
Reg[] cycle

DMEM

7/09/2018 CS61C Su18 - Lecture 11 13

Basic Phases of Instruction Execution

rd
PC

Reg[]
rs1

IMEM
ALU

DMEM
rs2

+ imm
4
mux

1. Instruction 2. Decode/ 5. Register

3. Execute 4. Memory
Fetch Register Write
Read

Clock
7/09/2018 time 14
 Why Five Stages?
• Could we have a different number of stages?
– Yes, and other architectures do
• So why does RISC-V have five if instructions
tend to idle for at least one stage?
– The five stages are the union of all the operations
needed by all the instructions
– There is one instruction that uses all five stages:
load (lw/lb)

7/09/2018 CS61C Su18 - Lecture 11 15

 Agenda
• Datapath Overview
• Assembling the Datapath Part 1
• Administrivia
• Processor Design Process
• Assembling the Datapath Part 2

7/09/2018 CS61C Su18 - Lecture 11 16

 Implementing the add instruction

add rd, rs1, rs2

• Instruction makes two changes to machine’s state:
− Reg[rd] = Reg[rs1] + Reg[rs2]
− PC = PC + 4

7/09/2018 CS61C Su18 - Lecture 11 17

 Datapath Walkthroughs (1/3)
• add x3,x1,x2 # r3 = r1+r2
1) IF: fetch this instruction, increment PC
2) ID: decode as add
then read R[1] and R[2]
3) EX: add the two values retrieved in ID
4) MEM: idle (not using memory)
5) WB: write result of EX into R[3]

7/09/2018 CS61C Su18 - Lecture 11 18

 Example: add Instruction

add x3,x1,x2
R[1] + R[2]
R[1]

registers
3
instruction
memory
PC

memory
1 ALU

Data
2 R[2]

imm
+4
MUX

7/09/2018 CS61C Su18 - Lecture 11 19

 Datapath for add

+4 Reg[]
DataD Reg[rs1]
pc inst[11:7] alu
pc+4
IMEM AddrD
inst[19:15] AddrA DataA Reg[rs2]
+
inst[24:20] AddrB DataB

inst[31:0] RegWriteEnable
(RegWEn)

Control Logic
7/09/2018 CS61C Su18 - Lecture 11 20
 Timing Diagram for add
+4 Reg[]
DataD Reg[rs1]
pc inst[11:7] alu
pc+4 IMEM AddrD
inst[19:15] AddrA DataA Reg[rs2]
+
inst[24:20] AddrB DataB

inst[31:0]
RegWEn

clock
time
Clock

PC 1000 1004

PC+4 1004 1008

inst[31:0] add x1,x2,x3 add x6,x7,x9

Reg[rs1] Reg[2] Reg[7]

Reg[rs2] Reg[3] Reg[9]

alu Reg[2]+Reg[3] Reg[7]+Reg[9]

Reg[1] ??? Reg[2]+Reg[3] 21

 Implementing the sub instruction

sub rd, rs1, rs2

• Almost the same as add, except now have to subtract
operands instead of adding them
• inst[30] selects between add and subtract

7/09/2018 CS61C Su18 - Lecture 11 22

 Datapath for add/sub

+4 Reg[]
DataD Reg[rs1]
ALU
pc inst[11:7] alu
IMEM AddrD
pc+4 inst[19:15] AddrA DataA Reg[rs2]
inst[24:20] AddrB DataB

inst[31:0] RegWEn ALUSel

(1=write, 0=no write) (Add=0/Sub=1)

Control Logic
7/09/2018 CS61C Su18 - Lecture 11 23
 Implementing other R-Format instructions

• All implemented by decoding funct3 and funct7 fields and

selecting appropriate ALU function
7/09/2018 CS61C Su18 - Lecture 11 24
Implementing the addi instruction
• RISC-V Assembly Instruction:
addi x15,x1,-50

111111001110 00001 000 01111 0010011

imm=-50 rs1=1 ADD rd=15 OP-Imm

7/09/2018 CS61C Su18 - Lecture 11 25

 Datapath for add/sub

+4 Reg[]
DataD Reg[rs1]
ALU
pc inst[11:7] alu
IMEM AddrD
pc+4 inst[19:15] AddrA DataA Reg[rs2]
inst[24:20] AddrB DataB

inst[31:0] RegWEn ALUSel

(1=write, 0=no write) (Add=0/Sub=1)

Control Logic
7/09/2018 CS61C Su18 - Lecture 11 26
 Adding addi to datapath

+4 Reg[]
DataD
ALU
pc inst[11:7] Reg[rs1] alu
IMEM AddrD
pc+4 inst[19:15] AddrA DataA 0
Reg[rs2]
inst[24:20] AddrB DataB 1

inst[31:20]
Imm. imm[31:0]
Gen

inst[31:0] ImmSel=I RegWEn=1 BSel=1 ALUSel=Add

Control Logic
7/09/2018 CS61C Su18 - Lecture 11 27
 I-Format immediates

inst[31:0]

------inst[31]-(sign-extension)------- inst[30:20]

imm[31:0]
inst[31:20] imm[31:0]
Imm.
Gen • High 12 bits of instruction (inst[31:20]) copied to low 12 bits
of immediate (imm[11:0])
• Immediate is sign-extended by copying value of inst[31] to
ImmSel=I fill the upper 20 bits of the immediate value (imm[31:12])

7/09/2018 CS61C Su18 - Lecture 11 28

 Adding addi to datapath

+4 Reg[]
DataD
ALU
pc inst[11:7] Reg[rs1] alu
IMEM AddrD
pc+4 inst[19:15] AddrA DataA 0
Reg[rs2]
inst[24:20] AddrB DataB 1

Also works for all other

I-format arithmetic instruction
inst[31:20] (slti,sltiu,andi,ori,
Imm. imm[31:0]
Gen xori,slli,srli,srai)
just by changing ALUSel

inst[31:0] ImmSel=I RegWEn=1 BSel=1 andi

sltiu
slti
xori
ALUSel=Add
ori

Control Logic
7/09/2018 CS61C Su18 - Lecture 11 29
 Agenda
• Datapath Overview
• Assembling the Datapath Part 1
• Administrivia
• Processor Design Process
• Assembling the Datapath Part 2

7/09/2018 CS61C Su18 - Lecture 11 30

 Administrivia
• Project 2-2 due Friday (7/13)
− Project Party tonight 4-6p in Soda 405 and 411!
• Homework 4 released; 3/4 due Monday (7/16)
• Guerilla Session on Wednesday, 4-6p, Cory 540AB
− SDS, FSM, and Single-Cycle Datapath
• Project 3 will be released Thursday
− Project party on 7/13, 4-6p (intended for students to get help
starting on proj3/finishing lab 6)
− Project party 7/20, 4-6p to finish up project 3
• Homework 2 grades are on glookup
− Hw0/Hw1 not yet updated, but if you still didn’t get credit for
hw2, please change your emails to match!
7/09/2018 CS61C Su18 - Lecture 11 31
 Agenda
• Datapath Overview
• Assembling the Datapath Part 1
• Administrivia
• Processor Design Process
• Assembling the Datapath Part 2

7/09/2018 CS61C Su18 - Lecture 11 32

 Processor Design Process
• Five steps to design a processor:
1. Analyze instruction set →
datapath requirements Processor
Input
2. Select set of datapath Control
components & establish Memory
Now

clock methodology
Datapath Output
3. Assemble datapath components
to meet the requirements
4. Analyze implementation of each instruction to determine
setting of control points that affect the register transfer
5. Assemble the control logic
• Formulate Logic Equations
• Design Circuits

7/09/2018 CS61C Su18 - Lecture 11 33

Step 1: Requirements of the Instruction Set
• Memory (MEM)
– Instructions & data (separate: in reality just caches)
– Load from and store to
• Registers (32 32-bit regs)
– Read rs1 and rs2
– Write rd
• PC
– Add 4 (+ maybe extended immediate)
• Add/Sub/OR unit for operation on register(s) or
extended immediate
– Compare if registers equal?

7/09/2018 CS61C Su18 - Lecture 11 34

Storage Element: Idealized Memory
• Memory (idealized) Write Enable Address

– One input bus: Data In

Data In DataOut
– One output bus: Data Out 32 32
• Memory access: CLK
– Read: Write Enable = 0, data at Address is placed on
Data Out
– Write: Write Enable = 1, Data In written to Address
• Clock input (CLK)
– CLK input is a factor ONLY during write operation
– During read, behaves as a combinational logic block:
Address valid → Data Out valid after “access time”

7/09/2018 CS61C Su18 - Lecture 11 35

 Storage Element: Register
Write Enable
• Similar to D flip-flop except:
Data In Data Out
– N-bit input and output buses
N N
– Write Enable input
• Write Enable: CLK
– De-asserted (0): Data Out will not change
– Asserted (1): Data In value placed onto Data Out
after CLK trigger

7/09/2018 CS61C Su18 - Lecture 11 36

 Storage Element: Register File
RW RA RB
Write Enable 5 5 5
• Register File consists of 32 registers: busA
– Output buses busA and busB busW 32 x 32-bit 32
– Input bus busW 32 Registers busB
• Register selection Clk 32
– Place data of register RA (number) onto busA
– Place data of register RB (number) onto busB
– Store data on busW into register RW (number) when Write
Enable is 1
• Clock input (CLK)
– CLK input is a factor ONLY during write operation
– During read, behaves as a combinational logic block:
RA or RB valid → busA or busB valid after “access time”
7/09/2018 CS61C Su18 - Lecture 11 37
 Step 2: CPU Clocking
• For each instruction, how do we control the flow of
information through the datapath?
• Single Cycle CPU: All stages of an instruction
completed within one long clock cycle
– Clock cycle sufficiently long to allow each instruction to
complete all stages without interruption within one cycle

38
 Step 3: Assembling the Datapath
• Assemble datapath to meet ISA requirements
– Exact requirements will change based on ISA
– Here we must examine each instruction of RISC
• The datapath is all of the hardware
components and wiring necessary to carry out
ALL of the different instructions
– Make sure all components (e.g. RegFile, ALU) have
access to all necessary signals and buses
– Control will make sure instructions are properly
executed (the decision making)

7/09/2018 CS61C Su18 - Lecture 11 39

 Agenda
• Datapath Overview
• Assembling the Datapath Part 1
• Administrivia
• Processor Design Process
• Assembling the Datapath Part 2

7/09/2018 CS61C Su18 - Lecture 11 40

Implementing Load Word instruction
• RISC-V Assembly Instruction:
lw x14, 8(x2)

000000001000 00010 010 01110 0000011

imm=+8 rs1=2 LW rd=14 LOAD

7/09/2018 CS61C Su18 - Lecture 11 41

 Adding addi to datapath

+4 Reg[]
DataD
ALU
pc IMEM inst[11:7]
AddrD Reg[rs1] alu
pc+4 inst[19:15] AddrA DataA 0
Reg[rs2]
inst[24:20] AddrB DataB 1

inst[31:20]Imm.
imm[31:0]
Gen

inst[31:0] ImmSel=I RegWEn=1 BSel=1 ALUSel=Add

Control Logic
7/09/2018 CS61C Su18 - Lecture 11 42
 Adding lw to datapath
ALU
+4 Reg[]
wb
DataD
ALU DMEM 1
pc IMEM inst[11:7]
AddrD Reg[rs1]
Addr wb
pc+4 inst[19:15] AddrA DataA 0
DataR 0
Reg[rs2] mem
inst[24:20] AddrB DataB 1

inst[31:20]Imm.
imm[31:0]
Gen

inst[31:0] ImmSel RegWEn BSel ALUSel MemRW WBSel

7/09/2018 CS61C Su18 - Lecture 11 43

 Adding lw to datapath
alu
+4 Reg[]
wb
DataD
Reg[rs1] ALU DMEM 1
pc IMEM inst[11:7]
AddrD
Reg[rs2] Addr wb
DataR 0
pc+4 inst[19:15] AddrA DataA 0
mem
inst[24:20] AddrB DataB 1

inst[31:20]Imm.
imm[31:0]
Gen

inst[31:0] ImmSel=I RegWEn=1 Bsel=1 ALUSel=Add MemRW=Read WBSel=0

7/09/2018 CS61C Su18 - Lecture 11 44

 All RV32 Load Instructions

funct3 field encodes size and

signedness of load data

• Supporting the narrower loads requires additional circuits to

extract the correct byte/halfword from the value loaded from
memory, and sign- or zero-extend the result to 32 bits before
writing back to register file.

7/09/2018 CS61C Su18 - Lecture 11 45

 Implementing Store Word
instruction
• RISC-V Assembly Instruction:
sw x14, 8(x2)

0000000 01110 00010 010 01000 0100011

offset[11:5] rs2=14 rs1=2 SW offset[4:0] STORE
=0 =8

combined 12-bit offset = 8

7/09/2018 0000000 01000 46
 Adding lw to datapath
ALU
+4 Reg[]
wb
DataD
Reg[rs1] ALU DMEM 1
pc IMEM inst[11:7]
AddrD
pc+4 Reg[rs2] Addr wb
DataR 0
inst[19:15] AddrA DataA 0
mem
inst[24:20] AddrB DataB 1

inst[31:20]Imm.
imm[31:0]
Gen

inst[31:0] ImmSel RegWEn BSel ALUSel MemRW WBSel

7/09/2018 CS61C Su18 - Lecture 11 47

 Adding sw to datapath
ALU
+4 Reg[]
wb
DataD
Reg[rs1] ALU DMEM
1
pc IMEM inst[11:7]
AddrD
pc+4 Reg[rs2] Addr wb
DataR 0
inst[19:15] AddrA DataA 0
DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

inst[31:0] ImmSel RegWEn Bsel ALUSel MemRW WBSel=

7/09/2018 CS61C Su18 - Lecture 11 48

 Adding sw to datapath
ALU
+4 Reg[]
wb
DataD
Reg[rs1] ALU DMEM
1
pc IMEM inst[11:7]
AddrD
pc+4 Reg[rs2] Addr wb
DataR 0
inst[19:15] AddrA DataA 0
DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

inst[31:0] ImmSel=S RegWEn=0 Bsel=1 ALUSel=Add MemRW=Write WBSel=*

*= “Don’t Care”

7/09/2018 CS61C Su18 - Lecture 11 49

 I-Format immediates

inst[31:0]

------inst[31]-(sign-extension)------- inst[30:20]

imm[31:0]
inst[31:20] imm[31:0]
Imm.
Gen • High 12 bits of instruction (inst[31:20]) copied to low 12 bits
of immediate (imm[11:0])
• Immediate is sign-extended by copying value of inst[31] to
ImmSel=I fill the upper 20 bits of the immediate value (imm[31:12])

7/09/2018 CS61C Su18 - Lecture 11 50

 I & S Immediate Generator inst[31:0]
31 25 24 20 19 15 14 12 11 7 6 0

imm[11:0] rs1 funct3 rd I-opcode

imm[11:5] rs2 rs1 funct3 imm[4:0] S-opcode

5
5
1 6
I S

inst[31](sign-extension) inst[30:25] inst[24:20] I

inst[31](sign-extension) inst[30:25] inst[11:7] S

31 11 10 5 4 0
• Just need a 5-bit mux to select between two positions where low imm[31:0]
five bits of immediate can reside in instruction
7/09/2018 • Other bits in immediate are wired to fixed positions in instruction 51
 Implementing Branches

• B-format is mostly same as S-Format, with two

register sources (rs1/rs2) and a 12-bit immediate
• But now immediate represents values -4096 to +4094
in 2-byte increments
• The 12 immediate bits encode even 13-bit signed byte
offsets (lowest bit of offset is always zero, so no need
to store it)

7/09/2018 CS61C Su18 - Lecture 11 52

 Adding sw to datapath

+4 Reg[] ALU
wb
DataD
Reg[rs1] ALU DMEM
pc IMEM inst[11:7]
AddrD
1
pc+4 Reg[rs2] Addr wb
DataR 0
inst[19:15] AddrA DataA 0
DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

inst[31:0] ImmSel RegWEn Bsel ALUSel MemRW WBSel=

7/09/2018 CS61C Su18 - Lecture 11 53

 Adding branches to datapath

+4 Reg[] pc
ALU
wb 1
DataD
alu 1 Reg[rs1] ALU DMEM
0
0
pc IMEM inst[11:7]
AddrD
1
Reg[rs2] Addr wb
pc+4 Branch DataR
0 0
inst[19:15] AddrA DataA
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

7/09/2018 CS61C Su18 - Lecture 11 54

 Adding branches to datapath

+4 Reg[] pc
alu
alu
wb 1
DataD
1 Reg[rs1] ALU DMEM
0
0
pc IMEM inst[11:7]
AddrD
1
Reg[rs2] Addr wb
Branch DataR 0
pc+4 inst[19:15] AddrA DataA 0
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

PCSel=taken/not-taken inst[31:0] ImmSel=B RegWEn=0 BrUn BrEq BrLT Bsel=1 ASel=1 MemRW=Read WBSel=*

ALUSel=Add

7/09/2018 CS61C Su18 - Lecture 11 55

 Branch Comparator
A • BrEq = 1, if A=B
Branch
Comp. • BrLT = 1, if A < B
B
• BrUn =1 selects unsigned comparison
for BrLT, 0=signed

• BGE branch: A >= B, if !(A<B)

BrUn BrEq BrLT

7/09/2018 CS61C Su18 - Lecture 11 56

 Break!

7/09/2018 CS61C Su18 - Lecture 11 57

 Multiply Branch Immediates by
Shift?
• 12-bit immediate encodes PC-relative offset of -4096 to +4094 bytes in multiples of 2 bytes
• Standard approach: treat immediate as in range -2048..+2047, then shift left by 1 bit to
multiply by 2 for branches

s imm[10:5] rs2 rs1 funct3 imm[4:0] B-opcode

sign-extension s imm[10:5] imm[4:0] S-Immediate

sign-extension s imm[10:5] imm[4:0] 0 B-Immediate (shift left by 1)

Each instruction immediate bit can appear in one of two places in output immediate value –
so need one 2-way mux per bit

7/09/2018 CS61C Su18 - Lecture 11 58

 RISC-V Branch Immediates
• 12-bit immediate encodes PC-relative offset of -4096 to +4094 bytes in multiples of 2 bytes
• RISC-V approach: keep 11 immediate bits in fixed position in output value, and rotate LSB
of S-format to be bit 12 of B-format

sign=imm[11] imm[10:5] imm[4:0] S-Immediate

sign=imm[12] imm[10:5] imm[4:1] 0 B-Immediate (shift left by 1)

imm[11]

Only one bit changes position between S and B, so only need a single-bit 2-way mux

7/09/2018 CS61C Su18 - Lecture 11 59

 RISC-V Immediate Encoding
Instruction Encodings, inst[31:0]

32-bit immediates produced, imm[31:0]

Only bit 7 of instruction changes role in

Upper bits sign-extended from inst[31] always immediate between S and B 60
 Implementing JALR Instruction (I-Format)

• JALR rd, rs, immediate

− Writes PC+4 to Reg[rd] (return address)
− Sets PC = Reg[rs1] + immediate
− Uses same immediates as arithmetic and loads
▪ no multiplication by 2 bytes

7/09/2018 CS61C Su18 - Lecture 11 61

 Adding branches to datapath

+4 Reg[] pc
alu
wb 1
DataD
alu 1 Reg[rs1] ALU DMEM
0
0
pc IMEM inst[11:7]
AddrD
1
Reg[rs2] Addr wb
pc+4 Branch DataR
0 0
inst[19:15] AddrA DataA
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

7/09/2018 CS61C Su18 - Lecture 11 62

 Adding jalr to datapath
pc+4
+4 Reg[] pc
alu
wb 1
DataD 2
alu 1 Reg[rs1] ALU DMEM
0
0
pc IMEM inst[11:7]
AddrD
1
Reg[rs2] Addr wb
pc+4 Branch DataR
0 0
inst[19:15] AddrA DataA
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

7/09/2018 CS61C Su18 - Lecture 11 63

 Adding jalr to datapath
pc+4
alu
+4 Reg[] pc alu
wb 1
DataD 2
1 Reg[rs1] ALU DMEM
0
0
pc IMEM inst[11:7]
AddrD
1
Reg[rs2] Addr wb
pc+4 Branch DataR
0 0
inst[19:15] AddrA DataA
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

WBSel=2
PCSel inst[31:0] ImmSel=B RegWEn=1 Bsel=1 Asel=0 MemRW=Read

ALUSel=Add
BrUn=* BrEq=* BrLT=*

7/09/2018 CS61C Su18 - Lecture 11 64

 Implementing jal Instruction

• JAL saves PC+4 in Reg[rd] (the return address)

• Set PC = PC + offset (PC-relative jump)
• Target somewhere within ±219 locations, 2 bytes apart
− ±218 32-bit instructions
• Immediate encoding optimized similarly to branch
instruction to reduce hardware cost

7/09/2018 CS61C Su18 - Lecture 11 65

 Adding jal to datapath
pc+4
+4 Reg[] pc
alu
wb 1
DataD 2
alu 1 Reg[rs1] ALU DMEM
0
0
pc IMEM inst[11:7]
AddrD
1
Reg[rs2] Addr wb
pc+4 Branch DataR
0 0
inst[19:15] AddrA DataA
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

7/09/2018 CS61C Su18 - Lecture 11 66

 Adding jal to datapath
pc+4
alu
+4 Reg[] pc alu
wb 1
DataD 2
1 Reg[rs1] ALU DMEM
0
0
pc IMEM inst[11:7]
AddrD
1
Reg[rs2] Addr wb
pc+4 Branch DataR
0 0
inst[19:15] AddrA DataA
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

WBSel=2
PCSel inst[31:0] ImmSel=J RegWEn=1 Bsel=1 Asel=1 MemRW=Read

ALUSel=Add
BrUn=* BrEq=* BrLT=*

7/09/2018 CS61C Su18 - Lecture 11 67

 Single-Cycle RISC-V RV32I Datapath
pc+4
+4 Reg[] pc
alu
wb 1
DataD 2
alu 1 Reg[rs1] ALU DMEM
0
0
pc IMEM inst[11:7]
AddrD
1
Reg[rs2] Addr wb
pc+4 Branch DataR
0 0
inst[19:15] AddrA DataA
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7] Imm. imm[31:0]

Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

7/09/2018 CS61C Su18 - Lecture 11 68

Question: Which of the following RISC-V instructions
is active in the most stages?

instruction rd
memory
Register

memory
PC

rs1 ALU

Data
rs2 File

+4 imm
MUX

1. Instruction 2. Decode/ 4. Memory 5. Register

3. Execute
Fetch Register Read Write

(A) lw (B) jal (C) beq (D) add

IF,ID,EX, IF,EX,WB IF,ID,EX IF,ID,EX,
MEM,WB WB 69
 Processor Design Process
• Five steps to design a processor:
1. Analyze instruction set → Processor
Input
datapath requirements Control
2. Select set of datapath Memory
components & establish
Datapath
clock methodology Output
3. Assemble datapath meeting
the requirements
Now

4. Analyze implementation of each instruction to determine

setting of control points that affect the register transfer
5. Assemble the control logic
• Formulate Logic Equations
• Design Circuits
7/09/2018 CS61C Su18 - Lecture 11 70
 Control
• Need to make sure that correct parts of the
datapath are being used for each instruction
– Have seen control signals in datapath used to
select inputs and operations
– For now, focus on what value each control signal
should be for each instruction in the ISA
• Next lecture, we will see how to implement the proper
combinational logic to implement the control

7/09/2018 CS61C Su18 - Lecture 11 71

 Summary (1/2)
• Five steps to design a processor:
1) Analyze instruction set → Processor
datapath requirements Input
Control
2) Select set of datapath Memory
components & establish
clock methodology Datapath Output
3) Assemble datapath meeting
the requirements
4) Analyze implementation of each instruction to determine
setting of control points that effects the register transfer
5) Assemble the control logic
• Formulate Logic Equations
• Design Circuits

7/09/2018 CS61C Su18 - Lecture 11 72

 Summary (2/2)
• Determining control signals
– Any time a datapath element has an input that
changes behavior, it requires a control signal
(e.g. ALU operation, read/write)
– Any time you need to pass a different input based
on the instruction, add a MUX with a control
signal as the selector
(e.g. next PC, ALU input, register to write to)
• Your control signals will change based on your
exact datapath
• Your datapath will change based on your ISA
7/09/2018 CS61C Su18 - Lecture 11 73
 And in Conclusion, …
• Universal datapath
− Capable of executing all RISC-V instructions in one cycle each
− Not all units (hardware) used by all instructions
• 5 Phases of execution
− IF, ID, EX, MEM, WB
− Not all instructions are active in all phases
• Controller specifies how to execute instructions
− what new instructions can be added with just most control?

7/09/2018 CS61C Su18 - Lecture 11 74