CHAPTER SIX

CENTRAL PROCESSING UNIT (CPU)

 The part of the computer performs the bulk of data processing operations is called the
central processing unit
 The CPU is made up of three major parts:
 Register set
 ALU
 Control units

The central processing unit (CPU) of a computer is the main unit that dictates the rest of the
computer organization.

 1. Register set:
t: Stores intermediate data during the execution of instructions;
 2. Arithmetic logic unit (ALU):
(ALU Performs the required micro-operations
perations for executing the
instructions;
 3. Control unit:
t: supervises the transfer of information among the registers and instructs
the ALU as to which operation to perform by generating control signals.

GENERAL REGISTER ORGANIZATIONS

CPU must have some working space (fast access and close to CPU). This space is
efficiently used to store intermediate values.
values The most convenient way to communicate
registers is trough common bus system.
system

Bus organization for 7 CPU registers:

 2 MUX:: select one of 7 register

regis or external data input by SELA and SELB
 BUS A and BUS B : form the inputs to a common ALU
 ALU : OPR determine the arithmetic or logic microoperation
 The result of the microoperation is available for external data output and also
goes into the inputs
input of all registers
 3 X 8 Decoder:: select the register (by SELD)) that receives the information from ALU

 An operation is selected by the ALU operation selector (OPR).

 The result of a microoperation is directed to a destination register selected by a decoder
(SELD).

Control word: The 14 binary selection inputs. It consists of four fields. (3 bits for SELA, 3 for
SELB, 3 for SELD, and 5 for OPR)

The three bit s of SELA select a source register for the A input of the ALU. The three bit s of SELB
select a register for the B input of the ALU. The three bits of SELD select a destination register
using the decoder and its seven load outputs. The five bits OPR select one of the operations in
the ALU. The 14 bits control word when applied to the selection inputs specify a particular
microoperation.

Example:
 R1  R 2  R3

 Binary selector input

1) MUX A selector (SELA) : to place the content of R2 into BUS A
2) MUX B selector (SELB) : to place the content of R3 into BUS B
3) ALU operation selector (OPR) : to provide the arithmetic addition R2 +
R3
4) Decoder selector (SELD) : to transfer the content of the output bus into
R1

The encoding of the register selections is specified in the following table. The 3 bit binary code
listed in the first column of the table specifies the binary code for each of the three fields.

Encoding of Register Selection Fields:

 » SELA or SELB = 000 (External Input) : MUX selects the external
data
» SELD = 000 (None) : no destination register is selected but the
contents of the output bus are available in the external output

Examples of Micro operations:

A control word of 14 bits is needed to specify a microoperation in the CPU. The control
word for a given microoperation can be derived from the selection variables, for example,
the subtract microoperation given by the statement.

R1  R2 – R3

Specifies R2 for the A input of the ALU, R3 for the B input of the ALU, R1 for the destination
register, and an ALU operation to subtract A-B. The binary control word for the subtract
microoperation is 010 011 001 00101 is obtained as follows:

Field : SELA SELB SELD OPR

Symbol : R2 R3 R1 SUB
Control word 010 011 001 00101

The control word for this Microoperation and a few others are listed in the following table:

Symbolic designation

Microoperation SELA SELB SELD OPR Control word

R1 R2-R3 R2 R3 R1 SUB 010 011 001 00101

R4  R4 V R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 +1 R6 -- R6 INCA 110 000 110 00001
R7  R1 R1 -- R7 TSFA 001 000 111 00000
Output  R2 R2 -- None TSFA 010 000 000 00000
Output input input -- None TSFA 000 000 000 00000
R4  sh1 R4 R4 -- R4 SHLA 100 000 100 11000
R5  0 R5 R5 R5 XOR 101 101 101 01100

The increment and transfer Microoperation do not use the B input of the ALU. For these cases,
the B field is marked with a dash. We assign 000 to any unused field when formulating the
binary control word. To place the content of a register into the output terminals we place the
content of the register into the A input of the ALU, but none of the registers are selected to
accept the data.
The most efficient way to generate control words with a large number of bits is to store them in
a memory unit. A memory unit that stores control words is referred to as a control memory.
This type of control is referred to as micro programmed control.

ASSEMBLY LANGUAGE PROGRAMMING

Assembly Language:
• Alphanumeric equivalent of machine language
• Mnemonics more human-oriented than 1’s and 0’s
Assembler:
• Computer program that transliterates (one-to-one mapping)
assembly to machine language
• Computer’s native language is machine/assembly language

Why Assembly Language Programming ?

Faster and shorter programs.

• Compilers do not always generate optimum code.
Instruction set knowledge is important for machine
designers.
Compiler writers must be familiar with details of
machine language.
Small controllers embedded in many products
• Have specialized functions,
• Rely so heavily on input/output functionality,

CPU Registers (8086 microprocessor)

Fourteen 16-bit registers
Data Registers
• AX (Accumulator Register): AH and AL
• BX (Base Register): BH and BL
• CX (Count Register): CH and CL
• DX (Data Register): DH and DL
Pointer and Index Registers
• SI (Source Index)
• DI (Destination Index)
• SP (Stack Pointer)
• BP (Base Pointer)
• IP (Instruction Pointer)
 Segment Registers
• CS (Code Segment)
• DS (Data Segment)
• SS (Stack Segment)
• ES (Extra Segment)
FLAGS Register
• Zero flag
• Sign flag
• Parity flag
• Carry flag
• Overflow flag

INSTRUCTION FORMATS

A computer will usually have a variety of instruction code formats. It is the function of the
control unit within the CPU to interpret each instruction code and provide the necessary
control functions needed to process the instruction.

The bits of the instruction are divided into groups called fields. The most common fields found
in instruction formats are:

1. Mode field:
d: Specifies the way the effective address is determined
2. Operation code:e: Specifies the operations to be performed.
3. Address field: Designates a memory address or a processor register

The operation code field of an instruction is a group of bits that define various processor
operations, such as add, subtract, complement, and shift.
The bits that define the mode field of an instruction
instruction code specify a variety of alternatives for
choosing the operands from the given address.
 Operations specified by computer instructions are executed on some data stored in
memory or processor registers.
 Operands residing in memory are specified by their
the memory address.
 Operands residing in processor registers are specified with a register address
address.
A register address is a binary number of k bits that defines one of 2k registers in the CPU. Thus a
CPU with 16 processor registers R0 through R15 will have a register address field of 4 bits.

Most computers fall into one of 3 types of CPU organizations:

1. Single accumulator organization
2. General register organization
3. Stack organization

All operations are performed with an implied accumulator register. The instruction format in
this type of computer uses one address field.
 For example, the instruction that specifies an arithmetic addition is defined by an
assembly language instruction as
ADD X
Where X is the address of the operand. The ADD instruction in this case results in the
operation
AC AC + M[X]
AC is the accumulator register and M[X] symbolizes the memory word located at
address X
 The instruction format in this type of computer needs three register address fields.
ADD R1, R2, R3
to denote the operation R1  R2 + R3.
 The number of address fields in the instruction can be reduced from 3 to 2 if the
destination register is the same as one of the source registers.
ADD R1, R2
would denote the operation R1  R1 + R2. Only register addresses for R1 and R2 need
be specified in this instruction.
 Computers with multiple processor registers use the move instruction with a mnemonic
MOV to symbolize a transfer instruction.
MOV R1 , R2 denotes the transfer R1  R2

 General register type computers employ two or three address fields.

ADD R1, X
Would specify the operation R1  R1 + M[X]. It has two address fields, one for register
R1 and the other for the memory address X.
 Computers with stack organization would have PUSH and POP instructions which
require an address field.
PUSH X
will push the word at address X to the top of the stack. The stack pointer is updated
automatically.
 Operation type instructions do not need an address field in stack organized computers.
This is because the operation is performed on the two items that are on top of the stack.
Ie., ADD
 in a stack computer consists of an operation code only with no address field. This
operation has the effect of popping the two top numbers from the stack, adding the
numbers, and pushing the sum into the stack. There is no need to specify with an
address field since all operands are implied to be in the stack.

Some computers combine features from more than one organizational structure.
For Example, the intel 8080 microprocessor has 7 CPU registers, one of which is an accumulator
register. The processor has some of the characteristics of a general register type and some of
the characteristics of an accumulator type. Moreover, the intel 8080 processor has a stack
pointer and instructions to push and pop from a memory stack.

 To illustrate the influence of the number of addresses on computer programs, we will

evaluate the arithmetic statement
X = (A + B) * (C + D)
We will use the symbols ADD, SUB, MUL and DIV for the 4 arithmetic operations.
MOV for the transfer type operation
LOAD and STORE for transfers to and from memory and AC register.

We will assume that the operands are in memory addresses A,B,C, and D, and the result must be
stored in memory at address X
Three Address Instructions:
ADD R1, A, B ie., R1  M[A] + M[B]
ADD R2, C, D i.e., R2  M[C] + M[D]
MUL X, R1, R2 i.e., M[X]  R1 * R2
It is assumed that the computer has two processor registers, R1, and R2. The symbol M[A]
denotes the operand at memory address symbolized by A.

Two Address Instructions:

MOV R1, A ie., R1  M[A]
ADD R1, B i.e., R1  R1 + M[B]
MOV R2, C ie., R2  M[C]
ADD R2, D i.e., R2  R2 + M[D]
MUL R1, R2 i.e., R1  R1 * R2
MOV X, R1 i.e., M[X]  R1
One Address Instructions:
LOAD A ie., AC  M[A]
ADD B i.e., AC  AC + M[B]
STORE T i.e., M[T]  AC
LOAD C ie., AC  M[C]
ADD D i.e., AC  AC + M[D]
MUL T i.e., AC  AC * M[T]
STORE X i.e., M[X]  AC
All operations are done between the AC register and a memory operand. T is the address of a
temporary memory location required for storing the intermediate result.

Zero Address Instructions:

A stock organized computer does not use an address field for the instructions ADD and MUL.
The PUSH and POP instructions, however, need an address field to specify the operand that
communicates with the stack.
(TOS stands for top of stack)
PUSH A i.e., TOS  A
PUSH B i.e., TOS  B
ADD i.e., TOS  ( A + B ).
PUSH C i.e., TOS  C
PUCH D i.e., TOS  D
ADD i.e., TOS  ( C + D )
MUL i.e., TOS  ( C + D ) * ( A + B )