UCC28070-Q1

www.ti.com SLUSA71A – JULY 2010 – REVISED JUNE 2011

INTERLEAVING CONTINUOUS CONDUCTION MODE PFC CONTROLLER

Check for Samples: UCC28070-Q1

1FEATURES
• Qualified for Automotive Applications DESCRIPTION
• Interleaved Average Current-Mode PWM The UCC28070 is an advanced power factor
Control with Inherent Current Matching correction device that integrates two pulse-width
modulators (PWMs) operating 180° out of phase.
• Advanced Current Synthesizer Current
This interleaved PWM operation generates
Sensing for Superior Efficiency
substantial reduction in the input and output ripple
• Highly-Linear Multiplier Output with Internal currents, and the conducted-EMI filtering becomes
Quantized Voltage Feed-Forward Correction easier and less expensive. A significantly improved
for Near-Unity PF multiplier design provides a shared current reference
• Programmable Frequency (30 kHz to 300 kHz) to two independent current amplifiers that ensures
• Programmable Maximum Duty-Cycle Clamp matched average current mode control in both PWM
• Programmable Frequency Dithering Rate and outputs while maintaining a stable, low-distortion
Magnitude for Enhanced EMI Reduction sinusoidal input line current.
– Magnitude: 3 kHz to 30 kHz The UCC28070 contains multiple innovations
– Rate: Up to 30 kHz including current synthesis and quantized voltage
feed-forward to promote performance enhancements
• External Clock Synchronization Capability
in PF, efficiency, THD, and transient response.
• Enhanced Load and Line Transient Response Features including frequency dithering, clock
through Voltage Amplifier Output Slew-Rate synchronization, and slew rate enhancement further
Correction expand the potential performance enhancements.
• Programmable Peak Current Limiting
The UCC28070 also contains a variety of protection
• Bias-Supply UVLO, Over-Voltage Protection, features including output over-voltage detection,
Open-Loop Detection, and PFC-Enable programmable peak-current limit, under-voltage
Monitoring lockout, and open-loop protection.
• External PFC-Disable Interface
• Open-Circuit Protection on VSENSE and
VINAC pins
• Programmable Soft Start
• 20-Lead TSSOP Package

Simplified Application Diagram

VIN L1
D1 VOUT
+

COUT

12V to 21V
–

To CSB

CCDR
1 CDR DMAX 20 RDMX
RS T1
RRDM
2 RDM RT 19 RRT
RA
3 VAO SS 18
CSS M1
4 VSENSE GDB 17
5 VINAC GND 16
RIMO
6 IMO VCC 15
RB RSYN
7 RSYNTH GDA 14
L2
D2
8 CSB VREF 13
9 CSA CAOA 12
To CSA
10 PKLMT CAOB 11
RS T2
From Ixfrms
CZV CZC CZC RA
RPK1
CREF
CPV CPC CPC M2
RPK2
RB
RZV RZC RZC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
UCC28070-Q1
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ORDERING INFORMATION
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 125°C TSSOP – PW Reel of 2000 UCC28070QPWRQ1 28070Q

ABSOLUTE MAXIMUM RATINGS (1) (2) (3) (4)

over operating free-air temperature range (unless otherwise noted)

PARAMETER LIMIT UNIT
Supply voltage: VCC 22 V
Supply current: IVCC 20 mA
Voltage: GDA, GDB −0.5 to VCC+0.3 V
Gate drive current – continuous: GDA, GDB +/− 0.25 A
Gate drive current – pulsed: GDA, GDB +/− 0.75 A
Voltage: DMAX, RDM, RT, CDR, VINAC, VSENSE, SS, VAO, IMO, CSA, CSB,
−0.5 to +7 V
CAOA, CAOB, PKLMT, VREF
Current: RT, DMAX, RDM, RSYNTH −0.5 mA
Current: VREF, VAO, CAOA, CAOB, IMO 10 mA
Operating junction temperature, TJ −40 to +140 °C
Storage temperature, TSTG −65 to +150 °C
Lead temperature (10 seconds) 260

(1) These are stress limits. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at
these or any conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to
absolute maximum rated conditions for extended periods of time may affect device reliability.
(2) All voltages are with respect to GND.
(3) All currents are positive into the terminal, negative out of the terminal.
(4) In normal use, terminals GDA and GDB are connected to an external gate driver and are internally limited in output current.

DISSIPATION RATINGS
THERMAL
IMPEDANCE TA = 25°C POWER TA = 125°C POWER
PACKAGE TA = 85°C POWER RATING
JUNCTION-TO- RATING RATING
AMBIENT
(1) (2) (1) (1) (1)
20-Pin TSSOP (PW) 125°C/W and 800 mW 320 mW 120 mW

(1) Thermal resistance is a strong function of board construction and layout. Air flow reduces thermal resistance. This number is only a
general guide.
(2) Thermal resistance calculated with a low-K methodology.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
VCC Input Voltage (from a low-impedance source) VUVLO + 1 V 21 V
VREF Load Current 2 mA
VINAC Input Voltage Range 0 3
IMO Voltage Range 0 3.3 V
PKLMT, CSA, CSB Voltage Range 0 3.6
RSYNTH Resistance (RSYN) 15 750
kΩ
RDM Resistance (RRDM) 30 330

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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range −40°C < TA < 125°C, VCC = 12 V, GND = 0 V, RRT = 75 kΩ,
RDMX = 68.1 kΩ, RRDM = RSYN = 100 kΩ, CCDR = 2.2 nF, CSS = CVREF = 0.1 µF, CVCC = 1 µF, IVREF = 0 mA (unless otherwise
noted)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Bias Supply
(1)
VCCSHUNT VCC shunt voltage IVCC = 10 mA 23 25 27 V
VCC current, disabled VSENSE = 0 V 7
mA
VCC current, enabled VSENSE = 3 V (switching) 9 12
VCC = 7 V 200 µA
VCC current, UVLO
VCC = 9 V 4 6 mA
VUVLO UVLO turn-on threshold Measured at VCC (rising) 9.8 10.2 10.6
UVLO hysteresis Measured at VCC (falling) 1 V
VREF enable threshold Measured at VCC (rising) 7.5 8 8.5
Linear Regulator
VREF voltage, no load IVREF = 0 mA 5.82 6 6.18 V
Measured as the change in VREF,
VREF load rejection -12 12
(IVREF = 0 mA and −2 mA)
Measured as the change in VREF, TA = 25°C -12 12 mV
VREF line rejection (VCC = 11V and 20 V, IVREF = 0
µA) TA = -40°C to 125°C -16 16
PFC Enable
VEN Enable threshold Measured at VSENSE (rising) 0.65 0.75 0.85
V
Enable hysteresis 0.15
External PFC Disable
Disable threshold Measured at SS (falling) 0.5 0.6
V
Hysteresis VSENSE > 0.85 V 0.15
Oscillator
Output phase shift Measured between GDA and GDB 179 180 181 °
VDMAX,VRT
, and Timing regulation voltages Measured at DMAX, RT, & RDM 2.91 3 3.09 V
VRDM
RRT = 75 kΩ, RDMX = 68.1 kΩ,
94 100 105
VRDM = 0 V, VCDR = 6 V
fPWM PWM switching frequency kHz
RRT = 24.9 kΩ, RDMX = 22.6 kΩ,
270 290 330
VRDM = 0 V, VCDR = 6 V
RRT = 75 kΩ, RDMX = 68.1 kΩ,
DMAX Duty-cycle clamp 92% 95% 98%
VRDM = 0 V, VCDR = 6 V
Minimum programmable RRT = 24.9 kΩ, RDMX = 22.6 kΩ,
50 150 250 ns
off-time VRDM = 0 V, VCDR = 6 V
Frequency dithering magnitude RRDM = 316 kΩ, RRT = 75 kΩ 1 3 4.3
fDM
change in fPWM RRDM = 31.6 kΩ, RRT = 24.9 kΩ 23 30 36
kHz
Frequency dithering rate rate of CCDR = 2.2 nF, RRDM = 100 kΩ 3
fDR
change in fPWM CCDR = 0.3 nF, RRDM = 100 kΩ 20
Dither rate current Measure at CDR (sink and source) ±10 µA
ICDR
Dither disable threshold Measured at CCDR (rising) 5 5.25 V

(1) Excessive VCC input voltage and/or current damages the device. This clamp will not protect the device from an unregulated supply. If
an unregulated supply is used, a series-connected fixed positive voltage regulator such as a UA78L15A is recommended. See the
Absolute Maximum Ratings section for the limits on VCC voltage and current.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range −40°C < TA < 125°C, VCC = 12 V, GND = 0 V, RRT = 75 kΩ,
RDMX = 68.1 kΩ, RRDM = RSYN = 100 kΩ, CCDR = 2.2 nF, CSS = CVREF = 0.1 µF, CVCC = 1 µF, IVREF = 0 mA (unless otherwise
noted)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Clock Synchronization
VCDR SYNC enable threshold Measured at CDR (rising) 5 5.25 V
SYNC propagation delay VCDR = 6 V, Measured from RDM (rising) to GDx (rising) 50 100 ns
SYNC threshold (Rising) VCDR = 6 V, Measured at RDM 1.2 1.5
V
SYNC threshold (Falling) VCDR = 6 V, Measured at RDM 0.4 0.7
Positive pulse width 0.2 μs
SYNC pulses (2)
Maximum duty cycle 50 %
Voltage Amplifier
VSENSE voltage In regulation, TA = 25°C 2.94 3 3.06
V
VSENSE voltage In regulation 2.84 3 3.10
VSENSE input bias current In regulation 250 500 nA
VAO high voltage VSENSE = 2.9 V 4.8 5 5.2
V
VAO low voltage VSENSE = 3.1 V 0.05 0.50
gMV VAO transconductance 2.8 V < VSENSE < 3.2 V, VAO = 3 V 70 μs
VAO sink current, overdriven
VSENSE = 3.5 V, VAO = 3 V 30
limit
VAO source current, overdriven VSENSE = 2.5 V, VAO = 3 V, SS = 3 V −30 μA
VAO source current,
VSENSE = 2.5 V, VAO = 3 V −130
overdriven limit + ISRC
Slew-rate correction threshold Measured as VSENSE (falling) / VSENSE (regulation) 92 93 95 %
Slew-rate correction hysteresis Measured at VSENSE (rising) 3 9 mV
ISRC Slew-rate correction current Measured at VAO, in addition to VAO source current. −100 μA
Slew-rate correction enable
Measured at SS (rising) 4 V
threshold
VAO discharge current VSENSE = 0.5 V, VAO = 1 V 10 μA
Soft Start
ISS SS source current VSENSE = 0.9 V, SS = 1 V −10 μA
Adaptive source current VSENSE = 2.0 V, SS = 1 V −1.5 -2.5 mA
Adaptive SS disable Measured as VSENSE – SS -30 0 30 mV
SS sink current VSENSE = 0.5 V, SS = 0.2 V 0.5 0.9 mA

(2) Due to the influence of the synchronization pulse width on the programmability of the maximum PWM switching duty cycle (DMAX) it is
recommended to minimize the synchronization signal's duty cycle.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range −40°C < TA < 125°C, VCC = 12 V, GND = 0 V, RRT = 75 kΩ,
RDMX = 68.1 kΩ, RRDM = RSYN = 100 kΩ, CCDR = 2.2 nF, CSS = CVREF = 0.1 µF, CVCC = 1 µF, IVREF = 0 mA (unless otherwise
noted)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Over Voltage
VOVP OVP threshold Measured as VSENSE (rising) / VSENSE (regulation) 104 106 108 %
OVP hysteresis Measured at VSENSE (falling) 100 mV
OVP propagation delay Measured between VSENSE (rising) and GDx (falling) 0.2 0.3 μs
Zero-Power
VZPWR Zero-power detect threshold Measured at VAO (falling) 0.65 0.75
V
Zero-power hysteresis 0.15
Multiplier
VAO ≥ 1.5 V, TA = 25°C 15.4 17 20
VAO = 1.2 V, TA = 25°C 13.5 17.0 20.5
kMULT Gain constant
VAO ≥ 1.5 V 14 17 22
μA
VAO = 1.2 V 12 17 22.5
VINAC = 0.9 VPK, VAO = 0.8 V -0.2 0 0.2
IIMO Output current: zero
VINAC = 0 V, VAO = 5 V -0.2 0 0.2
Quantized Voltage Feed Forward
(3)
VLVL1 Level 1 threshold 0.6 0.7 0.8
VLVL2 Level 2 threshold 1
VLVL3 Level 3 threshold 1.2
VLVL4 Level 4 threshold 1.4
Measured at VINAC (rising) V
VLVL5 Level 5 threshold 1.65
VLVL6 Level 6 threshold 1.95
VLVL7 Level 7 threshold 2.25
VLVL8 Level 8 threshold 2.6
Current Amplifiers
CAOx high voltage 5.75 6
V
CAOx low voltage 0.1
gMC CAOx transconductance 100 μs
CAOx sink current, overdriven 50
CAOx source current, μA
−50
overdriven
Input common mode range 0 3.6 V
RSYNTH = 6 V, TA = 25°C -16 -8 0
Input offset Voltage mV
RSYNTH = 6 V -50 -8 40
Input offset voltage -50 −8 40
Measured as Phase A's input TA = 25°C -12 0 12 mV
Phase mismatch
offset minus Phase B's input offset TA = -40°C to 125°C -20 14
CAOx pulldown current VSENSE = 0.5 V, CAOx = 0.2 V 0.5 0.9 mA

(3) The Level 1 threshold represents the "zero-crossing detection" threshold above which VINAC must rise to initiate a new input half-cycle,
and below which VINAC must fall to terminate that half-cycle.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range −40°C < TA < 125°C, VCC = 12 V, GND = 0 V, RRT = 75 kΩ,
RDMX = 68.1 kΩ, RRDM = RSYN = 100 kΩ, CCDR = 2.2 nF, CSS = CVREF = 0.1 µF, CVCC = 1 µF, IVREF = 0 mA (unless otherwise
noted)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Synthesizer
VSENSE = 3 V, VINAC = 0 V 2.91 3 3.09
VRSYNTH Regulation voltage
VSENSE = 3 V, VINAC = 2.85 V 0.10 0.15 0.20 V
Synthesizer disable threshold Measured at RSYNTH (rising) 5 5.25
VINAC input bias current 0.250 0.500 μA
Peak Current Limit
Peak current limit threshold PKLMT = 3.30 V, measured at CSx (rising) 3.27 3.3 3.33 V
Peak current limit propagation
Measured between CSx (rising) and GDx (falling) edges 60 100 ns
delay
PWM Ramp
VRMP PWM ramp amplitude 3.8 4.0 4.2
V
PWM ramp offset voltage TA = 25°C, RRT = 75 kΩ 0.55 0.7
PWM ramp offset temperature
−2 mV/°C
coefficient
Gate Drive
GDA, GDB output voltage,
VCC = 20 V, CLOAD = 1 nF 11.5 13 15
high, clamped
V
GDA, GDB output voltage, High CLOAD = 1 nF 10 10.5
GDA, GDB output voltage, Low CLOAD = 1 nF 0.2 0.3
Rise time GDx 1 V to 9 V, CLOAD = 1 nF 18 30
ns
Fall time GDx 9 V to 1 V, CLOAD = 1 nF 12 25
GDA, GDB output voltage,
VCC = 0 V, IGDA, IGDB = 2.5 mA 0.7 2 V
UVLO
Thermal Shutdown
Thermal shutdown threshold 160
°C
Thermal shutdown recovery 140

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DEVICE INFORMATION
PW PACKAGE
(TOP VIEW)

CDR 1 20 DMAX
RDM 2 19 RT
VAO 3 18 SS
VSENSE 4 17 GDB
VINAC 5 16 GND
IMO 6 15 VCC
RSYNTH 7 14 GDA
CSB 8 13 VREF
CSA 9 12 CAOA
PKLMT 10 11 CAOB

TERMINAL FUNCTIONS
NAME PIN # I/O DESCRIPTION
Dither Rate Capacitor. Frequency-dithering timing pin. An external capacitor to GND programs
CDR 1 I
the rate of oscillator dither. Connect the CDR pin to the VREF pin to disable dithering.
Dither Magnitude Resistor. Frequency-dithering magnitude and external synchronization pin. An
external resistor to GND programs the magnitude of oscillator frequency dither. When frequency
RDM
2 I dithering is disabled (CDR > 5 V), the internal master clock will synchronize to positive edges
(SYNC)
presented on the RDM pin. Connect RDM to GND when dithering is disabled and synchronization
is not desired.
Voltage Amplifier Output. Output of transconductance voltage error amplifier. Internally
VAO 3 O connected to Multiplier input and Zero-Power comparator. Connect the voltage regulation loop
compensation components between this pin and GND.
Output Voltage Sense. Internally connected to the inverting input of the transconductance
voltage error amplifier in addition to the positive terminal of the Current Synthesis difference
VSENSE 4 I
amplifier. Also connected to the OVP, PFC Enable, and slew-rate comparators. Connect to PFC
output with a resistor-divider network.
Scaled AC Line Input Voltage. Internally connected to the Multiplier and negative terminal of the
VINAC 5 I Current Synthesis difference amplifier. Connect a resistor-divider network between VIN, VINAC,
and GND identical to the PFC output divider network connected at VSENSE.
Multiplier Current Output. Connect a resistor between this pin and GND to set the multiplier
IMO 6 O
gain.
Current Synthesis Down-Slope Programming. Connect a resistor between this pin and GND to
RSYNTH 7 I set the magnitude of the current synthesizer down-slope. Connecting RSYNTH to VREF will
disable current synthesis and connect CSA and CSB directly to their respective current amplifiers.
Phase B Current Sense Input. During the on-time of GDB, CSB is internally connected to the
CSB 8 I
inverting input of Phase B's current amplifier through the current synthesis stage.
Phase A Current Sense Input. During the on-time of GDA, CSA is internally connected to the
CSA 9 I
inverting input of Phase A's current amplifier through the current synthesis stage.
Peak Current Limit Programming. Connect a resistor-divider network between VREF and this
PKLMT 10 I pin to set the voltage threshold of the cycle-by-cycle peak current limiting comparators. Allows
adjustment for desired ΔILB.
Phase B Current Amplifier Output. Output of phase B's transconductance current amplifier.
Internally connected to the inverting input of phase B's PWM comparator for trailing-edge
CAOB 11 O
modulation. Connect the current regulation loop compensation components between this pin and
GND.
Phase A Current Amplifier Output. Output of phase A's transconductance current amplifier.
Internally connected to the inverting input of phase A's PWM comparator for trailing-edge
CAOA 12 O
modulation. Connect the current regulation loop compensation components between this pin and
GND.
6-V Reference Voltage and Internal Bias Voltage. Connect a 0.1-μF ceramic bypass capacitor
VREF 13 O
as close as possible to this pin and GND.
Phase A's Gate Drive. This limited-current output is intended to connect to a separate gate-drive
GDA 14 O device suitable for driving the Phase A switching component(s). The output voltage is typically
clamped to 13.5 V.
Bias Voltage Input. Connect a 0.1-μF ceramic bypass capacitor as close as possible to this pin
VCC 15 I
and GND.

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TERMINAL FUNCTIONS (continued)

NAME PIN # I/O DESCRIPTION
Device Ground Reference. Connect all compensation and programming resistor and capacitor
GND 16 I/O networks to this pin. Connect this pin to the system through a separate trace for high-current
noise isolation.
Phase B's Gate Drive. This limited-current output is intended to connect to a separate
GDB 17 O gate-drivedevice suitable for driving the Phase B switching component(s). The output voltage is
typically clamped to 13.5 V.
Soft-Start and External Fault Interface. Connect a capacitor to GND on this pin to set the
soft-start slew rate based on an internally-fixed 10-μA current source. The regulation reference
voltage for VSENSE is clamped to VSS until VSS exceeds 3 V. Upon recovery from certain fault
SS 18 I
conditions a 1-mA current source is present at the SS pin until the SS voltage equals the
VSENSE voltage. Pulling the SS pin below 0.6 V immediately disables both GDA and GDB
outputs.
Timing Resistor. Oscillator frequency programming pin. A resistor to GND sets the running
RT 19 I
frequency of the internal oscillator.
Maximum Duty-Cycle Resistor. Maximum PWM duty-cycle programming pin. A resistor to GND
DMAX 20 I
sets the PWM maximum duty-cycle based on the ratio of RDMX/RRT.

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Functional Block Diagram

OVP
+ VSENSE
VCC 15 Fault 3.18V
3.08V
25V 0.75V
ReStart Ext.Disable +
160 On o ThermSD 0.60V

Linear EN + 140 Off C SS

VREF 13 6V Regulator 8V
0.75V
S Q
+
0.60V
VSENSE R Q
0.90V
GND 16 UVLO ZeroPwr + 0.75V
10.2V
9.2V
+ VAO

6 IMO

5 VINAC
DMAX 20 Voltage 250nA
Feed-
CLKA
Forward
Oscillator w/ VVINAC * (VVAO – 1)
CLKB IIMO = * 17uA
RT 19 Freq. Dither KVFF KVFF
OffA x
OffB Mult. /
x 3 VAO

RDM/ SYNC ReStart + SS

2 Logic 100uA
SYNC 4V
5V Slew Rate
Correction 2.8V
SYNC Dither +
10uA
CDR 1 + Enable Disable
5V

GmAmp
- 4 VSENSE
VA + 3V
+
250nA
Adaptive SS
PKLMT 10 IpeakA ReStart 1mA
ISS
+ 10uA
+
Control
ReStart
Logic
Ext.Disable
IpeakB
CSA 9
+ + PWM1 18 SS
CA1
VCC
GmAmp + S Q
(Clamped at 13.5V)
OutA
CSB 8 OutB
OffA CLKA R Q Driver 14 GDA
Current IpeakA

Synthesizer Fault GND

RSYNTH 7 Disable + PWM2
CA2 VCC
+ VINAC
+ S Q
5V VSENSE GmAmp (Clamped at 13.5V)
OffB
IpeakB
CLKB R Q Driver 17 GDB
CAOA 12

Fault
GND
CAOB 11

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TYPICAL CHARACTERISTICS
SUPPLY CURRENT REFERENCE VOLTAGE
vs vs
TEMPERATURE TEMPERATURE
12 6.18

10 IVCC, VCC = 12 V, enabled 6.12

VREF - Reference Voltage - V

IVCC - Supply Current - mA

8 6.06
VREF (IVREF = 0 mA)

6 IVCC, VCC = 12 V, disabled 6.00

4 5.94

2 5.88

0 5.82
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -10 40 90 140
TJ - Temperature - 0C TJ - Temperature - 0C
Figure 1. Figure 2.

IVSENSE BIAS CURRENT

VSENSE REGULATION
vs
vs
TEMPERATURE
TEMPERATURE
0.50
3.06
0.45

3.04 0.40
IVSENSE - Bias Current - mA

0.35
VSENSE Regulation - V

3.02
0.30

3.00 0.25

0.20
2.98 0.15

0.10
2.96
0.05

2.94 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -10 40 90 140
TJ - Temperature - 0C TJ - Temperature - 0C

Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS (continued)

MULTIPLIER OUTPUT CURRENT
MULTIPIER CONSTANT
vs
vs
VOLTAGE AMPLIFIER OUTPUT
TEMPERATURE
180
20
QVFF Level
160
Level 1
IMO - Multiplier Output Current - mA

19
140 Level 2
Level 3

Multiplier Constant - mA
120 18 VAO = 3.0 V VAO = 5.0 V
Level 4

100 Level 5
Level 6 17
80 Level 7
Level 8
60 16 VAO = 1.5 V

40
15 VAO = 1.2 V
20

0 14
0 1 2 3 4 5 6 -60 -40 -20 0 20 40 60 80 100 120 140
VAO - Voltage Amplifier Output - V TJ - Temperature - 0C

Figure 5. Figure 6.

IVINAC BIAS CURRENT SWITCHING FREQUENCY (normalized change)

vs vs
TEMPERATURE TEMPERATURE
1.0
0.50
Normalized Change in Switching Frequency - %

0.8 Typical Frequency= 30 kHz

0.45 RT = 249 k?

0.5 Typical Frequency= 100 kHz

0.40 VINAC = 2.85 V
RT = 75 k?
VINAC = 2.5 V
IVINAC - Bias Current - mA

0.35 0.3

0.30 0

0.25 -0.3
Typical Frequency= 290 kHz
RT = 24.9 k?
0.20 -0.5

0.15 VINAC = 1.0 V

-0.8
VINAC = 0.2 V
VINAC = 2.0 V
0.10 -1.0
-60 -40 -20 0 20 40 60 80 100 120 140
0.05
TJ - Temperature - 0C
0.00
-60 -10 40 90 140
TJ - Temperature - 0C
Figure 7. Figure 8.

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TYPICAL CHARACTERISTICS (continued)

VOLTAGE AMPLIFIER TRANSFER FUNCTION
VOLTAGE AMPLIFIER TRANSCONDUCTANCE
vs
vs
VSENSE
TEMPERATURE
40
80
VAO - Voltage Amplifier Transconductance - mS

IVAO - Voltage Amplifier Output Current - mA

20
75
0

70 -20

-40
65
-60

60 -80

-100
55
-120

50 -140
-60 -40 -20 0 20 40 60 80 100 120 140 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
TJ - Temperature - 0C VSENSE - V

Figure 9. Figure 10.

CURRENT AMPLIFIER TRANSCONDUCTANCE

vs
TEMPERATURE
110

105
CAOx Transconductance - mS

100

95

90

85

80
-60 -40 -20 0 20 40 60 80 100 120 140
TJ - Temperature - 0C

Figure 11.

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TYPICAL CHARACTERISTICS (continued)

CAx INPUT OFFSET VOLTAGE CA1 TO CA2 RELATIVE OFFSET
vs vs
TEMPERATURE (at 0.8 V common mode) TEMPERATURE (at 0.8 V common mode)
5 15

CA1 to CA2 Relative Offset Voltage - mV

CAx +3s 10 A-B +3s
0
CAx Input Offset - mV

5
-5

-10 CAx AVG A-B AVG

-5

-15 CAx -3s A-B -3s

-10

-20 -15
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
TJ - Temperature - 0C TJ - Temperature - 0C
Figure 12. Figure 13.

CAx INPUT OFFSET VOLTAGE CA1 TO CA2 RELATIVE OFFSET

vs vs
TEMPERATURE (at 2.0 V common mode) TEMPERATURE (at 2.0 V common mode)
5 15
CA1 to CA2 Relative Offset Voltage - mV

10
0
A-B +3s
CAx +3s
CAx Input Offset - mV

5
-5

-10 CAx AVG A-B AVG

-5

-15 CAx -3s

-10 A-B -3s

-20 -15
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
TJ - Temperature - 0C TJ - Temperature - 0C

Figure 14. Figure 15.

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TYPICAL CHARACTERISTICS (continued)

CAx INPUT OFFSET VOLTAGE CA1 TO CA2 RELATIVE OFFSET
vs vs
TEMPERATURE (at 3.6 V common mode) TEMPERATURE (at 3.6 V common mode)
5 15

CA1 to CA2 Relative Offset Voltage - mV

10
0
A-B +3s
CAx +3s
CAx Input Offset - mV

5
-5

-10 CAx AVG

-5 A-B AVG

-15 CAx -3s

-10 A-B -3s

-20 -15
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
TJ - Temperature - 0C TJ - Temperature - 0C
Figure 16. Figure 17.

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APPLICATION INFORMATION

THEORY OF OPERATION

Interleaving
One of the main benefits from the 180° interleaving of phases is significant reductions in the high-frequency
ripple components of both the input current and the current into the output capacitor of the PFC pre-regulator.
Compared to that of a single-phase PFC stage of equal power, the reduced ripple on the input current eases the
burden of filtering conducted-EMI noise and helps reduce the EMI filter and CIN sizes. Additionally, reduced
high-frequency ripple current into the PFC output capacitor, COUT, helps to reduce its size and cost. Furthermore,
with reduced ripple and average current in each phase, the boost inductor size can be smaller than in a
single-phase design [1].
Ripple current reduction due to interleaving is often referred to as "ripple cancellation", but strictly speaking, the
peak-to-peak ripple is completely cancelled only at 50% duty-cycle in a 2-phase system. At duty-cycles other
than 50%, ripple reduction occurs in the form of partial cancellation due to the superposition of the individual
phase currents. Nevertheless, compared to the ripple currents of an equivalent single-phase PFC pre-regulator,
those of a 2-phase interleaved design are extraordinarily smaller [1]. Independent of ripple cancellation, the
frequency of the interleaved ripple, at both the input and output, is 2 x fPWM.
On the input, 180° interleaving reduces the peak-to-peak ripple amplitude to 1/2 or less of the ripple amplitude of
the equivalent single-phase current.
On the output, 180° interleaving reduces the rms value of the PFC-generated ripple current in the output
capacitor by a factor of slightly more than √2, for PWM duty-cycles > 50%.
This can be seen in the following derivations, adapting the method by Erickson [2].
In a single-phase PFC pre-regulator, the total rms capacitor current contributed by the PFC stage at all
duty-cycles can be shown to be approximated by:

æ I ö æ æ 16VO ö 2
ö
iCRMS 1j = ç O ÷ ç ç ÷ - 1h ÷÷
è h ø èç è 3p VM ø ø (1)
In a dual-phase interleaved PFC pre-regulator, the total rms capacitor current contributed by the PFC stage for D
> 50% can be shown to be approximated by:

æ I ö æ æ 16VO ö 2
ö
iCRMS 2j = ç O ÷ ç ç ÷ - 1h ÷÷
è h ø çè è 6p VM ø ø (2)
In these equations, IO = average PFC output load current, VO = average PFC output voltage, VM = peak of the
input ac-line voltage, and η = efficiency of the PFC stage at these conditions. It can be seen that the quantity
under the radical for iCrms2φ is slightly smaller than 1/2 of that under the radical for iCrms1φ. The rms currents
shown contain both the low-frequency and the high-frequency components of the PFC output current.
Interleaving reduces the high-frequency component, but not the low-frequency component.

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Programming the PWM Frequency and Maximum Duty-Cycle Clamp

The PWM frequency and maximum duty-cycle clamps for both GDx outputs of the UCC28070 are set through
the selection of the resistors connected to the RT and DMAX pins, respectively. The selection of the RT resistor
(RRT) directly sets the PWM frequency (fPWM).
7500
RRT (k W ) =
f PWM (kHz )
(3)
Once RRT has been determined, the DMAX resistor (RDMX) may be derived.
RDMX = RRT ´ (2 ´ DMAX - 1)
(4)
where DMAX is the desired maximum PWM duty-cycle.

Frequency Dithering (Magnitude and Rate)

Frequency dithering refers to modulating the switching frequency to achieve a reduction in conducted-EMI noise
beyond the capability of the line filter alone. The UCC28070 implements a triangular modulation method which
results in equal time spent at every point along the switching frequency range. This total range from minimum to
maximum frequency is defined as the dither magnitude, and is centered around the nominal switching frequency
fPWM set with RRT. For example, a dither magnitude of 20 kHz on a nominal fPWM of 100 kHz results in a
frequency range of 100 kHz ±10 kHz. Furthermore, the programmed duty-cycle clamp set by RDMX remains
constant at the programmed value across the entire range of the frequency dithering.
The rate at which fPWM traverses from one extreme to the other and back again is defined as the dither rate. For
example, a dither rate of 1 kHz would linearly modulate the nominal frequency from 110 kHz to 90 kHz to 110
kHz once every millisecond. A good initial design target for dither magnitude is ±10% of fPWM. Most boost
components can tolerate such a spread in fPWM. The designer can then iterate around there to find the best
compromise between EMI reduction, component tolerances, and loop stability.
The desired dither magnitude is set by a resistor from the RDM pin to GND, of value calculated by the following
equation:
937.5
RRDM (k W ) =
f DM (kHz )
(5)
Once the value of RRDM is determined, the desired dither rate may be set by a capacitor from the CDR pin to
GND, of value calculated by the following equation:
æ R ( kW ) ö
CCDR ( pF ) = 66.7 ´ ç RDM ÷
è f DR ( kHz ) ø (6)
Frequency dithering may be fully disabled by forcing the CDR pin > 5 V or by connecting it to VREF (6 V) and
connecting the RDM pin directly to GND. (If populated, the relatively high impedance of the RDM resistor may
allow system switching noise to couple in and interfere with the controller timing functions if not bypassed with a
low impedance path when dithering is disabled.)
If an external frequency source is used to synchronize fPWM and frequency dithering is desired, the external
frequency source must provide the dither magnitude and rate functions as the internal dither circuitry is disabled
to prevent undesired performance during synchronization. (See following section for more details.)

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External Clock Synchronization

The UCC28070 has also been designed to be easily synchronized to almost any external frequency source. By
disabling frequency dithering (pulling CDR > 5 V), the UCC28070's SYNC circuitry is enabled permitting the
internal oscillator to be synchronized with pulses presented on the RDM pin. In order to ensure a precise 180
degree phase shift is maintained between the GDA and GDB outputs, the frequency (fSYNC) of the pulses
presented at the RDM pin needs to be at twice the desired fPWM. For example, if a 100-kHz switching frequency
is desired, the fSYNC should be 200 kHz.
f SYNC
f PWM =
2 (7)
In order to ensure the internal oscillator does not interfere with the SYNC function, RRT should be sized to set the
internal oscillator frequency at least 10% below the fSYNC.
15000
RRT (k W ) = ´ 1 .1
f SYNC (kHz )
(8)
It must be noted that the PWM modulator gain will be reduced by a factor equivalent to the scaled RRT due to a
direct correlation between the PWM ramp current and RRT. Adjustments to the current loop gains should be
made accordingly.
It must also be noted that the maximum duty cycle clamp programmability is affected during external
synchronization. The internal timing circuitry responsible for setting the maximum duty cycle is initiated on the
falling edge of the synchronization pulse. Therefore, the selection of RDMX becomes dependent on the
synchronization pulse width (tSYNC).
DSYNC = tSYNC ´ f SYNC
(9)
For use in RDMX equation immediately below.
æ 15000 ö
RDMX (k W ) = ç ÷ ´ (2 ´ DMAX - 1 - DSYNC )
è f SYNC ( kHz ) ø (10)
Consequently to minimize the impact of the tSYNC it is clearly advantageous to utilize the smallest synchronization
pulse width feasible.

NOTE
When external synchronization is used, a propagation delay of approximately 50 ns to 100
ns exists between internal timing circuits and the SYNC signal's falling edge, which may
result in reduced off-time at the highest of switching frequencies. Therefore, RDMX should
be adjusted downward slightly by (TSYNC-0.1 μs)/TSYNC to compensate. At lower SYNC
frequencies, this delay becomes an insignificant fraction of the PWM period, and can be
neglected.

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Multi-phase Operation
External synchronization also facilitates using more than 2 phases for interleaving. Multiple UCC28070s can
easily be paralleled to add an even number of additional phases for higher-power applications. With appropriate
phase-shifting of the synchronization signals, even more input and output ripple current cancellation can be
obtained. (An odd number of phases can be accommodated if desired, but the ripple cancellation would not be
optimal.) For 4-, 6-, or any 2 x n-phases (where n = the number of UCC28070 controllers), each controller should
receive a SYNC signal which is 360/n degrees out of phase with each other. For a 4-phase application
interleaving with two controllers, SYNC1 should be 180° out of phase with SYNC2 for optimal ripple cancellation.
Similarly for a 6-phase system, SYNC1, SYNC2, and SYNC3 should be 120° out of phase with each other for
optimal ripple cancellation.
In a multi-phase interleaved system, each current loop is independent and treated separately, however there is
only one common voltage loop. To maintain a single control loop, all VSENSE, VINAC, SS, IMO and VAO
signals are paralleled, respectively between the n controllers. Where current-source outputs are combined (SS,
IMO, VAO), the calculated load impedances must be adjusted by 1/n to maintain the same performance as with
a single controller.
Figure 18 illustrates the paralleling of two controllers for a 4-phase 90°-interleaved PFC system.

VSENSE and VINAC Resistor Configuration

The primary purpose of the VSENSE input is to provide the voltage feedback from the output to the voltage
control loop. Thus, a traditional resistor-divider network needs to be sized and connected between the output
capacitor and the VSENSE pin to set the desired output voltage based on the 3-V regulation voltage on
VSENSE.
A unique aspect of the UCC28070 is the need to place the same resistor-divider network on the VIN side of the
inductor to the VINAC pin. This provides the scaled input voltage monitoring needed for the linear multiplier and
current synthesizer circuitry. It is not required that the actual resistance of the VINAC network be identical to the
VSENSE network, but it is necessary that the attenuation (kR) of the two divider networks be equivalent for
proper PFC operation.
RB
kR =
(RA + RB ) (11)
In noisy environments, it may be beneficial for small filter capacitors to be applied to the VSENSE and VINAC
inputs to avoid the destabilizing effects of excessive noise on these inputs. If applied, the RC time-constant
should not exceed 100μs on the VSENSE input to avoid significant delay in the output transient response. The
RC time-constant should also not exceed 100 μs on the VINAC input to avoid degrading of the wave-shape
zero-crossings. Usually, a time constant of 3/fPWM is adequate to filter out typical noise on VSENSE and VINAC.
Some design and test iteration may be required to find the optimal amount of filtering required in a particular
application.

VSENSE and VINAC Open Circuit Protection

Both the VSENSE and VINAC pins have been designed with an internal 250-nA current sink to ensure that in the
event of an open circuit at either pin, the voltage is not left undefined, and the UCC28070 remains in a "safe"
operating mode.

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V IN L1
D1
– +

To CSB1

RDMX1 T1
VREF1 RS1
1 CDR DMAX 20
2 RDM RT 19
RRT1
3 VAO SS 18
RA
M1
4 VSENSE GDB 17
5 VINAC GND 16
6 IMO VCC 15 12V to 21V
RB
7 RSYNTH GDA 14
CSB1 L2
VREF1 D2
8 CSB VREF 13
From Ixfrms
9 CSA CAOA 12
CSA1 To CSA1
10 PKLMT CAOB 11

RS 2 T2
RSYN1

M2

CZV RPK1 CZC CZC

CREF
RIMO

CPV CPC CPC

RPK2 CSS

RZV RZC RZC VOUT

RZC RZC RA
COUT

CPC CPC
CREF RB
CZC CZC

Vin L3
D3

To CSA2
RSYN2

RS 3 T3
10 PKLMT CAOB 11
CSB2
9 CSA CAOA 12
From Ixfrms
VREF2
8 CSB VREF 13
CSA2 M3
7 RSYNTH GDA 14
6 IMO VCC 15 12V to 21V

5 VINAC GND 16
4 VSENSE GDB 17
L4
D4
3 VAO SS 18
RRT2
2 RDM RT 19
To CSB2
1 CDR DMAX 20
RDMX2
Synchronized RS 4 T4
Clocks
w/ 180 o
Phase Shift
M4

Figure 18. Simplified Four-Phase Application Diagram Using Two UCC28070

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Current Synthesizer
One of the most prominent innovations in the UCC28070 design is the current synthesizer circuitry that
synchronously monitors the instantaneous inductor current through a combination of on-time sampling and
off-time down-slope emulation.
During the on-time of the GDA and GDB outputs, the inductor current is recorded at the CSA and CSB pins
respectively via the current transformer network in each output phase. Meanwhile, the continuous monitoring of
the input and output voltage via the VINAC and VSENSE pins permits the UCC28070 to internally recreate the
inductor current's down-slope during each output's respective off-time. Through the selection of the RSYNTH
resistor (RSYN), based on the equation below, the internal response may be adjusted to accommodate the wide
range of inductances expected across the wide array of applications.
During inrush surge events at power-up and ac drop-out recovery, VSENSE < VINAC, so the synthesized down
slope becomes zero. In this case, the synthesized inductor current will remain above the IMO reference and the
current loop drives the duty cycle to zero. This avoids excessive stress on the MOSFETS during the surge event.
Once VINAC falls below VSENSE the duty cycle increases until steady-state operation resumes.

Waveform at Synthesized
CSx input down-slope

Current Synthesizer
output to CA

Figure 19. Inductor Current's Down Slope

RSYN (k W ) =
(10 ´ N CT ´ LB (m H )´ k R )
RS (W )
(12)
Variables
• LB = Nominal Zero-Bias Boost Inductance (μH),
• RS = Sense Resistor (Ω),
• NCT = Current-sense Transformer turns ratio,
• kR = RB/(RA+RB) = the resistor-divider attenuation at the VSENSE and VINAC pins.

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Programmable Peak Current Limit

The UCC28070 has been designed with a programmable cycle-by-cycle peak current limit dedicated to disabling
either GDA or GDB output whenever the corresponding current-sense input (CSA or CSB respectively) rises
above the voltage established on the PKLMT pin. Once an output has been disabled via the detection of peak
current limit, the output remains disabled until the next clock cycle initiates a new PWM period. The programming
range of the PKLMT voltage extends to upwards of 4 V to permit the full utilization of the 3-V average current
sense signal range, however it should be noted that the linearity of the current amplifiers begin to compress
above 3.6 V.
A resistor-divider network from VREF to GND can easily program the peak current limit voltage on PKLMT,
provided the total current out of VREF is less than 2 mA to avoid drooping of the 6-V VREF voltage. A load of
less than 0.5 mA is suggested, but if the resistance on PKLMT is very high, a small filter capacitor on PKLMT is
recommended to avoid operational problems in high-noise environments.

PKLMT
Externally Programmable Peak
Current Limit level (PKLMT) 10
IPEAKx
+ To Gate-Drive
Shut-down

CSx
DI Current To Current
Synthesizer Amplifier

3V Average Current-sense
Signal Range, plus Ripple

Figure 20. Externally Programmable Peak Current Limit

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Linear Multiplier
The multiplier of the UCC28070 generates a reference current which represents the desired wave shape and
proportional amplitude of the ac input current. This current is converted to a reference voltage signal by the RIMO
resistor, which is scaled in value to match the voltage of the current-sense signals. The instantaneous multiplier
current is dependent upon the rectified, scaled input voltage VVINAC and the voltage-error amplifier output VVAO.
The VVINAC signal conveys three pieces of information to the multiplier:
1. The overall wave-shape of the input voltage (typically sinusoidal),
2. The instantaneous input voltage magnitude at any point in the line cycle,
3. The rms level of the input voltage.
The VVAO signal represents the total output power of the PFC pre-regulator.
A major innovation in the UCC28070 multiplier architecture is the internal quantized VRMS feed-forward (QVFF)
circuitry, which eliminates the requirement for external filtering of the VINAC signal and the subsequent slow
response to transient line variations. A unique circuit algorithm detects the transition of the peak of VVINAC
through seven thresholds and generates an equivalent VFF level centered within the eight QVFF ranges. The
boundaries of the ranges expand with increasing VIN to maintain an approximately equal-percentage delta
between levels. These eight QVFF levels are spaced to accommodate the full "universal" line range of 85 V-265
VRMS.
A great benefit of the QVFF architecture is that the fixed kVFF factors eliminate any contribution to distortion of the
multiplier output, unlike an externally-filtered VINAC signal which unavoidably contains 2nd-harmonic distortion
components. Furthermore, the QVFF algorithm allows for rapid response to both increasing and decreasing
changes in input rms voltage so that disturbances transmitted to the PFC output are minimized. 5% hysteresis in
the level thresholds help avoid "chattering" between QVFF levels for VVINAC voltage peaks near a particular
threshold or containing mild ringing or distortion. The QVFF architecture requires that the input voltage be largely
sinusoidal, and relies on detecting zero-crossings to adjust QVFF downward on decreasing input voltage.
Zero-crossings are defined as VVINAC falling below 0.7 V for at least 50 μs typically.
Table 1 reflects the relationship between the various VINAC peak voltages and the corresponding kVFF terms for
the multiplier equation.

Table 1. VINAC Peak Voltages

LEVEL VVINAC PEAK VOLTAGE kVFF (V2) VIN PEAK VOLTAGE (1)

8 2.60 V ≤ VVINAC(pk) 3.857 > 345 V

7 2.25 V ≤ VVINAC(pk) < 2.60 V 2.922 300 V to 345 V
6 1.95 V ≤ VVINAC(pk) < 2.25 V 2.199 260 V to 300 V
5 1.65 V ≤ VVINAC(pk) < 1.95 V 1.604 220 V to 260 V
4 1.40 V ≤ VVINAC(pk) < 1.65 V 1.156 187 V to 220 V
3 1.20 V ≤ VVINAC(pk) < 1.40 V 0.839 160 V to 187 V
2 1.00 V ≤ VVINAC(pk) < 1.20 V 0.600 133 V to 160 V
1 VVINAC(pk) ≤ 1.00 V 0.398 < 133 V

(1) The VIN peak voltage boundary values listed above are calculated based on a 400-V PFC output voltage and the use of a matched
resistor-divider network (kR = 3 V/400 V = 0.0075) on VINAC and VSENSE (as required for current synthesis). When VOUT is designed
to be higher or lower than 400 V, kR = 3 V/VOUT, and the VIN peak voltage boundary values for each QVFF level adjust to VVINAC(pk)/kR.

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The multiplier output current IIMO for any line and load condition can thus be determined by the equation
17 m A ´ (VVINAC )´ (VVAO - 1)
I IMO =
kVFF
(13)
2
Because the kVFF value represents the scaled VRMS at the center of a level, VVAO will adjust slightly upwards or
downwards when VINACpk is either lower or higher than the center of the QVFF voltage range to compensate for
the difference. This is automatically accomplished by the voltage loop control when VIN varies, both within a level
and after a transition between levels.
The output of the voltage-error amplifier VAO is clamped at 5.0 V, which represents the maximum PFC output
power. This value is used to calculate the maximum reference current at the IMO pin, and sets a limit for the
maximum input power allowed (and, as a consequence, limits maximum output power).
Unlike a continuous VFF situation, where maximum input power is a fixed power at any VRMS input, the discrete
QVFF levels permit a variation in maximum input power within limited boundaries as the input VRMS varies within
each level.
The lowest maximum power limit occurs at the VINAC voltage of 0.76 V, while the highest maximum power limit
occurs at the increasing threshold from level-1 to level-2. This pattern repeats at every level transition threshold,
keeping in mind that decreasing thresholds are 95% of the increasing threshold values. Below VINAC = 0.76 V,
PIN is always less than PIN(max), falling linearly to zero with decreasing input voltage.
For example, to design for the lowest maximum power allowable, determine the maximum steady-state (average)
output power required of the PFC pre-regulator and add some additional percentage to account for line drop-out
recovery power (to recharge COUT while full load power is drawn) such as 10% or 20% of POUT(max). Then apply
the expected efficiency factor to find the lowest maximum input power allowable:
1.10 ´ POUT (max)
PIN (max) =
h
(14)
At the PIN(max) design threshold, VVINAC = 0.76 V, hence QVFF = 0.398 and input VAC = 73 VRMS (accounting for
2-V bridge-rectifier drop) for a nominal 400-V output system.
PIN (max)
Thus I IN ( rms ) = , and I IN ( pk ) = 1.414 ´ I IN ( rms )
73VRMS
(15)

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This IIN(pk) value represents the combined average current through the boost inductors at the peak of the line
voltage. Each inductor current is detected and scaled by a current-sense transformer (CT). Assuming equal
currents through each interleaved phase, the signal voltage at each current sense input pin (CSA and CSB) is
developed across a sense resistor selected to generate ~3 V based on (1/2) x IIN(pk) x RS/NCT, where RS is the
current sense resistor and NCT is the CT turns-ratio.
IIMO is then calculated at that same lowest maximum-power point, as

I IMO(max) = 17 m A ´
(0.76V )(5V - 1V ) = 130m A
0.398 (16)
RIMO is selected such that:
æ1ö R
RIMO ´ I IMO(max) = ç ÷ ´ I IN ( pk ) ´ S
è2ø N CT
(17)
Therefore:
ææ 1 ö ö
ç ç 2 ÷ ´ I IN ( pk ) ´ RS ÷
è ø
RIMO =è ø
(NCT ´ I IMO(max) ) (18)
At the increasing side of the level-1 to level-2 threshold, it should be noted that the IMO current would allow
higher input currents at low-line:

I IMO( L1- L 2 ) = 17 m A ´
(1.0V )(5V - 1V ) = 171m A
0.398 (19)
However, this current may easily be limited by the programmable peak current limiting (PKLMT) feature of the
UCC28070 if required by the power stage design.
The same procedure can be used to find the lowest and highest input power limits at each of the QVFF level
transition thresholds. At higher line voltages, where the average current with inductor ripple is traditionally below
the PKLMT threshold, the full variation of maximum input power will be seen, but the input currents will inherently
be below the maximum acceptable current levels of the power stage.
The performance of the multiplier in the UCC28070 has been significantly enhanced when compared to previous
generation PFC controllers, with high linearity and accuracy over most of the input ranges. The accuracy is at its
worst as VVAO approaches 1 V because the error of the (VVAO-1) subtraction increases and begins to distort the
IMO reference current to a greater degree.

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Enhanced Transient Response (VA Slew-Rate Correction)

Due to the low voltage loop bandwidth required to maintain proper PFC and ignore the slight 120-Hz ripple on
the output, the response of ordinary controllers to input voltage and load transients will also be slow. However,
the QVFF function effectively handles the line transient response with the exception of any minor adjustments
needed within a QVFF level. Load transients on the other hand can only be handled by the voltage loop, therefore,
the UCC28070 has been designed to improve its transient response by pulling up on the output of the voltage
amplifier (VAO) with an additional 100 μA of current in the event the VSENSE voltage drops below 93% of
regulation (2.79 V). During a soft-start cycle, when VSENSE is ramping up from the 0.75-V PFC Enable
threshold, the 100-μA correction current source is disabled to ensure the gradual and controlled ramping of
output voltage and current during a soft start.

Voltage Biasing (VCC and VREF)

The UCC28070 operates within a VCC bias supply range of 10 V to 21 V. An Under-Voltage Lock-Out (UVLO)
threshold prevents the PFC from activating until VCC > 10.2 V, and 1 V of hysteresis assures reliable start-up
from a possibly low-compliance bias source. An internal 25-V zener-like clamp on VCC is intended only to protect
the device from brief energy-limited surges from the bias supply, and should NOT be used as a regulator with a
current-limited source.
At minimum, a 0.1-μF ceramic bypass capacitor must be applied from VCC to GND close to the device pins to
provide local filtering of the bias supply. Larger values may be required depending on ICC peak current
magnitudes and durations to minimize ripple voltage on VCC.
In order to provide a smooth transition out of UVLO and to make the 6-V voltage reference available as early as
possible, the VREF output is enabled when VCC exceeds 8 V typically.
The VREF circuitry is designed to provide the biasing of all internal control circuits and for limited use externally.
At minimum, a 22-nF ceramic bypass capacitor must be applied from VREF to GND close to the device pins to
ensure stability of the circuit. External load current on VREF should be limited to less than 2 mA, or degraded
regulation may result.

PFC Enable and Disable

The UCC28070 contains two independent circuits dedicated to disabling the GDx outputs based on the biasing
conditions of the VSENSE or SS pins. The first circuit which monitors the VVSENSE, is the traditional PFC Enable
that holds off soft-start and the overall PFC function until the output has pre-charged to ~25%. Prior to VVSENSE
reaching 0.75 V, almost all of the internal circuitry is disabled. Once VVSENSE reaches 0.75 V and VAO < 0.75 V,
the oscillator, multiplier, and current synthesizer are enabled and the SS circuitry begins to ramp up the voltage
on the SS pin. The second circuit provides an external interface to emulate an internal fault condition to disable
the GDx output without fully disabling the voltage loop and multiplier. By externally pulling the SS pin below 0.6
V, the GDx outputs are immediately disabled and held low. Assuming no other fault conditions are present,
normal PWM operation resumes when the external SS pulldown is released. It must be noted that the external
pulldown needs to be sized large enough to override the internal 1.5-mA adaptive SS pullup once the SS voltage
falls below the disable threshold. It is recommended that a MOSFET with less than 100-Ω RDS(on) resistance be
used to ensure the SS pin is held adequately below the disable threshold.

Copyright © 2010–2011, Texas Instruments Incorporated 25

UCC28070-Q1
SLUSA71A – JULY 2010 – REVISED JUNE 2011 www.ti.com

Adaptive Soft Start

In order to maintain a controlled power up, the UCC28070 has been designed with an adaptive soft-start function
that overrides the internal reference voltage with a controlled voltage ramp during power up. On initial power up,
once VVSENSE exceeds the 0.75-V enable threshold (VEN), the internal pull down on the SS pin is released, and
the 1.5-mA adaptive soft-start current source is activated. This 1.5-mA pullup almost immediately pulls the SS pin
to 0.75 V (VVSENSE) to bypass the initial 25% of dead time during a traditional 0 V to Vregulation SS ramp. Once
the SS pin has reached the voltage on VSENSE, the 10-μA soft-start current (ISS) takes over. Thus, through the
selection of the soft-start capacitor (CSS), the effective soft-start time (tSS) may be easily programmed based on
the equation below.

æ 2.25V ö
tSS = CSS ´ ç ÷
è 10 m A ø (20)
Often, a system restart is desired following a brief shut-down. In such a case, VSENSE may still have substantial
voltage if VOUT has not fully discharged or if high line has peak charged COUT. To eliminate the delay caused by
charging CSS from 0 V up to the pre-charged VVSENSE with only the 10-μA current source and minimize any
further output voltage sag, the adaptive soft start uses a 1.5-mA current source to rapidly charge CSS to VVSENSE,
after which time the 10-μA source controls the VSS accent to the desired soft-start ramp rate. In such a case, tSS
is estimated as follows:

æ 3V - VVSENSE 0 ö
tSS = CSS ´ ç ÷
è 10 m A ø (21)
where VVSENSE0 is the voltage at VSENSE at the moment a soft start or restart is initiated.

NOTE
For soft start to be effective and avoid overshoot on VOUT, the SS ramp must be slower
than the voltage-loop control response. Choose CSS ≥ CVZ to ensure this.

(V)

VSS

VVSENSE

VSS if no adaptive current

Time (s)
PFC externally
disabled due to Reduced delay to regulation
AC-line drop-out AC-Line recovers
and SS pin released

Figure 21. Soft-Start Ramp Rate

26 Copyright © 2010–2011, Texas Instruments Incorporated

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www.ti.com SLUSA71A – JULY 2010 – REVISED JUNE 2011

PFC Start-Up Hold Off

An additional feature designed into the UCC28070 is the "Start-Up Hold Off" logic that prevents the device from
initiating a soft-start cycle until the VAO is below the zero-power threshold (0.75 V). This feature ensures that the
SS cycle will initiate from zero-power and zero duty-cycle while preventing the potential for any significant inrush
currents due to stored charge in the VAO compensation network.

Output Over-Voltage Protection (OVP)

Because of the high voltage output and a limited design margin on the output capacitor, output over-voltage
protection is essential for PFC circuits. The UCC28070 implements OVP through the continuous monitoring of
the VSENSE voltage. In the event VVSENSE rises above 106% of regulation (3.18 V), the GDx outputs are
immediately disabled to prevent the output voltage from reaching excessive levels. Meanwhile the CAOx outputs
are pulled low in order to ensure a controlled recovery starting from 0% duty-cycle after an OVP fault is released.
Once the VVSENSE voltage has dropped below 3.08 V, the PWM operation resumes normal operation.

Zero-Power Detection
In order to prevent undesired performance under no-load and near no-load conditions, the UCC28070
zero-power detection comparator is designed to disable both GDA and GDB output in the event the VAO voltage
falls below 0.75 V. The 150 mV of hysteresis ensures that the output remains disabled until the VAO has nearly
risen back into the linear range of the multiplier (VAO ≥ 0.9 V).

Thermal Shutdown
In order to protect the power supplies from silicon failures at excessive temperatures, the UCC28070 has an
internal temperature-sensing comparator that shuts down nearly all of the internal circuitry, and disables the GDA
and GDB outputs, if the die temperature rises above 160°C. Once the die temperature falls below 140°C, the
device brings the outputs up through a typical soft start.

Copyright © 2010–2011, Texas Instruments Incorporated 27

UCC28070-Q1
SLUSA71A – JULY 2010 – REVISED JUNE 2011 www.ti.com

Current Loop Compensation

The UCC28070 incorporates two identical and independent transconductance-type current-error amplifiers (one
for each phase) with which to control the shaping of the PFC input current waveform. The current-error amplifier
(CA) forms the heart of the embedded current control loop of the boost PFC pre-regulator, and is compensated
for loop stability using familiar principles [4, 5]. The output of the CA for phase-A is CAOA, and that for phase-B
is CAOB. Since the design considerations are the same for both, they are collectively referred to as CAOx,
where the "x" may be "A" or "B".
In a boost PFC pre-regulator, the current control loop comprises the boost power plant stage, the current sensing
circuitry, the wave-shape reference, the PWM stage, and the CA with compensation components. The CA
compares the average boost inductor current sensed with the wave-shape reference from the multiplier stage
and generates an output current proportional to the difference.
This CA output current flows through the impedance of the compensation network generating an output voltage,
VCAO, which is then compared with a periodic voltage ramp to generate the PWM signal necessary to achieve
PFC.

IMO

CAOx
+
CAx
CSx
CZC
Current
gmc = 100µS
Synthesizer C PC

R ZC

Figure 22. Current Error Amplifier With Type II Compensation

For frequencies above boost LC resonance and below fPWM, the small-signal model of the boost stage, which
includes current sensing, can be simplified to:
R
Vout ´ S
vRS N CT
=
vCA DVRMP ´ kSYNC ´ s ´ LB
(22)
where LB = mid-value boost inductance, RS = CT sense resistor, NCT = CT turns ratio, VOUT = average output
voltage, ∆VRMP = 4Vpk-pk amplitude of the PWM voltage ramp, kSYNC = ramp reduction factor (if PWM frequency is
synchronized to an external oscillator; kSYNC = 1 otherwise), s = Laplace complex variable
An RZCCZC network is introduced on CAOx to obtain high gain for the low-frequency content of the inductor
current signal, but reduced flat gain above the zero frequency out to fPWM to attenuate the high-frequency
switching ripple content of the signal (thus averaging it).

28 Copyright © 2010–2011, Texas Instruments Incorporated

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The switching ripple voltage should be attenuated to less than 1/10 of the ΔVRMP amplitude so as to be
considered "negligible" ripple.
Thus, CAOx gain at fPWM is:
DVRMP ´ k SYNC
g mc Rzc £ 10
RS
DI LB ´
N CT
(23)
where ∆ILB is the maximum peak-to-peak ripple current in the boost inductor, and gmc is the transconductance of
the CA, 100 μS.
4V ´ N CT
Rzc £
10 ´100 m S ´ DI LB ´ RS
(24)
The current-loop cross-over frequency is then found by equating the open loop gain to 1 and solving for fCXO:
RS
Vout ´
N CT
fCXO = ´ g mc Rzc
DVRMP ´ kSYNC ´ 2p ´ LB
(25)
CCZ is then determined by setting fZC = fCXO = 1/(2πxRZCxCZC) and solving for CZC. At fZC = fCXO, a phase margin
of 45° is obtained at fCXO. Greater phase margin may be had by placing fZC < fCXO.
An additional high-frequency pole is generally added at fPWM to further attenuate ripple and noise at fPWM and
higher. This is done by adding a small-value capacitor, Cpc, across the RzcCzc network.
1
Cpc =
2p ´ f PWM ´ Rzc
(26)
The procedure above is valid for fixed-value inductors.

NOTE
If a "swinging-choke" boost inductor (inductance decreases with increasing current) is
used, fCXO varies with inductance, so CZC should be determined at maximum inductance.

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Voltage Loop Compensation

The outer voltage control loop of the dual-phase PFC controller functions the same as with a single-phase
controller, and compensation techniques for loop stability are standard [4]. The bandwidth of the voltage-loop
must be considerably lower than the twice-line ripple frequency (f2LF) on the output capacitor, to avoid
distortion-causing correction to the output voltage. The output of the voltage-error amplifier (VA) is an input to the
multiplier, to adjust the input current amplitude relative to the required output power. Variations on VAO within the
bandwidth of the current loops will influence the wave-shape of the input current. Since the low-frequency ripple
on COUT is a function of input power only, its peak-to-peak amplitude is the same at high-line as at low-line. Any
response of the voltage-loop to this ripple will have a greater distorting effect on high-line current than on low-line
current. Therefore, the allowable percentage of 3rd-harmonic distortion on the input current contributed by VAO
should be determined using high-line conditions.
Because the voltage-error amplifier (VA) is a transconductance type of amplifier, the impedance on its input has
no bearing on the amplifier gain, which is determined solely by the product of its transconductance (gmv) with its
output impedance (ZOV). Thus the VSENSE input divider-network values are determined separately, based on
criteria discussed in the VINAC section. Its output is the VAO pin.

VAO
3V +
VA
C ZV
VSENSE gmv = 70µS
CPV

RZV

Figure 23. Voltage Error Amplifier With Type II Compensation

The twice-line ripple voltage component of VSENSE must be sufficiently attenuated and phase-shifted at VAO to
achieve the desired level of 3rd-harmonic distortion of the input current wave-shape [4]. For every 1% of
3rd-harmonic input distortion allowable, the small-signal gain GVEA = VVAOpk / vSENSEpk = gmvxZOV at the twice-line
frequency should allow no more than 2% ripple over the full VAO voltage range. In the UCC28070, VVAO can
range from 1 V at zero load power to ~4.2 V(see note below) at full load power for a ΔVVAO = 3.2 V, so 2% of 3.2
V is 64-mV peak ripple.

NOTE
Although the maximum VAO voltage is clamped at 5 V, at full load VVAO may vary around
an approximate center point of 4.2 V to compensate for the effects of the quantized
feed-forward voltage in the multiplier stage (see Multiplier Section for details). Therefore,
4.2 V is the proper voltage to use to represent maximum output power when performing
voltage-loop gain calculations.

30 Copyright © 2010–2011, Texas Instruments Incorporated

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The output capacitor maximum low-frequency zero-to-peak ripple voltage is closely approximated by:
Pinavg ´ X Cout Pinavg
v0 pk = =
Voutavg Voutavg ´ 2p ´ f 2 LF ´ Cout
(27)
where PIN(avg) is the total maximum input power of the interleaved-PFC pre-regulator, VOUT(avg) is the average
output voltage and COUT is the output capacitance.
VSENSEpk = vopkxkR, where kR is the gain of the resistor-divider network on VSENSE.
Thus, for k3rd% of allowable 3rd-harmonic distortion on the input current attributable to the VAO ripple,
k3rd ´ 64mV ´ Voutavg ´ 2p f 2 LF ´ Cout
Z OV ( f2 LF ) =
g mv ´ k R ´ Pinavg
(28)
This impedance on VAO is set by a capacitor (Cpv), where CPV = 1/( 2πf2LFxZOV(f2LF)) therefore,
g mv ´ k R ´ Pinavg
Cpv =
k3rd ´ 64mV ´ Voutavg ´ ( 2p f 2 LF )2 ´ Cout
(29)

The voltage-loop unity-gain cross-over frequency (fVXO) may now be solved by setting the open-loop gain equal
to 1:
æ Pinavg ´ X Cout ö
Tv( fVXO ) = GBST ´ GVEA ´ k R = ç
ç DVVAO ´ Voutavg ÷÷ ´ (g mv ´ X Cpv )´ k R = 1
è ø (30)

g mv ´ k R ´ Pinavg
fVXO 2 = 2
DVVAO ´ Voutavg ´ (2p ) ´ Cpv ´ Cout
so, (31)
The "zero-resistor" (RZV) from the zero-placement network of the compensation may now be calculated. Together
with CPV, RZV sets a pole right at fVXO to obtain 45° phase margin at the cross-over.
1
Rzv =
2p fVXO ´ Cpv
Thus, (32)
Finally, a zero is placed at or below fVXO/6 with capacitor CZV to provide high gain at dc but with a breakpoint far
enough below fVXO so as not to significantly reduce the phase margin. Choosing fVXO/10 allows one to
approximate the parallel combination value of CZV and CPV as CZV, and solve for CZV simply as:
10
Czv = » 10 ´ Cpv
2p fVXO ´ Rzv
(33)
By using a spreadsheet or math program, CZV, RZV, and CPV may be manipulated to observe their effects on fVXO
and phase margin and %-contribution to 3rd-harmonic distortion (see note below). Also, phase margin may be
checked as PIN(avg) level and system parameter tolerances vary.

NOTE
The percent of 3rd-harmonic distortion calculated in this section represents the
contribution from the f2LF voltage ripple on COUT only. Other sources of distortion, such as
the current-sense transformer, the current synthesizer stage, even distorted VIN, etc., can
contribute additional 3rd and higher harmonic distortion.

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UCC28070-Q1
SLUSA71A – JULY 2010 – REVISED JUNE 2011 www.ti.com

Advanced Design Techniques

Current Loop Feedback Configuration

(Sizing of the Current Transformer Turns Ratio and Sense Resistor (RS)
A current-sense transformer (CT) is typically used in high-power applications to sense inductor current while
avoiding significant losses in the sensing resistor. For average current-mode control, the entire inductor current
waveform is required; however low-frequency CTs are obviously impracticable. Normally, two high-frequency
CTs are used, one in the switching leg to obtain the up-slope current and one in the diode leg to obtain the
down-slope current. These two current signals are summed together to form the entire inductor current, but this
is not the case for the UCC28070.
A major advantage of the UCC28070 design is the current synthesis function, which internally recreates the
inductor current down-slope during the switching period off-time. This eliminates the need for the diode-leg CT in
each phase, significantly reducing space, cost and complexity. A single resistor programs the synthesizer down
slope, as previously discussed in the Current Synthesizer section.
A number of trade-offs must be made in the selection of the CT. Various internal and external factors influence
the size, cost, performance, and distortion contribution of the CT.
These factors include, but are not limited to:
• Turns-ratio (NCT)
• Magnetizing inductance (LM)
• Leakage inductance (LLK)
• Volt-microsecond product (Vμs)
• Distributed capacitance (Cd)
• Series resistance (RSER)
• External diode drop (VD)
• External current sense resistor (RS)
• External reset network
Traditionally, the turns-ratio and the current sense resistor are selected first. Some iterations may be needed to
refine the selection once the other considerations are included.

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In general, 50 ≤ NCT ≤ 200 is a reasonable range from which to choose. If NCT is too low, there may be high
power loss in RS and insufficient LM. If too high, there could be excessive LLK and Cd. (A one-turn primary
winding is assumed.)

CSx
LLK
RSER D
IDS 1 NCT LM iM Cd Reset RS
Network

Figure 24. Current Sense Transformer Equivalent Circuit

A major contributor to distortion of the input current is the effect of magnetizing current on the CT output signal
(iRS). A higher turns-ratio results in a higher LM for a given core size. LM should be high enough that the
magnetizing current (iM) generated is a very small percentage of the total transformed current. This is an
impossible criterion to maintain over the entire current range, because iM unavoidably becomes a larger fraction
of iRS as the input current decreases toward zero. The effect of iM is to "steal" some of the signal current away
from RS, reducing the CSx voltage and effectively understating the actual current being sensed. At low currents,
this understatement can be significant and CAOx increases the current-loop duty-cycle in an attempt to correct
the CSx input(s) to match the IMO reference voltage. This unwanted correction results in overstated current on
the input wave shape in the regions where the CT understatement is significant, such as near the ac line zero
crossings. It can affect the entire waveform to some degree under the high line, light-load conditions.
The sense resistor RS is chosen, in conjunction with NCT, to establish the sense voltage at CSx to be about 3 V
at the center of the reflected inductor ripple current under maximum load. The goal is to maximize the average
signal within the common-mode input range VCMCAO of the CAOx current-error amplifiers, while leaving room for
the peaks of the ripple current within VCMCAO. The design condition should be at the lowest maximum input power
limit as determined in the Multiplier Section. If the inductor ripple current is so high as to cause VCSx to exceed
VCMCAO, then RS or NCT or both must be adjusted to reduce peak VCSx, which could reduce the average sense
voltage center below 3 V. There is nothing wrong with this situation; but be aware that the signal is more
compressed between full- and no-load, with potentially more distortion at light loads.
The matter of volt-second balancing is important, especially with the widely varying duty-cycles in the PFC stage.
Ideally, the CT is reset once each switching period; that is, the off-time Vμs product equals the on-time Vμs
product. (Because a switching period is usually measured in microseconds, it is convenient to convert the
volt-second product to volt-microseconds to avoid sub-decimal numbers.) On-time Vμs is the time-integral of the
voltage across LM generated by the series elements RSER, LLK, D, and RS. Off-time Vμs is the time-integral of the
voltage across the reset network during the off-time. With passive reset, Vμs-off is unlikely to exceed Vμs-on.
Sustained unbalance in the on or off Vμs products will lead to core saturation and a total loss of the
current-sense signal. Loss of VCSx causes VCAOx to quickly rise to its maximum, programming a maximum
duty-cycle at any line condition. This, in turn causes the boost inductor current to increase without control, until
the system fuse or some component failure interrupts the input current.

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SLUSA71A – JULY 2010 – REVISED JUNE 2011 www.ti.com

It is vital that the CT has plenty of Vμs design-margin to accommodate various special situations where there to
be several consecutive maximum duty-cycle periods at maximum input current, such as during peak current
limiting.
Maximum Vμs(on) can be estimated by:
Vm (on )max = tON (max ) ´ (VRS + VD + VRSER + VLK )
(34)
where all factors are maximized to account for worst-case transient conditions and tON(max) occurs during the
lowest dither frequency when frequency dithering is enabled. For design margin, a CT rating of ~5*Vμs(on)max
or higher is suggested. The contribution of VRS varies directly with the line current. However, VD may have a
significant voltage even at near-zero current, so substantial Vμs(on) may accrue at the zero-crossings where the
duty-cycle is maximum. VRSER is the least contributor, and often can be neglected if RSER<<RS. VLK is developed
by the di/dt of the sensed current, and is not observable externally. However, its impact is considerable, given
the sub-microsecond rise-time of the current signal plus the slope of the inductor current. Fortunately, most of the
built-up Vμs across LM during the on-time is removed during the fall-time at the end of the duty-cycle, leaving a
lower net Vμs(on) to be reset during the off-time. Nevertheless, the CT must, at the very minimum, be capable of
sustaining the full internal Vμs(on)max built up until the moment of turn-off within a switching period.
Vμs(off) may be generated with a resistor or zener diode, using the iM as bias current.

CRST D D

RRST RRST ZRST

Figure 25. Possible Reset Networks

In order to accommodate various CT circuit designs and prevent the potentially destructive result due to CT
saturation, the UCC28070's maximum duty-cycle needs to be programmed such that the resulting minimum
off-time accomplishes the required worst-case reset. (See the PWM Frequency and Duty-Cycle Clamp section of
the data sheet for more information on sizing RDMX) Be aware that excessive Cd in the CT can interfere with
effective resetting, because the maximum reset voltage is not reached until after 1/4-period of the CT
self-resonant frequency. A higher turns-ratio results in higher Cd [3], so a trade-off between NCT and DMAX must
be made.
The selected turns-ratio also affects LM and LLK, which vary proportionally to the square of the turns. Higher LM is
good, while higher LLK is not. If the voltage across LM during the on-time is assumed to be constant (which it is
not, but close enough to simplify) then the magnetizing current is an increasing ramp.
This upward ramping current subtracts from iRS, which affects VCSx especially heavily at the zero-crossings and
light loads, as stated earlier. With a reduced peak at VCSx, the current synthesizer starts the down-slope at a
lower voltage, further reducing the average signal to CAOx and further increasing the distortion under these
conditions. If low input current distortion at very light loads is required, special mitigation methods may need to
be developed to accomplish that goal.

34 Copyright © 2010–2011, Texas Instruments Incorporated

 UCC28070-Q1
www.ti.com SLUSA71A – JULY 2010 – REVISED JUNE 2011

Current Sense Offset and PWM Ramp for Improved Noise Immunity
To improve noise immunity at extremely light loads, a PWM ramp with a dc offset is recommended to be added
to the current sense signals. Electrical components RTA, RTB, ROA, ROB, CTA, CTB, DPA1, DPA2, DPB1, DPB1 CTA,
CTB form a PWM ramp that is activated and deactivated by the gate drive outputs of the UCC28070. Resistor
ROA and ROB add a dc offset to the CS resistors (RSA and RSB).

VCC
D PA1

R OA
R TA D PA2
G DA CSA

C TA
R SA

VCC
D PB1

R OB
R TB D PB2
G DB

C TB R SB

Figure 26. PWM Ramp and Offset Circuit

Copyright © 2010–2011, Texas Instruments Incorporated 35

UCC28070-Q1
SLUSA71A – JULY 2010 – REVISED JUNE 2011 www.ti.com

When the inductor current becomes discontinuous the boost inductors ring with the parasitic capacitances in the
boost stages. This inductor current rings through the CTs causing a false current sense signal. Please refer to
the following graphical representation of what the current sense signal looks like when the inductor current goes
discontinuous.

NOTE
The inductor current and RS may vary from this graphical representation depending on
how much inductor ringing is in the design when the unit goes discontinuous.

Figure 27. False Current Sense Signal

To counter for the offset (VOFF) just requires adjusting resistors ROA and ROB to ensure that when the unit goes
discontinuous the current sense resistor is not seeing a positive current when it should be zero. Setting the offset
to 120 mV is a good starting point and may need to be adjusted based on individual design criteria.
RSA = RSB
(35)

ROA = ROB =
(VVCC - VOFF ) RSA
VOFF
(36)
A small PWM ramp that is equal to 10% of the maximum current sense signal (VS) less the offset can then be
added by properly selecting RTA, RTB, CTA and CTB.

RTA = RTB =
(VVCC - (VS ´ 0.1 - VOFF ) + VDA2 ) RSA
VS ´ 0.1 - VOFF
(37)
1
CTA = CTB =
RTA ´ f S ´ 3
(38)

36 Copyright © 2010–2011, Texas Instruments Incorporated

 UCC28070-Q1
www.ti.com SLUSA71A – JULY 2010 – REVISED JUNE 2011

Recommended PCB Device Layout

Interleaved PFC techniques dramatically reduce input and output ripple current caused by the PFC boost
inductor, which allows the circuit to use smaller and less expensive filters. To maximize the benefits of
interleaving, the output filter capacitor should be located after the two phases allowing the current of each phase
to be combined together before entering the boost capacitor. Similar to other power management devices, when
laying out the PCB it is important to use star grounding techniques and to keep filter and high frequency bypass
capacitors as close to device pins and ground as possible. To minimize the possibility of interference caused by
magnetic coupling from the boost inductor, the device should be located at least 1 inch away from the boost
inductor. It is also recommended that the device not be placed underneath magnetic elements.

References
1. O'Loughlin, Michael, "An Interleaving PFC Pre-Regulator for High-Power Converters", Texas Instruments,
Inc. 2006 Unitrode Power Supply Seminar, Topic 5
2. Erickson, Robert W., "Fundamentals of Power Electronics", 1st ed., pp. 604-608 Norwell, MA: Kluwer
Academic Publishers, 1997
3. Creel, Kirby "Measuring Transformer Distributed Capacitance", White Paper, Datatronic Distribution, Inc.
website: http://www.datatronics.com/pdf/distributed_capacitance_paper.pdf
4. L. H. Dixon, "Optimizing the Design of a High Power Factor Switching Preregulator", Unitrode Power Supply
Design Seminar Manual SEM700, 1990. Texas Instruments Literature Number SLUP093
5. L. H. Dixon, "High Power Factor Preregulator for Off-Line Power Supplies", Unitrode Power Supply Design
Seminar Manual SEM600, 1988. Texas Instruments Literature Number SLUP087

Copyright © 2010–2011, Texas Instruments Incorporated 37

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UCC28070QPWRQ1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 28070Q

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC28070-Q1 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

• Catalog: UCC28070

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC28070QPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC28070QPWRQ1 TSSOP PW 20 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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