SN74AUP1T04

www.ti.com SCES800 – APRIL 2010

LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE

INVERTER GATE
Check for Samples: SN74AUP1T04

1FEATURES
• Single-Supply Voltage Translator • More Gate Options Available at
• Output Level Up to Supply VCC CMOS Level www.ti.com/littlelogic
– 1.8 V to 3.3 V (at VCC = 3.3 V) • ESD Performance Tested Per JESD 22
– 2.5 V to 3.3 V (at VCC = 3.3 V) – 2000-V Human-Body Model
– 1.8 V to 2.5 V (at VCC = 2.5 V) (A114-B, Class II)
– 3.3 V to 2.5 V (at VCC = 2.5 V – 1000-V Charged-Device Model (C101)
• Schmitt-Trigger Inputs Reject Input Noise and DCK PACKAGE
Provide Better Output Signal Integrity (TOP VIEW)
• Ioff Supports Partial Power Down (VCC = 0 V)
NC 1 5 VCC
• Very Low Static Power Consumption:
0.1 µA
A 2
• Very Low Dynamic Power Consumption:
0.9 µA GND 3 4 Y
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• Pb-Free Packages Available: SC-70 (DCK)
2 x 2.1 x 0.65 mm (Height 1.1 mm)

DESCRIPTION/ORDERING INFORMATION
The SN74AUP1T04 performs the Boolean function Y = A with designation for logic-level translation applications
with output referenced to supply VCC.
AUP technology is the industry's lowest-power logic technology designed for use in extending battery-life in
operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V
VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external
controllers or processors.
Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise
immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger
inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.
Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile
applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of
the device. No damage occurs to the device under these conditions.
The SN74AUP1T04 is designed with optimized current-drive capability of 4 mA to reduce line reflections,
overshoot, and undershoot caused by high-drive outputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AUP1T04
SCES800 – APRIL 2010 www.ti.com

ORDERING INFORMATION (1)

TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (3)
Reel of 3000 SN74AUP1T04DCKR
–40°C to 85°C SOT (SC-70) – DCK 6C_
Reel of 250 SN74AUP1T04DCKT

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) The actual top-side marking has one additional character that designates the wafer fab/assembly site.

FUNCTION TABLE
INPUT OUTPUT
(Lower Level Input) (VCC CMOS)
A Y
H L
L H

Supply VCC = 2.3 V to 2.7 V (2.5 V)

INPUTS
OUTPUT
VT+ max = VIH min
CMOS
VT- min = VIL max
A B Y
VIH = 1.1 V VOH = 1.85 V
VIL = 0.35 V VOL = 0.45 V

Supply VCC = 3 V to 3.6 V (3.3 V)

INPUTS
OUTPUT
VT+ max = VIH min
CMOS
VT- min = VIL max
A B Y
VIH = 1.19 V VOH = 2.55 V
VIL = 0.5 V VOL = 0.45 V

LOGIC DIAGRAM (INVERTER GATE)

2 4
A Y

Static-Power Consumption Dynamic-Power Consumption Switching Characteristics

(µA) (pF) at 25 MHz†
3.5
100% 100% 3
80% 80% 2.5
Voltage − V

2 Input Output
60% 60% 1.5
3.3-V 3.3-V
LVC 1
40% Logic† 40% Logic†
0.5
20% 20% 0
AUP AUP −0.5
0% 0% 0 5 10 15 20 25 30 35 40 45
† Single, dual, and triple gates Time − ns
† AUP1G08 data at C = 15 pF
L

Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity

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3.3 V 3.3 V

VIH = 1.19 V VIH = 1.19 V

VIL = 0.5 V VIL = 0.5 V
1.8-V 3.3-V 2.5-V 3.3-V
System System System System

2.5 V 2.5 V

VIH = 1.10 V VIH = 1.10 V

VIL = 0.35 V VIL = 0.35 V
1.8-V 2.5-V 3.3-V 2.5-V
System System System System

Figure 3. Typical Design Examples

3.3 V

1.8-V 3.3-V
System System

VOH min
VT+ max = VIH min = 1.19 V
VT− min = V IL max = 0.5 V VOL max

Input Switching Waveform Output Switching Waveform

Figure 4. Switching Thresholds for 1.8-V to 3.3-V Translation

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ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 4.6 V
VI Input voltage range (2) –0.5 4.6 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 4.6 V
(2)
VO Output voltage range in the high or low state –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±20 mA
Continuous current through VCC or GND ±50 mA
qJA Package thermal impedance (3) DCK package 259 °C/W
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.

RECOMMENDED OPERATING CONDITIONS (1)

MIN MAX UNIT
VCC Supply voltage 2.3 3.6 V
VI Input voltage 0 3.6 V
VO Output voltage 0 VCC V
VCC = 2.3 V –3.1
IOH High-level output current mA
VCC = 3 V –4
VCC = 2.3 V 3.1
IOL Low-level output current mA
VCC = 3 V 4
TA Operating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.

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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA = –40°C
TA = 25°C
PARAMETER TEST CONDITIONS VCC to 85°C UNIT
MIN TYP MAX MIN MAX
VT+ 2.3 V to 2.7 V 0.6 1.1 0.6 1.1
Positive-going input V
threshold voltage 3 V to 3.6 V 0.75 1.16 0.75 1.19
VT– 2.3 V to 2.7 V 0.35 0.6 0.35 0.6
Negative-going
V
input threshold 3 V to 3.6 V 0.5 0.85 0.5 0.85
voltage
ΔVT 2.3 V to 2.7 V 0.23 0.6 0.1 0.6
Hysteresis V
(VT+ – VT–) 3 V to 3.6 V 0.25 0.56 0.15 0.56
IOH = –20 mA 2.3 V to 3.6 V VCC – 0.1 VCC – 0.1
IOH = –2.3 mA 2.05 1.97
2.3 V
VOH IOH = –3.1 mA 1.9 1.85 V
IOH = –2.7 mA 2.72 2.67
3V
IOH = –4 mA 2.6 2.55
IOL = 20 mA 2.3 V to 3.6 V 0.1 0.1
IOL = 2.3 mA 0.31 0.33
2.3 V
VOL IOL = 3.1 mA 0.44 0.45 V
IOL = 2.7 mA 0.31 0.33
3V
IOL = 4 mA 0.44 0.45
II All inputs VI = 3.6 V or GND 0 V to 3.6 V 0.1 0.5 mA
Ioff VI or VO = 0 V to 3.6 V 0V 0.1 0.5 mA
ΔIoff VI or VO = 3.6 V 0 V to 0.2 V 0.2 0.5 mA
ICC VI = 3.6 V or GND, IO = 0 2.3 V to 3.6 V 0.5 0.9 mA
One input at 0.3 V or 1.1 V,
2.3 V to 2.7 V 4
Other inputs at 0 or VCC, IO = 0
ΔICC mA
One input at 0.45 V or 1.2 V,
3 V to 3.6 V 12
Other inputs at 0 or VCC, IO = 0
Ci VI = VCC or GND 3.3 V 1.5 pF
Co VO = VCC or GND 3.3 V 3 pF

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 1.8 V ± 0.15 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
FROM TO TA = 25°C
PARAMETER CL to 85°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
5 pF 1.8 2.3 2.9 0.5 6.8
10 pF 2.3 2.8 3.4 1 7.9
tpd A Y ns
15 pF 2.6 3.1 3.8 1 8.7
30 pF 3.8 4.4 5.1 1.5 10.8

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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 2.5 V ± 0.2 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
FROM TO TA = 25°C
PARAMETER CL to 85°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
5 pF 1.8 2.3 3.1 0.5 6
10 pF 2.2 2.8 3.5 1 7.1
tpd A Y ns
15 pF 2.6 3.2 5.2 1 7.9
30 pF 3.7 4.4 5.2 1.5 10

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 3.3 V ± 0.3 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
FROM TO TA = 25°C
PARAMETER CL to 85°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
5 pF 2 2.7 3.5 0.5 5.5
10 pF 2.4 3.1 3.9 1 6.5
tpd A Y ns
15 pF 2.8 3.5 4.3 1 7.4
30 pF 4 4.7 5.5 1.5 9.5

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 1.8 V ± 0.15 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
FROM TO TA = 25°C
PARAMETER CL to 85°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
5 pF 1.6 2 2.5 0.5 8
10 pF 2 2.4 2.9 1 8.5
tpd A Y ns
15 pF 2.3 2.8 3.3 1 9.1
30 pF 3.4 3.9 4.4 1.5 9.8

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 2.5 V ± 0.2 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
FROM TO TA = 25°C
PARAMETER CL to 85°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
5 pF 1.6 1.9 2.4 0.5 5.3
10 pF 2 2.3 2.7 1 6.1
tpd A Y ns
15 pF 2.3 2.7 3.1 1 6.8
30 pF 3.4 3.8 4.2 1.5 8.5

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www.ti.com SCES800 – APRIL 2010

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 3.3 V ± 0.3 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
FROM TO TA = 25°C
PARAMETER CL to 85°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
5 pF 1.6 2.1 2.7 0.5 4.7
10 pF 2 2.4 3 1 5.7
tpd A Y ns
15 pF 2.3 2.7 3.3 1 6.2
30 pF 3.4 3.8 4.4 1.5 7.8

OPERATING CHARACTERISTICS
TA = 25°C
VCC = 2.5 V VCC = 3.3 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 4 5 pF

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PARAMETER MEASUREMENT INFORMATION

From Output
Under Test VCC = 2.5 V VCC = 3.3 V
CL ± 0.2 V ± 0.3 V
1 MΩ
(see Note A) CL 5, 10, 15, 30 pF 5, 10, 15, 30 pF
VMI VI/2 VI/2
VMO VCC/2 VCC/2

LOAD CIRCUIT

VI
Input VMI VMI
0V

tPLH tPHL
VOH
Output VMO VMo
VOL
tPHL tPLH

VOH
Output VMo VMo
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. tPLH and tPHL are the same as tpd.

Figure 5. Load Circuit and Voltage Waveforms

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 PACKAGE OPTION ADDENDUM

www.ti.com 20-Feb-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74AUP1T04DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 6CF Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-Mar-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AUP1T04DCKR SC70 DCK 5 3000 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-Mar-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUP1T04DCKR SC70 DCK 5 3000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.15
0.1 C A B 4X 0 -12 0.1
(0.9) TYP
NOTE 5 0.0

4X 4 -14

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/F 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.
6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.25mm per side

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 EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/F 08/2024

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/F 08/2024

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.

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