DEPARTMENT OF ELECTRONICS AND COMMUNICATION

EC3561- VLSI DESIGN LABORATORY (Regulation –

LAB MANUAL

Prepared By

G.Mani Sankar AP/ECE

DEPARTMENT OF ECE
VISION
To produce technically competent and socially responsible Electronics and
Communication Engineers to meet industry needs.
MISSION
1. Establishing state of art technology in the field of Electronics and Communication
Engineering and enriching the know ledge of faculty through continuous improvement
process.
2. Adopting innovative teaching learning practices and facilitating industry
institute partnership for professional development.
3. Inculcating ethical and social values through extension activities.

PROGRAM EDUCATIONAL OBJECTIVES (PEOS)

 1. Graduates w ill exhibit conceptual, practical and analy tical know ledge in the field
of Electronics and Communication Engineering.
2. Graduates w ill excel in their chosen technical profession in Electronics and
Communication Engineering or interdisciplinary areas.
3. Graduates w ill engage in life-long learning and team w ork w ith ethical values.

PROGRAM OUTCOMES
PO1- Engineering Know ledge: Apply the know ledge of Mathematics, Science, Engineering
fundamentals, and an Engineering specialization to the solution of complex engineering
problems.
PO2 - Problem analysis: Identify, formulate, review research literature, and analyze complex
Engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and Engineering sciences. PO3 - Design/development of
solutions: Design solutions for complex Engineering problems and design system
components or processes that meet the specified needs w ith appropriate consideration for
the public health and safety, and the cultural, societal, and environmental considerations.
PO4 - Conduct investigations of complex problems: Use research based know ledge and
research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.
PO5 - Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex Engineering
activities w ith an understanding of the limitations.
PO6 - The Engineer and society: Apply reasoning informed by the contextual know ledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional Engineering practice.
PO7 - Environment and sustainability: Understand the impact of the professional Engineering
solutions in societal and environmental contexts, and demonstrate the know ledge of, and the
need for sustainable developments.
PO8 - Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the Engineering practice.
PO9 - Individual and team w ork: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.

PO10 - Communication: Communicate effectively on complex Engineering activities w ith the

Engineering Community and w ith society at large, such as, being able to comprehend and
w rite effective reports and design documentation, make effective presentations, and give and
receive clear instructions.
PO11- Project management and finance: Demonstrate know ledge and understanding of the
Engineering and management principles and apply these to one’s ow n w ork, as a member and
leader in a team, to manage projects and in multi- disciplinary environments.
PO12 - Life -long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life- long learning in the broadest context of technological change.
 PROGRAM SPECIFIC OUTCOMES
1. Analyze, Design, Simulate and Integrate Electronic Circuits and Systems for given
specifications.
2. Apply the technical know ledge to solve issues in the areas like signal processing,
Communication, VLSI design and Embedded Systems

Formulated Course Outcome (CO)

Students develop the ability to learn Hardw are Descriptive Language(Verilog/VHDL)

Students develop the ability to learn the fundamental principles of VLSI

circuit design in digital and analog domain
Students have the ability to familiarize fusing of logical modules on FPGAs

Students have the ability to provide hands on design experience w ith

professional design (EDA) platforms

CO-PO & CO-PSO MAPPING

CO Course Outcomes (COs) Know ledge

No. Level
Examine the HDL code for basic as w ell as advanced
C317.1 K4
digital integrated
circuit

C317.2 Examine the logic modules into FPGA Boards. K4

C317.3 Examine to Place and Route the digital Ips K4

Analyze, Simulate and Extract the layouts of Digital &
C317. Analog IC Blocks using EDA tools K4
4
C317.5 Analyze the Test and Verification of IC design. K4

CO - PO MATRICES OF COURSE
Mapping of Course Outcomes w ith Program Outcomes& Program Specific
Outcomes :
CO No PO PO P P PO P PO PO P PO1 PO1 PO PS PS
1 2 O O 5 O 7 8 O 0 1 12 O1 O2
3 4 6 9
C317.1 3 2 2 2 3 - - 1 1 1 - 3 2 3
C317.2 3 2 2 2 3 - - 1 1 1 - 3 2 3
 C317.3 3 2 2 2 3 - - 1 1 1 - 3 2 3
C317.4 3 2 2 2 3 - - 1 1 1 - 3 2 3
C317.5 3 2 2 2 3 - - 1 1 1 - 3 2 3
C317 3 2 2 2 3 - - 1 1 1 - 3 2 3

SYLLABUS

EC3561 VLSI DESIGN LABORATORY L 0 T 0 P 4 C

2

OBJECTIVES:
To learn Hardw are Descriptive Language (Verilog/VHDL).
To learn the fundamental principles of Digital System Desing using HDL and FPGA.
To learn the fundamental principles of VLSI circuit design in digital domain
To learn the fundamental principles of VLSI circuit design in analog domain
To provide hands on design experience w ith EDA platforms
LIST OF EXPERIMENTS:

Part I: Digital System Design using HDL & FPGA (24 Periods)

1. Design of basic combinational and sequential (Flip- flops) circuits using HDL. Simulate it
using Xilinx/Altera Softw are and implement by Xilinx/Altera FPGA
2. Design an Adder ; Multiplier (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Softw are
and implement by Xilinx/Altera FPGA
3. Design and implement Universal Shift Register using HDL. Simulate it using Xilinx/Altera
Softw are
4. Design Memories using HDL. Simulate it using Xilinx/Altera Softw are and implement by Xilinx/
Altera FPGA
5. Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera
Softw are and implement by Xilinx/Altera FPGA
6. Design 3-bit synchronous up/dow n counter using HDL. Simulate it using Xilinx/Altera
Softw are and implement by Xilinx/Altera FPGA
7. Design 4 -bit Asynchronous up/dow n counter using HDL. Simulate it using Xilinx/Altera
Softw are and implement by Xilinx/Altera FPGA
8. Design and simulate a CMOS Basic Gates & Flip-Flops. Generate Manual/Automatic
Layout .
9. Design and simulate a 4 -bit synchronous counter using a Flip-Flops. Generate Manual/
Automatic Layout
10. Design and Simulate a CMOS Inverting Amplifier.
11.D esign and Simulate basic Common Source, Common Gate and Common Drain Amplifiers.
12.D esign and simulate simple 5 transistor differential amplifier.

Requirements: Cadence/Synopsis/ Mentor Graphics/Tanner/equivalent EDA Tools

 TOTAL: 60 PERIODS

INDEX

S.No Pag
. Dat Name of the Experiment e Mark Signatu
e s re
No
.
OPTICAL EXPERIMENTS

1 Design of basic combinational and

sequential (Flip- flops) circuits using HDL.
2 Design an Adder ; Multiplier (Min 8 Bit)
using HDL.
3 Design and implement Universal Shift
Register using HDL.
4
Design Memories using HDL (Single Port
RAM)
5 Design Finite State Machine (Moore/
Mealy) using HDL.
6 Design 3-bit synchronous up/dow n
counter using HDL.
7 Design 4 -bit Asynchronous up/dow n
counter using HDL.
8 Design and simulate a CMOS Basic Gates
& Flip- Flops.
9 Design and simulate a 4 -bit synchronous
counter using a Flip-Flops.
10
Design and Simulate a CMOS Inverting
Amplifier.
11 Design and Simulate basic Common
Source, Common Gate and Common
Drain Amplifiers.
12 Design and simulate simple 5 transistor
differential amplifier.
TOPIC BEYOND THE SYLLABUS EXPERIMENT
 13 Design entry simulation and
implementation of 4 - bit Ripple Carry
Adder
14 Design entry simulation and
implementation of 32- to-1multiplexer
using 2- to-1multiplexer

EXPERIMENTS

Exp: 1aDesign of basic combinational circuits using HDL

Aim:

To check the functionality of a design, w e have to apply test vectors and simulate the circuit.

Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:

1)Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2)A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3)In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4)A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5)On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6)Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7)Now Select the behavioral Syntax first and then the Simulate behavioral.
8)Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9)After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11)After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View
technology scheme pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.

15) Then Select Implement design that is present on the left side of the w indow.
Under Implement design click translate map place and route.
16) Select generate programming file and Sw itch ON FPGA kit.
17) In this W indow click Configure target device manage configure Survey No.
18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click
IC and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.
Program:

Combinational circuit
module

o_gate_tb_v; reg

a; reg b;

w ire z;

o_gate

uut (
.a(a),

.b(b),

.z(z)

);

initial begin

a = 0 ;

b = 0 ;

// Wait 10 0 ns for global reset to

finish #10 0 ;

// Add stimulus

here end
End module

module o_gate_tb_v;

reg a; reg

b; w ire z;

o_gate

uut (
.a(a),

.b(b),
.z(z)

);

initial begin

a = 0 ;

b = 0 ;

//Wait 10 0 ns for global reset to

finish #10 0 ;
a = 0 ;

b = 1;

// Wait 10 0 ns for global reset to

finish #10 0 ;
a = 1;

b = 0 ;

// Wait 10 0 ns for global reset to

finish #10 0 ;
a = 1;

b = 1; // Wait 10 0 ns for global

reset to finish #10 0 ;

end

endmodul

e

Output:
 Result:

Thus the output module is checked in order to apply test vectors, a test bench file is w ritten.

Exp: 1bDesign of basic sequential (Flip- flops) circuits using HDL

 Aim:

To check the functionality of a design, w e have to apply test vectors and simulate the circuit.

Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:

1) Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2) Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3) In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4) A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5) On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6) Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7) Now Select the behavioral Syntax first and then the Simulate behavioral.
8) Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9) After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11) After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View technology scheme
pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.

15) Then Select Implement design that is present on the left side of the w indow. Under
Implement design click translate map place and route.
16) Select generate programming file and Sw itch ON FPGA kit.
17) In this W indow click Configure target device manage configure Survey No.
18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click IC
and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.
Program:

A D- flip w ith asynchronous reset can be modeled as a Procedural block as follow s

module dff_async (data, clock,

reset, q); \ input data, clock, reset;

output q; reg q;

// logic begins here

alw ays @ (posedge clock or negedge

reset) if(reset == 1'b0 )

q <= 1'b0 ;

else

q <=
data;

Endmod
ule

A D- flip w ith synchronous reset can be modeled as a Procedural block as follow s:
module dff_sync (data, clock,

reset, q); input data, clock, reset;

output q; reg q;

// logic begins here

alw ays @ (posedge

clock) if(reset ==

1'b0 )
q <= 1'b0 ;

else q <=
data;

Endmodule

Simulation of sequential

designs module

test_bench(clk)

output

clk; reg

clk;

initial begin clk =

0 ; forever begin

#5 clk = ~clk; //Time period of the clock is 10

time units. End

// rest of the
 logic endmodule

Result:

Thus the output module is checked in order to apply test vectors, a test bench file is w ritten.

Exp: 2aDesign entry simulation and implementation of 8 bit adder

Aim:

To design simulate and implement 8 bit adder in Spartan-3E FPGA

Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:

1) Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2) A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3) In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4) A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5) On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6) Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7) Now Select the behavioral Syntax first and then the Simulate behavioral.
8) Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9) After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11) After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View technology scheme
pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.

15) Then Select Implement design that is present on the left side of the w indow. Under
Implement design click translate map place and route.
16) Select generate programming file and Sw itch ON FPGA kit.
17) In this W indow click Configure target device manage configure Survey No.
18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click IC
and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.
Program:

8 BIT ADDER

module

adder(s,cout,a,b,cin);

output[7:0 ]s;

output

cout;

input[7:0 ]a,

b; input cin;

w ire c1,c2,c3,c4 ,c5,c6,c7;

fulladd

fa0 (s[0 ],c1,a[0 ],b[0 ],cin);

fulladd fa1(s[1],c2,a[1],b[1],c1);

fulladd fa2(s[2],c3,a[2],b[2],c2);

fulladd fa3(s[3],c4 ,a[3],b[3],c3);

fulladd fa4 (s[4 ],c5,a[4 ],b[4 ],c4 );

fulladd fa5(s[5],c6,a[5],b[5],c5);

fulladd fa6(s[6],c7,a[6],b[6],c6);

fulladd fa7(s[7],cout,a[7],b[7],c7);

endmodule
module fulladd(s,cout,a,b,cin);

output

s,cout;

input

a,b,cin;

xor(s,a,b,ci

n);

assign cout = ((a & b )|(b& cin)|( a &

cin)) ; endmodule

Output:
 Result:

Thus the 8 bit adder w as successfully designed using verilog HDL and implemented in
Spartan-3E FPGA.

Exp: 2bDesign entry simulation and implementation of 4 bit multiplier

Aim:

To design simulate and implement 4 bit multiplier in Spartan-3E FPGA

Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:

1)Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2)A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3)In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4)A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5)On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6)Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7)Now Select the behavioral Syntax first and then the Simulate behavioral.
8)Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9)After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11)After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View
technology scheme pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.

15) Then Select Implement design that is present on the left side of the w indow.
Under Implement design click translate map place and route.
16) Select generate programming file and Sw itch ON FPGA kit.
17) In this W indow click Configure target device manage configure Survey No.
18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click
IC and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.
Program:

module fourbitmulti(m,a,b);

input[3:0 ]a;
input[3:0 ]b;

output[7:0 ]m;

w ire[15:0 ]p;

w ire[12:1]s;

w ire[12:1]c;

and(p[0 ],a[0 ],b[0

]);
and(p[1],a[1],b[0 ]);
and(p[2],a[0 ],b[1]);

and(p[3],a[2],b[0 ]);

and(p[4 ],a[1],b[1]);

and(p[5],a[0 ],b[2]);

and(p[6],a[3],b[0 ]);

and(p[7],a[2],b[1]);

and(p[8],a[1],b[2]);

and(p[9],a[0 ],b[3]);

and(p[10 ],a[3],b[1]);

and(p[11],a[2],b[2]);

and(p[12],a[1],b[3]);

and(p[13],a[3],b[2]);

and(p[14 ],a[2],b[3]);

and(p[15],a[3],b[3]);

half ha1(s[1],c[1],p[1],p[2]);

half ha2(s[2],c[2],p[4 ],p[3]);

half ha3(s[3],c[3],p[7],p[6]);

full fa4 (s[4 ],c[4 ],p[11],p[10 ],c[3]);

full fa5(s[5],c[5],p[14 ],p[13],c[4 ]);

full fa6(s[6],c[6],p[5],s[2],c[1]);

full fa7(s[7],c[7],p[8],s[3],c[2]);

full fa8(s[8],c[8],p[12],s[4 ],c[7]);

full fa9(s[9],c[9],p[9],s[7],c[6]);

half ha10 (s[10 ],c[10 ],s[8],c[9]);

full fa11(s[11],c[11],s[5],c[8],c[10 ]);

full fa12(s[12],c[12],p[15],s[5],c[11]);

buf (m[0 ],p[0 ]);

buf (m[1],s[1]);

buf (m[2],s[6]);

buf (m[3],s[9]);

buf (m[4 ],s[10 ]);

buf (m[5],s[11]);

buf (m[6],s[12]);

buf

(m[7],c[12]);

endmodule

module half

(s,c0 ,x,y); input x,y;

output

s,c0 ;

xor(s,x,y)

;
and(c0 ,x,y);

endmodule

module

full(s,c0 ,x,y,cin);

input x,y,cin;

output

s,c0 ; w ire
s1,d1,d2;

half

ha_1(s1,d1,x,y);

half

ha_2(s,d2,s1,cin);

or

or_gate(c0 ,d2,d1);

endmodule
Output:

Result:

Thus the 4 bit multiplier w as successfully designed using verilog HDL and implemented in
Spartan FPGA.

Exp: 3Design entry simulation and implementation of Universal Shift Register

Aim:

To design simulate and implement a Universal Shift Register in Spartan-3E FPGA

 Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:

1)Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2)A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3)In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4)A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5)On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6)Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7)Now Select the behavioral Syntax first and then the Simulate behavioral.
8)Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9)After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11)After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View
technology scheme pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.
15) Then Select Implement design that is present on the left side of the w indow.
Under Implement design click translate map place and route.

16) Select generate programming file and Sw itch ON FPGA kit.

17) In this W indow click Configure target device manage configure Survey No.
18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click
IC and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.

Diagram:

Mode control
Register
S1 S0
Operation
0 0 No operation
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load
Program:

module

USR(A,g,clk,SLin,SRin,mode);

w ire[3:0 ]w ;

input[3:0 ]g;

input[1:0 ]mode;

input clk;
input

SLin,SRin;

output

[3:0 ]A;
mux4 _1M0 (w [0 ],A[0 ],A[1],SLin,g[0 ],mode);

mux4 _1M1(w [1],A[1],A[2],A[0 ],g[1],mode);

mux4 _1M2(w [2],A[2],A[3],A[1],g[2],mode);

mux4 _1

M3(w [3],A[3],SRin,A[2],g[3],mode);

dfff D0 (A[0 ],w [0 ],clk);

dfff D1(A[1],w [1],clk);

dfff D2(A[2],w [2],clk);

dfff

D3(A[3],w [3],clk);

endmodule

module

mux4 _1(y,i0 ,i1,i2,i3,mode);

input i0 ,i1,i2,i3;

input

[1:0 ]mode;

output reg y;

alw ays@ (mode,i3,i2,i1,i

0 ) begin

case(mode)
2'b0 0 :y=i0 ;
2'b0 1:y=i1;

2'b10 :y=i2;

2'b11:y=i3;

endca

se end

endmodule

module

dfff(q,d,clk);

input d,clk;

output reg q;

alw ays@ (posedg

e clk) q<=d;
endmodule

Output:

Input : g=10 10 (Decimal Value:10 ) sLin=1, sRin=1

Mode (S1,S0 )
Operation Output
S1 S0
No operation 0 0 0 0 0 0
Shift Right 0 1 10 0 0
Shift Left 1 0 0 0 0 1
Parallel Load 1 1 10 10
 Result:

Thus the 4 bit universal shift register w as successfully designed and implemented in FPGA

Exp: 3Design Memories using HDL (Single Port RAM)

Aim:

To design simulate and implement a Single Port RAM in Spartan-3E FPGA

Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:

1) Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2) A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3) In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4) A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5) On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6) Then Select the Simulation Tool bar and select the file name of the program w ritten.
 Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7) Now Select the behavioral Syntax first and then the Simulate behavioral.
8) Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9) After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11) After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View technology scheme
pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.
15) Then Select Implement design that is present on the left side of the w indow. Under
Implement design click translate map place and route.

16) Select generate programming file and Sw itch ON FPGA kit.

17) In this W indow click Configure target device manage configure Survey No.
18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click IC
and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.

Diagram:

Circuit Diagram
Program:
RTL Design Verilog Code for Single Port RAM

timescale 1ns / 1ps

module single_port_ram(data_in ,

ram_address,w rite_enable,clk,data_out); input [7:0 ]data_in;

input [5:0 ]

ram_address;

input

w rite_enable;

input clk;
output [7:0 ]data_out;

reg [7:0 ] ram_memory[31:0 ];

// a 32 by te ( 32*8 bit)

RAM reg [5:0 ]

address_register;

alw ays @ (posedge

clk) begin
if (w rite_enable)
// w rite operation

ram_memory[ram_address] <=

data_in; else address_register <=

ram_address;

end assign data_out =

ram_memory[address_register]; Endmodule

Program:

Test Bench Code for Single Port RAM

timescale 1ns / 1ps

module

single_port_ram_testbench;

reg [7:0 ]data_in;

reg [5:0 ]

ram_address; reg

w rite_enable;

reg clk;

w ire [7:0 ]data_out;

single_port_ram ram1(data_in ,

ram_address,w rite_enable,clk,data_out); initial begin // clock

initialization
clk =1'b1;

forever #10
clk=~clk; end

initi

al

begi

n

// w riting data into the memory

w rite_enable =1'b1;
#20 ;

ram_address=

5'd0 ; data_in =

8'h10 ; #20 ;

ram_address=

5'd2; data_in =

8'h11; #20 ;

ram_address=

5'd7; data_in =

8'haf; #20 ;

//reading data from the

memory w rite_enable = 1'b0 ;

ram_address=5'd0 ;
#20 ;

ram_address=5'

d2; #20 ;

ram_address=5'
d7; #20 ;

$finish;

end

endmod

ule

Output:

The output of the Test bench simulation ( w aveform) is as follow :

 Result:

Thus the design simulate and implement a Single Port RAM in Spartan-3E FPGA is
verified Successfully

Exp: 5Design entry simulation and implementation of Finite State Machine

Aim:

To design simulate and implement a finite state machine in Spartan-3E FPGA

Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:

1)Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2)A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3)In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4)A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5)On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6)Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7)Now Select the behavioral Syntax first and then the Simulate behavioral.
8)Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9)After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11)After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View
technology scheme pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.
15) Then Select Implement design that is present on the left side of the w indow.
Under Implement design click translate map place and route.

16) Select generate programming file and Sw itch ON FPGA kit.

17) In this W indow click Configure target device manage configure Survey No.
18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click
IC and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.

Theory:

The finite state machine is a mathematical model of computation. It is an

abstract machine that can be in exactly one of a finite number of states at any given
time. The finite state machine can change from one state to another in response to
some inputs. The change from one state to another is called a transition. There are
tw o types of finite state machines that generate output. They are Mealy state and
Moore state machine. In Moore state machine the output depends only on the current
state. The advantages of the Moore model are a simplification of the behavior. In
Mealy state machine, the output depends on both current state and input.

Program:

module

seqckt(y,x,clk,rst);

input x,clk,rst;

output

y; reg

y;
reg[2:0 ]state;

alw ays@ (posedge clk or posedge

rst) begin

if(rs

t)

begi

n

state<=3'b0

0 0 ; y<=0 ;

end

else

begi

n
case(state)

3'b0 0 0 :be

gin if(x)

begin

state<=3'b0

0 1; y<=0 ;

end

end

3'b0 0

1:

begi

if(x)

begi
n

state<=3'b0

0 1; y<=0 ;

end

else

begi

n

state<=3'b0 1

0 ; y<=0 ;

end

end

3'b0 1

0 :

begi

if(x)

begi

n

state<=3'b0

0 1; y<=0 ;

end

else

begin

state<=3'b0 11

; y<=0 ;

end
end

3'b0 11

:

begi

if(x)

begi

n

state<=3'b10

0 ; y<=1;

end

else

begi

n

state<=3'b0

0 0 ; y<=0 ;

end

end

3'b10

0 :

begi

if(x)

begi

n

state<=3'b0

0 1; y<=0 ;
end

else

begi

n
state<=3'b0 0 0 ;

y<=0 ;

en

en

d

endca

se end

end

endmodul

e Output:
 Result

Thus the sequence detector using Moore state machine for the sequence 10 0 1w as
successfully designed using verilog HDL and implemented in cyclone II FPGA

Exp: 6Design 8-bit synchronous up/dow n counter using HDL.

Aim:

To design and implement an 8bit Up/Dow n Counter w ith enable input and synchronous clear

Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:

1) Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2) A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3) In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4) A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5) On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6) Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7) Now Select the behavioral Syntax first and then the Simulate behavioral.
8) Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9) After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11) After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View technology scheme
pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.
15) Then Select Implement design that is present on the left side of the w indow. Under
Implement design click translate map place and route.

16) Select generate programming file and Sw itch ON FPGA kit.

17) In this W indow click Configure target device manage configure Survey No.
18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click IC
and Select program.
20) The program is successfully dumped into the kit and it displays as Program succeeded. The
Inputsare given using the sw itch in the kit and the corresponding output can be seen.

Theory:
These types of counters fall under the category of synchronous controller counter. Here the
mode control input is used to decide w hether w hich sequence w ill be generated by the
counter.In this case, mode control input is used to decide w hether the counter w ill perform
up counting or dow n counting. Designing of such a counter is the same as designing a
synchronous counter but the extra combinational logic for mode control input is required.

Program:
module
UpDownCounter(clk,enable,reset,mode,count,tc);
input clk,enable,reset,mode;
output reg
[7:0 ]count; output
reg tc;
alw ays @ (posedge
clk) begin
if(enable
) begin
if(reset)
begin
count=0
; tc=0 ;
end
else
begi
n
if(mode==0 )
begin
count=count+1;

if(count==255)
tc=1;
else
tc=0 ;
end
else
begi
n
count=count-1;
<if(count==0 )
tc=1;

else
tc=0
;
end
end
end
end
endmodule
 Output:

Result
Thus the design and implementation of an 8bit Up/Dow n Counter w ith enable input and
synchronous w as verified successfully

Exp: 7Design 8-bit Asynchronous up/dow n counter using HDL.

Aim:

To design and implement an 8bit Up/Dow n Counter w ith enable input and asynchronous clear
 Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:

1) Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2) A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3) In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4) A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5) On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6) Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7) Now Select the behavioral Syntax first and then the Simulate behavioral.
8) Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9) After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11) After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View technology scheme
pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.
15) Then Select Implement design that is present on the left side of the w indow. Under
Implement design click translate map place and route.

16) Select generate programming file and Sw itch ON FPGA kit.

17) In this W indow click Configure target device manage configure Survey No.
18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click IC
and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.

Theory:

Asynchronous counters can be easily designed by T

flip flop or D flip flop. These are also called as Ripple counters, and are used in low speed
circuits. They are used as Divide by- n counters, w hich divide the input by n, w here n is an
integer. Asynchronous counters are also used as Truncated counters

Program:

rese
Coun
else
if(UpOrDow
if Coun
Coun
upordow n_cou ( ,re ,UpOrDo Co module);
//input ports and their sizes
,UpOrDo input Clk,reset;
//output ports and
their size output [3 : 0 ]
Count;

//
Internal variables
reg [3 : 0 ] Count
= 0 ;
alw ays @ (posedge(Clk) or
posedge(reset)) begin

if(

== 1)

<= 0 ;

== 1) //Up mode selected

== 15)
<= 0 ;
 else

Count <= Count + 1; //Incremend

Counter else //Dow n mode selected
if(Count == 0 )

Count <= 15;

else
Count <= Count - 1; //Decrement counter
end

endmodule

Testbench for counter:

module tb_counter;

//
Inputs
reg Clk;
reg
reset;
reg UpOrDow n;

// Outputs
w ire [3:0 ] Count;

// Instantiate the Unit Under Test (UUT)

upordow n_counter uut (
.Clk(Clk),
.reset(reset),
.UpOrDow n(UpOrDow n),
.Count(Count)
);
 //Generate
clock w ith 10 ns clk period.
initial Clk = 0 ;
alw ays #5 Clk = ~Clk;

initial begin
// Apply
Inputs reset
= 0 ;
UpOrDow n = 0 ;
#30 0 ;
UpOrDow n = 1;
#30 0 ;
reset = 1;
UpOrDow n = 0 ;
#10 0 ;
reset = 0 ;
end

endmodule

Output:
 Result
Thus the design and implementation of an 8bit Up/Dow n Counter w ith enable input and
synchronous w as verified successfully

Exp. No.8Design and simulate CMOS Basic gates and Flipflops

Aim:

To design and simulate a CMOS basic logic gates (NAND and NOR) and flipflops (D,T,
JK flipflops) using Dsch2 and microw ind tools and perform the prelayout and post
layout simulations.

Apparatus Required:

Dsch2 and microw ind

Theory:

NAND gate: A NAND gate can be implemented using four MOS transistors i.e.
tw o pmos and tw o nmos as the inputs of the gate is tw o. pmos are connected in
parallel w hile nmos are connected in series, Vdd is supplied to the parallel
combination of pmos w hile the series combination of nmos is grounded. Inputs a &
b are applied to the gate terminals of all FETs, and the output f is obtained from the
common junction of these series and parallel combinations as illustrated in NAND
circuit.

NOR gate: The tw o-input NOR gate show n on the left is built from four
transistors. The parallel connection of the tw o n- channel transistors betw een GND
and the gate- output ensures that the gateoutput is driven low (logical 0 ) w hen
either gate input A or B is high (logical 1). The complementary series- connection of
the tw o transistors betw een VCC and gate- output means that the gate- output is
driven high (logical 1) w hen both gate inputs are low (logical 0 ).

Procedure:

1) Opening Dsch3 file.

2) Selecting the nNMOS transistor from Symbol Library on top right and
dragging it to the main screen.
3) Selecting the nNMOS transistor from Symbol Library on top right and
dragging it to the main screen.
4) Similarly selecting supply and ground symbols from Symbol Library and
dragging them to the main screen.
5) Connecting all symbols as show n in the figure.
6) Use add a line command to connect different nodes of these symbols
7) Adding a Button Symbol to the input and Light symbol to the output of the
circuit from Symbols library and completes the schematic diagram. Then
save as the file using a particular name.
8) Then go to simulate tab and click start simulation. After few seconds
stop the simulation and click on timing diagram to view the outputs.
9) Go to file and click on make verilog file and save it
10) Open the microw ind file. Choose Compile verilog file option and select the
respective file from dsch2 folder. Compile it and back to editor to view the
automatic genrated layout.
11) Finally simulate the file and get the final output
FLIP FLOPS:

D FLIP FLOP
D Flip flop Schematic

Layout of D flip flop

Result:

Thus the CMOS basic gates and flipflops w ere designed and simulated successfully.

Exp: 9Design and simulate a 4 bit synchronous counter using Flip flops
Aim:

To design and simulate a 4 bit synchronous counter using flip flop w ith the
tools Dsch2 and microw ind.

Theory:

In this circuit, the single clock signal is directly connected to all flipflops, so
that all flipflops change state at the same time. The result of this synchronization is
that all the individual output bits changing state at exactly the same time in
response to the common clock signal w ith no ripple effect and therefore, no
propagation delay. Obviously, this counter consists of four identical stages w ith a
D- type flipflop, an XOR- gate, and a tw o-input AND- gate each. The XOR- gate in front
of the D input of the flipflop basically converts the D- type flipflop into a toggle (T-
type) flipflop. Synchronous counters are sometimes called parallel counters as the
clock is fed in parallel to all flip- flops. The inherent memory circuit keeps track of
the counters present state. The count sequence is controlled using logic gates.
Overall faster operation may be achieved compared to Asynchronous counters.

Procedure:

Opening Dsch3 file.

Selecting the D flipflop from Symbol Library on top right and dragging it to the main
screen.
Selecting the XOR, AND gate from Symbol Library on top right and
dragging it to the main screen.
Similarly selecting supply and ground symbols from Symbol Library and
dragging them to the main screen. Select the digit symbol to display the
output.
Connecting all the symbols as show n in the figure.
Use add a line command to connect different nodes of these symbols
Adding a Button Symbol to the input and Light symbol to the output of the
circuit from Symbols library and completes the schematic diagram. Then
save as the file using a particular name.
Then go to simulate tab and click start simulation. After few seconds
stop the simulation and click on timing diagram to view the outputs.
Go to file and click on make verilog file and save it
Open the microw ind file. Choose Compile verilog file option and select the
respective file from dsch2 folder. Compile it and back to editor to view the
automatic generated layout.
Finally simulate the file and get the final output.

Schematic of 4 bit synchronous counter

Layout of 4 bit synchronous counter
 RESULT:

Thus the 4 bit synchronous counter using flipflop w as designed and simulated successfully.

Exp: 10 Design a CMOS inverting amplifier circuit

Aim:
 To design and simulate the simple five transistor differential amplifier circuit
and measure the parameters using Tanner EDA tools.

Apparatus Required:

PC w ith w indow s, Tanner EDA tools v13.0

Procedure:

1. Click on the S-Edit 13.0 . In the w indow select the file

2. Create new design by Click file New New Design

3. Enter the design name and select the path to save the design.

4. Create new cell view Cell new view Select the parameters and give ok.

5. Click add available in library w indow and select the library file.

6. Select devices in the library drag required PMOS and NMOS components from
the symbol brow ser and design five transistor differential amplifier circuit.

7. Common mode Inputs are applied to the circuit.

8. To open T spice w indow click Tools T- Spice.

9. Insert technology file and required comments using insert comment option in T- Spice.

10. Run the simulation by clicking simulation Run simulation.

11. Output w aveform is view ed in the w aveform view er (W- edit) now verify the result.

12. Input and output voltages are measured and tabulated for common mode.

13. Step 7 to step 12 is repeated for the differential mode.

14. Now calculate the gain, ICMR, and CMRR.

Theory:

CMOS inverter act as an inverting linear amplifier w ith a characteristics of Vout

=-AVin w here A is the stage gain. Near the input threshold voltage the, the CMOS
inverter acts as an inverting linear amplifier. It should be noted that the CMOS
inverter w hen used as a logic element is in reality an analog amplifier operated under
saturating condition. It can also be view ed as an nMOS common source

amplifier driving a pMOS common source amplifier.. For amplifiers operating at very
low supply voltages, the inverting amplifier stages should be applied. This circuits
display an output voltage range that is nearly equal to the supply voltage and can
operate on supply voltages.

Output:

Result:
Thus CMOS inverting amplifier circuit w as designed and simulated successfully using Tanner
EDA tool.

Exp: 11Design a CMOS Common Source, Common Drain and Common Gate Amplifier
circuits
Aim:

To design and simulate the Common source, drain and common gate amplifier
circuit using Tanner EDA tools.

Apparatus Required:

PC w ith w indow s, Tanner EDA tools v13.0

Procedure:

1. Click on the S-Edit 13.0 . In the w indow select the file

2. Create new design by Click file New New Design

3. Enter the design name and select the path to save the design.

4. Create new cell view Cell new view Select the parameters and give ok.

5. Click add available in library w indow and select the library file.

6. Select devices in the library drag required PMOS and NMOS components from
the symbol brow ser and design five transistor differential amplifier circuit.

7. Common mode Inputs are applied to the circuit.

8. To open T spice w indow click Tools T- Spice.

9. Insert technology file and required comments using insert comment option in T- Spice.

10. Run the simulation by clicking simulation Run simulation.

11. Output w aveform is view ed in the w aveform view er (W- edit) now verify the result.

12. Input and output voltages are measured and tabulated for common mode.

Theory:

Common Drain Amplifier (Source Follow er):

The common drain amplifier figure show s the source follow er circuit in w hich
drain terminal of the device is common. In this circuit the drain terminal is directly
connected to VDD. In CS amplifier analysis w e have seen that in order to achieve the
high voltage gain the load impedance should be as high as possible. Therefore for
low impedance load the buffer must be placed after the amplifier to drive the load
w ith negligible loss of the signal level. The source follow er thus w orked as a buffer
stage. The

source follow er is also called as the common drain amplifier. In this circuit, the signal
at the gate is sensed and drives the load at the source w hich allow s the source
potential to follow the gate voltage. The draw back of source follow er is nonlinearity
due to body effect and poor driving capability of the input signal.

Common Source Amplifier:

In this circuit the MOSFET converts variations in the gate-source voltage into a
small signal drain current w hich passes through a resistive load and generates the
amplified voltage across the load resistor. the voltage gain of CS amplifier is depends
upon the transconductance gm, the linear resistor ro and load. In order to increase
the gain w e have to increase the gm. Inturn w e have to increase the ratio.

Common Gate amplifier:

In common source amplifier and source follow er circuits, the input signal are
applied to the gate of a MOSFET. It is also possible to apply the input signal to the
source terminal by keeping common gate terminal. This type of amplifier is called as
common gate amplifier. The CG amplifier in w hich the input signal is sensed at the
source terminal and the output is produced at the drain terminal. The gate terminal is
connected to VB i.e. dc potential w hich w ill maintain the proper operating conditions.

Circuit Diagram:

Common Source:

Output:
Common Gate:
 Output:

Common Source:

Output:
Result:

Thus the common source, drain and gate amplifier circuit w as design and
simulated successfully using tanner EDA tool.

Exp:12Design a 5 transistor differential amplifier circuit

Aim:

To design and simulate the simple five transistor differential amplifier circuit
and measure the parameters using Tanner EDA tools.

Apparatus Required:

PC w ith w indow s, Tanner EDA tools v13.0

Procedure:

1. Click on the S-Edit 13.0 . In the w indow select the file

2. Create new design by Click file New New Design

3. Enter the design name and select the path to save the design.

4. Create new cell view Cell new view Select the parameters and give ok.

5. Click add available in library w indow and select the library file.

6. Select devices in the library drag required PMOS and NMOS components from
the symbol brow ser and design five transistor differential amplifier circuit.

7. Common mode Inputs are applied to the circuit.

8. To open T spice w indow click Tools T- Spice.

9. Insert technology file and required comments using insert comment option in T- Spice.

10. Run the simulation by clicking simulation Run simulation.

11. Output w aveform is view ed in the w aveform view er (W- edit) now verify the result.

12. Input and output voltages are measured and tabulated for common mode.

13. Step 7 to step 12 is repeated for the differential mode.

14. Now calculate the gain, ICMR, and CMRR.

Theory:

The differential amplifier is a form of amplifier that strengthens the difference

betw een tw o voltages in a circuit. In electronic designs, w e use a differential
amplifier to produce high voltage gain and high CMRR. Its main characteristics
include very low bias current input, very high impedance input,

and very low offset voltage. The essential benefit of differential mode from
common mode is its higher immunity to noise. Also, differential amplifiers provide
better immunity to environmental noise, improve linearity, and more upper signal
sw ing. It may operate in tw o modes: common mode and differential mode. The
common method produces a zero voltage output result w hile the differential mode
produces a high voltage output result. Given this, the differential amplifier generally
has high CMRR. If the tw o input voltages are of similar value, the amp provides an
output voltage value that is almost zero. W hen the tw o input voltages are unequal,
the amplifier produces a high voltage output. The remarkable advantage of
differential operation over common mode operation is its higher immunity to noise.

Circuit Diagram:

Differential Mode

Common mode:
Outputs:
Result:
 Thus the simple five transistor differential amplifier w as simulated and gain,
ICMR, and CMRR are calculated using Tanner EDA tools

Exp: 13Design entry simulation and implementation of 4 bit Ripple Carry Adder
Aim:

To design simulate and implement 4 - bit Ripple Carry Adder in Spartan-3E FPGA

Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:
1)Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2)A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3)In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4)A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5)On the left side choose Synthesize XST. If the Synthesize is successful than w e have
to select Check Syntax for checking the Syntax.
6)Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7)Now Select the behavioral Syntax first and then the Simulate behavioral.
8)Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9)After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11)After input pin planning –port Synthesis, new w indow w ill open, in that Select Scalar
posts. Now click Site and assign the input and output pin numbers that is present in
the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View
technology scheme pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.
15) Then Select Implement design that is present on the left side of the w indow.
Under Implement design click translate map place and route.
16) Select generate programming file and Sw itch ON FPGA kit.
17) In this W indow click Configure target device manage configure Survey No.

18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click
IC and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.

Program:

4 - BIT RIPPLE CARRY ADDER

module fulladder(X, Y, Ci, S,
Co); input X, Y, Ci;
output S, Co;
w ire
w 1,w 2,w 3;
//Structural code for one bit full
adder xor G1(w 1, X, Y);
xor G2(S, w 1, Ci);
and G3(w 2, w 1, Ci);
and G4 (w 3, X, Y);
or G5(Co, w 2,
w 3); endmodule

module rippe_adder(X, Y, S,
Co); input [3:0 ] X, Y;// Tw o
4 -bit inputs output [3:0 ] S;
output Co;
w ire w 1, w 2, w 3;
// instantiating 4 1-bit full adders in
Verilog fulladder u1(X[0 ], Y[0 ], 1'b0 ,
S[0 ], w 1);
fulladder u2(X[1], Y[1], w 1, S[1], w 2);
fulladder u3(X[2], Y[2], w 2, S[2], w 3);
fulladder u4 (X[3], Y[3], w 3, S[3],
Co); endmodule
Output:
 Result:

Thus the 4 - bit Ripple Carry Adder w as successfully designed using verilog HDL and
implemented in Spartan FPGA.

Exp: 14 Design entry simulation and implementation of 32 to 1multiplexer using 2 to 1

Aim:

To design simulate and implement 32- to-1multiplexer using 2- to-1multiplexer in Spartan-3E

FPGA

Apparatus Required:

Xilinx ISE softw are, Spartan-3E FPGA, Personal computer

Procedure:
1)Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box w ill
appear and give the name of the file and select Next.
2)A Project Setting dialog box w ill appear, choose the Simulator as ISIM (VHDL /
Verilog) & click Next. A project Summary dialog box w ill appear in that Select Finish.
3)In the project toolbar, select New VHDL Source. Then Select the file type as Verilog
module and give name to the file.
4)A dialog boxy appears and assign the input and Output ports and click Ok. A
programming w indow w ill appear and w rite the required program and save it.
5)On the left side choose Synthesize XST. If the Synthesize is successful than w e
have to select Check Syntax for checking the Syntax.
6)Then Select the Simulation Tool bar and select the file name of the program w ritten.
Click Isim Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7)Now Select the behavioral Syntax first and then the Simulate behavioral.
8)Now the output w indow w ill open the assigned input and output ports. Give the
inputs to the ports by selecting force Constant and click Run all to View the outputs.
9)After Simulation is over, select Implementation. Under Implementation select User
Constraint and then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11)After input pin planning –port Synthesis, new w indow w ill open, in that Select
Scalar posts. Now click Site and assign the input and output pin numbers that is
present in the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize View RTL port. Click Logic gates and then View
technology scheme pic (LUT).
14) Now Select Summation ∑ and select Analysis synthesis report.
15) Then Select Implement design that is present on the left side of the w indow.
Under Implement design click translate map place and route.
16) Select generate programming file and Sw itch ON FPGA kit.
17) In this W indow click Configure target device manage configure Survey No.

18) Click No. It show s the dialog box as Welcome to Impart, click OK and Select Yes
Configure. Now give the filename and Open SPI or BPT Prom give number.
19) A W indow w ill Open, click Device 1 OK. Click Identify Succeed IC. Right Click
IC and Select program.
20) The program is successfully dumped into the kit and it displays as Program
succeeded. The Inputs are given using the sw itch in the kit and the corresponding
output can be seen.

Program:

32-TO-1MULTIPLEXER USING 2-TO-1MULTIPLEXER

module mux2x32to32( DataOut,Data0 , Data1,
Select); output [31:0 ] DataOut; // Data Out
input [31:0 ] Data0 , Data1; // Data In 1
and 2 input Select;
// if Select = 0 , DataOut = Data0
// otherw ise, DataOut = Data1

mux2_1
mux0 (DataOut[0 ],Data0 [0 ],Data1[0 ],Select);
mux2_1
mux1(DataOut[1],Data0 [1],Data1[1],Select);
mux2_1
mux2(DataOut[2],Data0 [2],Data1[2],Select);
mux2_1
mux3(DataOut[3],Data0 [3],Data1[3],Select);
mux2_1
mux4 (DataOut[4 ],Data0 [4 ],Data1[4 ],Select);
mux2_1
mux5(DataOut[5],Data0 [5],Data1[5],Select);
mux2_1
mux6(DataOut[6],Data0 [6],Data1[6],Select);
mux2_1
mux7(DataOut[7],Data0 [7],Data1[7],Select);
mux2_1
mux8(DataOut[8],Data0 [8],Data1[8],Select);
mux2_1
mux9(DataOut[9],Data0 [9],Data1[9],Select);
mux2_1
mux10 (DataOut[10 ],Data0 [10 ],Data1[10 ],Select);
mux2_1
mux11(DataOut[11],Data0 [11],Data1[11],Select);
mux2_1
mux12(DataOut[12],Data0 [12],Data1[12],Select);
mux2_1
mux13(DataOut[13],Data0 [13],Data1[13],Select);
mux2_1
mux14 (DataOut[14 ],Data0 [14 ],Data1[14 ],Select);
mux2_1
mux15(DataOut[15],Data0 [15],Data1[15],Select);
mux2_1
mux16(DataOut[16],Data0 [16],Data1[16],Select);
mux2_1
mux17(DataOut[17],Data0 [17],Data1[17],Select);
mux2_1
mux18(DataOut[18],Data0 [18],Data1[18],Select);
mux2_1
mux19(DataOut[19],Data0 [19],Data1[19],Select);
mux2_1
mux20 (DataOut[20 ],Data0 [20 ],Data1[20 ],Selec
t); mux2_1
mux21(DataOut[21],Data0 [21],Data1[21],Select);
mux2_1
mux22(DataOut[22],Data0 [22],Data1[22],Select)
; mux2_1
mux23(DataOut[23],Data0 [23],Data1[23],Select
); mux2_1
mux24 (DataOut[24 ],Data0 [24 ],Data1[24 ],Selec
t); mux2_1
mux25(DataOut[25],Data0 [25],Data1[25],Select)
; mux2_1
mux26(DataOut[26],Data0 [26],Data1[26],Select
); mux2_1
mux27(DataOut[27],Data0 [27],Data1[27],Select)
; mux2_1
mux28(DataOut[28],Data0 [28],Data1[28],Select
); mux2_1
mux29(DataOut[29],Data0 [29],Data1[29],Select
); mux2_1
mux30 (DataOut[30 ],Data0 [30 ],Data1[30 ],Sele
ct); mux2_1
mux31(DataOut[31],Data0 [31],Data1[31],Select);

endmodule
// fpga4 student.com: FPGA projects, Verilog projects, VHDL projects
// Verilog project: Verilog code for Multiplexer
// Verilog code for 2x5- to-5 Multiplexer
module mux2x5to5( AddrOut,Addr0 , Addr1,
Select); output [4 :0 ] AddrOut; // Address Out
input [4 :0 ] Addr0 , Addr1; // Address In 1
and 2 input Select;
mux2_1
mux0 (AddrOut[0 ],Addr0 [0 ],Addr1[0 ],Selec
t); mux2_1
mux1(AddrOut[1],Addr0 [1],Addr1[1],Select);
mux2_1
mux2(AddrOut[2],Addr0 [2],Addr1[2],Select)
; mux2_1
mux3(AddrOut[3],Addr0 [3],Addr1[3],Select
); mux2_1
mux4 (AddrOut[4 ],Addr0 [4 ],Addr1[4 ],Selec
t); endmodule
// fpga4 student.com: FPGA projects, Verilog projects, VHDL projects
// Verilog project: Verilog code for Multiplexer
// Verilog code for 2- to-1
Multiplexer module
mux2_1(O,A,B,sel);
// if sel = 0 , O = A
// if sel = 1, O =B
output O;
input A,B,sel;
not #(50 ) not1(nsel,sel);
and #(50 ) and1(O1,A,nsel);
and #(50 ) and2(O2,B,sel);
or #(50 ) or2(O,O1,O2);
endmodule

Output:
Result:
Thus the 4 - bit Ripple Carry Adder w as successfully designed using verilog HDL and
implemented in Spartan FPGA.