Chapter-8

Q.1. Describe the analog to digital conversion of a signal.

Analog to digital conversion (ADC) is the process of converting continuous analog signals
into discrete digital representations. This conversion is essential for various digital systems to
process and manipulate analog data. Here's a simplified explanation of the process:

Sampling: The first step in ADC is sampling, where the continuous analog signal is sampled
at regular intervals. The rate at which samples are taken is called the sampling rate or
frequency, usually measured in samples per second (Hz) or kilohertz (kHz). According to
Nyquist-Shannon sampling theorem, the sampling frequency must be at least twice the
highest frequency component of the analog signal to avoid aliasing.

Quantization: Once sampled, each amplitude value is quantized into a discrete

representation. Quantization involves mapping each sampled value to the closest available
digital value within a finite set of possible values. This process introduces quantization error,
which is the difference between the actual analog value and the quantized digital
representation.

Encoding: After quantization, the quantized values are encoded into binary format. This
typically involves assigning a binary code to each quantization level. The number of bits used
for encoding determines the resolution and dynamic range of the digital signal. Higher bit
depths result in finer quantization and better representation of the original analog signal but
require more storage or bandwidth.
Q.2. Describe the digital to analog conversion of a signal.

Digital-to-analog conversion is the process of changing one of the characteristics of an analog

signal based on the information in digital data.

A sine wave is defined by three characteristics: amplitude, frequency, and phase. When we
change anyone of these characteristics, we create a different version of that wave. So, by
changing one characteristic of a simple electric signal, we can use it to represent digital data.

There are three mechanisms for modulating digital data into an analog signal: amplitude shift
keying (ASK), frequency shift keying (FSK), and phase shift keying (PSK). In addition, there
is a fourth (and better) mechanism that combines changing both the amplitude and phase,
called quadrature amplitude modulation (QAM).

Bandwidth

The required bandwidth for analog transmission of digital data is proportional to the signal
rate except for FSK, in which the difference between the carrier signals needs to be added.

Carrier Signal

In analog transmission, the sending device produces a high-frequency signal that acts as a
base for the information signal. This base signal is called the carrier signal or carrier
frequency. The receiving device is tuned to the frequency of the carrier signal that it expects
from the sender. Digital information then changes the carrier signal by modifying one or
more of its characteristics (amplitude, frequency, or phase). This kind of modification is
called modulation (shift keying).

1. Amplitude Shift Keying:

In amplitude shift keying, the amplitude of the carrier signal is varied to create signal
elements. Both frequency and phase remain constant while the amplitude changes.

ASK is normally implemented using only two levels. This is referred to as binary amplitude
shift keying or on-off keying (OOK). The peak amplitude of one signal level is 0; the other is
the same as the amplitude of the carrier frequency. The following figure gives a conceptual
view of binary ASKS.

Implementation:

If digital data are presented as a unipolar NRZ digital signal with a high voltage of 1V and a
low voltage of 0V, the implementation can achieved by multiplying the NRZ digital signal by
the carrier signal coming from an oscillator which is represented in the following figure.
When the amplitude of the NRZ signal is 1, the amplitude of the carrier frequency is held;
when the amplitude of the NRZ signal is 0, the amplitude of the carrier frequency is zero.

Bandwidth for ASK:

The carrier signal is only one simple sine wave, but the process of modulation produces a
non-periodic composite signal. This signal has a continuous set of frequencies. As we expect,
the bandwidth is proportional to the signal rate (baud rate).

However, there is normally another factor involved, called d, which depends on the
modulation and filtering process. The value of d is between 0 and 1. This means that the
bandwidth can be expressed as shown, where S is the signal rate and the B is the bandwidth.

B = (1 +d) x S

The formula shows that the required bandwidth has a minimum value of S and a maximum
value of 2S. The most important point here is the location of the bandwidth. The middle of
the bandwidth is where fc the carrier frequency, is located. This means if we have a bandpass
channel available, we can choose our fc so that the modulated signal occupies that bandwidth.
This is in fact the most important advantage of digital-to- analog conversion.

[NB : The writing below for question two only for understanding
comprehensively]

2. Frequency Shift Keying

In frequency shift keying, the frequency of the carrier signal is varied to represent data. The
frequency of the modulated signal is constant for the duration of one signal element, but
changes for the next signal element if the data element changes. Both peak amplitude and
phase remain constant for all signal elements.
Binary FSK (BFSK)

One way to think about binary FSK (or BFSK) is to consider two carrier frequencies. In the
following Figure, we have selected two carrier frequencies f1 and f2. We use the first carrier
if the data element is 0; we use the second if the data element is 1.
The above figure shows, the middle of one bandwidth is f1 and the middle of the other is f2.
Both f1 and f2 are ∆f apart from the midpoint between the two bands. The difference between
the two frequencies is 2∆f.

Implementation:

There are two implementations of BFSK: non-coherent and coherent. In non-coherent BFSK,
there may be discontinuity in the phase when one signal element ends and the next begins. In
coherent BFSK, the phase continues through the boundary of two signal elements. Non-
coherent BFSK can be implemented by treating BFSK as two ASK modulations and using
two carrier frequencies. Coherent BFSK can be implemented by using one voltage-controlled
oscillator (VCO) that changes its frequency according to the input voltage.

The following figure shows the simplified idea behind the second implementation. The input
to the oscillator is the unipolar NRZ signal. When the amplitude of NRZ is zero, the oscillator
keeps its regular frequency; when the amplitude is positive, the frequency is increased.
Bandwidth for BFSK:

The above figure shows the bandwidth of FSK. Again the carrier signals are only simple sine
waves, but the modulation creates a non-periodic composite signal with continuous
frequencies. We can think of FSK as two ASK signals, each with its own carrier frequency f1
and f2. If the difference between the two frequencies is 2∆f, then the required bandwidth is

B=(l+d)XS+2∆f

3. Phase Shift Keying:

In phase shift keying, the phase of the carrier is varied to represent two or more different
signal elements. Both peak amplitude and frequency remain constant as the phase changes.

Binary PSK (BPSK):

The simplest PSK is binary PSK, in which we have only two signal elements, one with a
phase of 0°, and the other with a phase of 180°. The following figure gives a conceptual view
of PSK. Binary PSK is as simple as binary ASK with one big advantage-it is less susceptible
to noise. In ASK, the criterion for bit detection is the amplitude of the signal. But in PSK, it is
the phase. Noise can change the amplitude easier than it can change the phase. In other
words, PSK is less susceptible to noise than ASK. PSK is superior to FSK because we do not
need two carrier signals.
Q.3. Describe TTL NAND Gate.
In a TTL (Transistor-Transistor Logic) NAND gate with three inputs and a +5V power
supply, the basic working principle remains the same as with two inputs. The gate will
produce a low output (logic 0) only when all three inputs are high (logic 1). Let's break down
the operation of the TTL NAND gate with three inputs using transistors T1, T2, and T3:

Components:

Transistors: T1, T2, and T3.

Resistors: Various resistors are used to bias the transistors and limit current flow.

Working Principle:

Input Stage:

Transistor T1, T2, and their corresponding input resistors form the input stage.

 Each transistor and its associated input resistor are arranged similarly to a basic TTL
NAND gate but replicated for each input.
 When any input is low (logic 0), the corresponding transistor is off, and no current
flows through it.
 When any input is high (logic 1), the corresponding transistor turns on, allowing
current to flow through it.

Transistor T3:

 Transistor T3 acts as the output stage, similar to the two-input NAND gate.
 The base of transistor T3 is connected to the emitters of transistors T1, T2, and
potentially another transistor for the third input (T3, for example).
 When all three inputs are high (logic 1), all three transistors T1, T2, and T3 conduct,
providing a path for current to flow through the base of transistor T3.
 When current flows through the base of transistor T3, it turns on, allowing current to
flow from Vcc (positive supply voltage) through the transistor and resistor to ground
(logic 0).

Output:

 The output of the TTL NAND gate is taken from the collector of transistor T3.
 When transistor T3 is on (due to all inputs being high), the output is pulled low (logic
0).
 When transistor T3 is off (due to any input being low), the output is pulled high (logic
1) by the pull-up resistor connected to Vcc.

Overall, the TTL NAND gate with three inputs operates similarly to the two-input version,
but with additional input stages replicated for each input. It produces a low output only when
all inputs are high, following the NAND gate's truth table.