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Digital System Design-Module01-Introduction

The document outlines the course structure for Digital System Design (EE-474) at Mirpur University, focusing on high-level digital design methodologies using VHDL/Verilog. It includes course objectives, literature, examination details, and key topics such as hardware description languages and design flow. The course aims to equip students with skills to model, analyze, and design digital circuits using Verilog HDL and FPGA tools.

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Muhammad Faizan
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10 views17 pages

Digital System Design-Module01-Introduction

The document outlines the course structure for Digital System Design (EE-474) at Mirpur University, focusing on high-level digital design methodologies using VHDL/Verilog. It includes course objectives, literature, examination details, and key topics such as hardware description languages and design flow. The course aims to equip students with skills to model, analyze, and design digital circuits using Verilog HDL and FPGA tools.

Uploaded by

Muhammad Faizan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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MIRPUR UNIVERSITY OF SCIENCE AND TECHNOLOGY (MUST), MIRPUR

DEPARTMENT OF ELECTRICAL ENGINEERING


DIGITAL SYSTEM DESIGN
EE-474

Module No. 01: INTRODUCTION

Engr. Jabbar Younis


Lecturer

Date: October 26, 2020


Course Outlines

• High-level digital design methodology using VHDL/Verilog,


Design, Implementation and Verification, Application
requiring HW implementation, Architectures for Basic
Building Blocks, Adder, Compression Trees and Multipliers,
Transformation for high speed using pipelining, retiming,
and parallel processing, Dedicated Fully Parallel
Architecture, Time shared Architecture, Hardwired State
Machine based Design, Micro Program State Machine based
Design, FPGA-based design and logic synthesis.

Digital System Design EE-474 (Summer 2020) 3


Course Objectives
• Successful completion of the course will enable the students:

• Understand basic concepts to model digital circuits with VERILOG


HDL at the algorithm (behavioral) and data-flow (RTL) levels.
• Analyze various types of architectures through test benches and
perform functional and timing verifications.
• Design combinational and sequential digital circuits by Verilog HDL
using software tools and their mapping on FPGA.

Digital System Design EE-474 (Summer 2020) 4


Course Literature
Main Books:
• “VERILOG HDL”-A guide to digital design and synthesis by Samir Palnitkar, Prentice
Hall Publisher
• Wayne Wolf, “FPGA Based System Design”, PRENTICE HALL, 2004, ISBN: 0-13-
142461-0.

Other Book:
• “Advanced Digital Design with VERILOG HDL” by Michael D. Ciletti, Prentice Hall
Publisher
Examination:
• Written Exam (Midterm= 25 marks, Terminal= 45 marks)
• 02 Assignments , 02 Quizzes
• Labs (Lab reports, Assignments, Project)

The written exam will be based on (i) Lectures (ii) Related book chapters (iii) Tutorials (iv) Any
additional material given

Digital System Design EE-474 (Summer 2020) 5


Lecture 1: Key Points

• Evolution of Computer Aided Design Tools

• Emergence of HDLs

• Typical Design Flow

• Importance of HDLs

• Verilog HDL

• Trends in HDLs

Digital System Design EE-474 (Summer 2020) 6


Design Abstraction Levels in Digital Circuits

SYSTEM

+ MODULE

GATE

CIRCUIT

G
S D DEVICE
n+ n+

Digital System Design EE-474 (Summer 2020) 7


Computer Aided Digital Design

• Early transistors designed using vacuum tubes


• Logic gates placed on single chip to make integrated circuits
• Integrated circuits classified as:
• SSI (Small Scale Integration)
• MSI (Medium Scale Integration)
• LSI (Large Scale Integration)
• VLSI (Very Large Scale Integration)

Digital System Design EE-474 (Summer 2020) 8


Computer Aided Digital Design

• VLSI technology include more than 100,000 transistors on a single


chip
• Verification of these circuits not possible on a breadboard
• Computer-Aided Techniques became critical for verification
• Automatic place and routing of circuit layouts
• Logic simulators for verification of these circuits before fabrication

Digital System Design EE-474 (Summer 2020) 9


Hardware Description Languages

• FORTRAN, Pascal, C used to describe computer programs, sequential


in nature
• Need for standard language to describe digital circuits
• HDLs allow designers to model concurrency
• HDLs
• Verilog HDL
• VHDL

Digital System Design EE-474 (Summer 2020) 10


Hardware Description Languages

• Used for logic verification


• Still manual translation of HDL based design into schematic level
• Logic synthesis tools developed
• Logic synthesis tools implement required functionality in terms of gates
and their interconnections
• HDLs also used for system-level design including
• Simulation of system boards
• Interconnection buses
• FPGAs (Field programmable Gate Arrays)
• PALs (Programmable Array Logic)

Digital System Design EE-474 (Summer 2020) 11


Typical Design Flow

Digital System Design EE-474 (Summer 2020) 12


Advantages of HDLs

• Designs can be described at very abstract level


• Technology independent
• Automatic conversion of design into any fabrication technology by
use of logic synthesis tools
• Functional verification can be done early in the design cycle
• Design cycle time significantly reduced
• HDL is analogous to computer programming
• Textual description easy way to develop and debug circuits

Digital System Design EE-474 (Summer 2020) 13


Verilog HDL

• Standard Hardware Description Language


• Easy to learn and use, similar to C programming
• Allows different levels of abstraction to be mixed in same model
• Most popular synthesis tools support Verilog HDLs
• Verilog libraries provided by all fabrication vendors
• Programmable Language Interface feature

Digital System Design EE-474 (Summer 2020) 14


Trends in HDLs

• Speed and complexity of digital circuits increased rapidly


• Designers describe functionality at higher levels of abstraction
• CAD tools take care of implementation details
• Currently Popular trend is to design in HDL at RTL level
• Logic Synthesis tools create gate level netlist from RTL level design
• Formal verification techniques used to verify correctness of Verilog
HDL descriptions

Digital System Design EE-474 (Summer 2020) 15


References

• VERILOG HDL”-A guide to digital design and synthesis by Samir


Palnitkar, Prentice Hall Publisher

Digital System Design EE-474 (Summer 2020) 16


End of Lecture

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