Digital Systems Modeling at Register-

Transfer-Level (RTL) using Verilog HDL

Lecture 01

Dr. Mehran Goli

Prof. Dr. Rolf Drechsler

University of Bremen, Germany

DFKI Bremen, Germany

mehran@informatik.uni-bremen.de

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Instructors
• Dr. Mehran Goli
– MZH 4202

– mehran@informatik.uni-bremen.de

• Prof. Dr. Rolf Drechsler

– MZH 4330

– drechsler@uni-bremen.de

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Instructors
• Dr. Mehran Goli
– MZH 4202

– mehran@informatik.uni-bremen.de

B.Sc. degree in computer engineering

Hardware-based placement algorithm
from the University of Shahid Beheshti, for reconfigurable hardware on FPGA
Tehran, Iran, in 2012

M.Sc. degree in computer engineering

Assertion-based Verification (ABV)
from the University of Tehran (UT), techniques at the Electronic System Level
Tehran, Iran, in 2015

Ph.D. degree (Dr.-Ing.) in Computer Analyzing SystemC Virtual Prototypes:

Science from University of Bremen, Design understanding, Verification, Security
Germany, in 2019 Validation and Machine learning techniques

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Instructors
• Dr. Mehran Goli
– MZH 4202

– mehran@informatik.uni-bremen.de

• Research Interests

Design understanding and Visualization

Machine Learning for CAD

Verification and Validation

Virtual Prototype Analysis, SystemC

Security Validation

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Course Goals
• Digital systems design using Verilog
• HDL simulation
• Building robust testbenches using SystemVerilog
• Good practices in Digital systems verification using SVA
• Basic static timing analysis and HW optimization
• Importance of synthesis concept

Teach you to be able to think hardware!

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Course Website (Stud.IP)
• What the website will have:
– Lecture notes
– Homework Assignments
– Tutorials
– Course Materials

• Industry-standard design tools

– Modelsim HDL simulation tool (Mentor)
• modelsim-pe_student_edition

– Quartus Prime Lite Edition Design Software (Intel)

– Verilator Open-source Verilog Simulator
– Online Simulator: https://www.edaplayground.com

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Course Materials
• Vaibbhav Taraate - Digital Logic Design Using Verilog Coding
and RTL Synthesis, Springer, 2016

• Zainalabedin Navabi - Verilog Digital System Design, McGraw-

Hill professional engineering Professional Engineering Series, 1999

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Evaluation and Grading
• Oral Examination
– 20-30 minutes
– Including both the lectures and homeworks

• Homeworks considered as bonus (up to 20%)

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Introduction
• Digital systems
– Systems which represent information using a binary system
– Everywhere!

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Introduction
• Digital systems
– Increasingly growing the complexity
– Far complex to be done by hand!

a
Multiplier mult
b

How designers use these tools and

built the desired digital system?

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 Design Flow
Requirements
• High-level Design Flow

Collecting the requirements, estimating the market

value of the end product, and evaluating the
number of resources required.
Specifications

CPUs Memories DSPs

Describing abstractly the functionality, interface and BUS

overall architecture of the system to be designed.

Architecture

Control BUS

Memory1 DSP1 CPU1

System level view of how the design should
operate. How should the data flow inside the Address BUS
chip? What clock frequencies they should run?
Data BUS

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Design Flow
• Levels of Abstraction

• Focus on abstract communication.

• Initial functional model.
• Architecture in form of functional blocks.
Process 1 Process 2
System Level
Memory

• Detailed representation of every

architecture block.
• Information of synchronous or
RT Level
asynchronous designs.

• Gate level netlist after RTL synthesis.

• Functional design in the form of
combinational and sequential logic cells.
Gate Level

• Layout to represent the design in the

form of switches. PMOS, NMOS, and Transistor Level
CMOS.

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 Design Flow HDL Design
always @ (in1, in2);
module M1 (in1, in2, out);
if (in1==in2)
• RTL-based Design Flow
input in1, in2;
output reg out; out = 1’b0;
… else
endmodule out=1’b1;
Testbench end
Module M1_tb ();
reg in1_tb, in2_tb;
wire out_tb; Test and Verification
initial begin
…
end Behavioral Formal
endmodule Validation
Simulation Verification

Waveform Monitor Coverage Correctness

VCD Assertions Assurance
Post-synthesis Analysis

Synthesis and physical Design

Placement Timing
Netlist
Routing Analysis

Fabrication 1.2 ns

1.1 ns

Device Custom
ASIC
Programming Layout

Silicon Wafer Create cells and

Standard Cell layout for all logic

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 Design Flow
• Physical Design

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 Design Flow
• Fabrication

Parameter FPGA ASIC

NRE Low High
Performance Medium High
Time to
Fast Slow
Market
Design Flow Simple Complex
Cost per Unit High Low
Power
High Low
Consumption

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