Microcontrollers and Embedded Systems

IAT-1 Question Bank Solved

1. Differentiate between RISC and CISC.
RISC CISC
• RISC processors have a • In CISC processors, the
reduced number of instructions are often variable
instruction classes which size and take many cycles to
provide simple operations execute.
that can be executed in a • Operations are relatively
single cycle. more complex
• Each instruction has a fixed
length.
• In RISC processors, the • In CISC processors,
processing of instructions is instructions are executed by a
broken down into smaller miniprogram called
units that can be executed in microcode.
parallel using pipelines.
• RISC processors have a large • CISC processors have
general-purpose register set. dedicated registers for
Any register can contain specific purposes.
either data or addresses.
• RISC processors operate on • In CISC processors, the data
data held in registers only. processing operations can act
Separate load and store on memory directly.
instructions are used to
transfer data between the
register bank and external
memory.

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2. Explain the Architecture of an ARM Embedded device with the help of a neat
diagram.

The ARM processor controls the embedded device.

• An ARM processor comprises a core (the execution engine that
processes instructions and manipulates data) plus the surrounding
components that interface it with a bus.
These components can include memory management and caches.
• Controllers coordinate important functional blocks of the system. Two
commonly found controllers are interrupt and memory controllers.
• The peripherals provide all the I/O capability external to the chip.
• A bus is used to communicate between different parts of the device.
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3. Explain in detail about CPSR.

The ARM core uses the Current Program Status Register (CPSR) to monitor
and control internal operations.
The CPSR is a dedicated 32-bit register and resides in the register file.

• The CPSR is divided into four fields, each 8 bits wide: flags, status,
extension, and control.
• The extension and status fields are reserved for future use,
while the control field contains the processor mode, state, and interrupt
mask bits, and
the flags field contains the condition flags
(N-negative, Z-zero, C-carry, V-overflow).

Some ARM processor cores have extra bits allocated. Ex: the J bit, which can be
found in the flags field, is only available on Jazelle-enabled processors, which
execute 8-bit instructions.

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4. With a neat diagram Explain System Hardware.
(Same as Question 2)
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5. What are Core Extensions? Explain in detail all the three extensions for ARM
Core.
(I doubt all three will come in full detail. If they do. Write only few lines for each one)

*Core extensions speed up and organize main memory as well as extend the
instruction set, they are standard components placed next to the ARM core.
They improve performance, manage resources, and provide extra functionality and
are designed to provide flexibility in handling particular applications.

*There are three hardware extensions ARM wraps around the core:-
I) Cache and Tightly coupled memory:-
*The cache is a block of fast memory placed between main memory and the core.
*It allows for more efficient fetches from some memory types.
*With a cache, the processor core can run for the majority of the time without
having to wait for data from slow external memory.
A cache provides an overall increase in performance but at the expense of
predictable
execution.
But for real-time systems it is paramount that code execution is deterministic—
the time taken for loading and storing instructions or data must be predictable.

*This is achieved using a form of memory called tightly coupled memory (TCM).
TCM is fast SRAM located close to the core and guarantees the clock cycles
required to fetch instructions or data—critical for real-time algorithms requiring
deterministic behavior.
*TCMs appear as memory in the address map and can be accessed as fast
memory.

*By combining both technologies, ARM processors can have both improved
performance and predictable real-time response.

II) Memory Management:-

*Memory Management hardware is used to assist organization of multiple memory
devices and protect the system from applications trying to make inappropriate
accesses to hardware.
*ARM cores have three different types of memory management hardware:
*No extensions:-
-Provides no protection
-Non protected memory is fixed and provides very little flexibility.

*A Memory Protection Unit (MPU):-

-Provides limited protection
-MPUs employ a simple system that uses a limited number of memory regions.
These regions are controlled with a set of special coprocessor registers.

*A Memory Management Unit (MMU):-

-Provides full protection
-The MMU uses a full set of translation tables to provide fine-grained control
over memory.
-These tables are stored in main memory and provide a virtual-to-physical
address map as well as access permissions.

III) Coprocessor Interface:

-A coprocessor extends the processing features of a core by extending the
instruction set or by providing configuration registers.
-The coprocessor can be accessed through a group of dedicated ARM instructions
that provide a load-store type interface.

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6. List and detail the various types of Exceptions or Interrupts in ARM.

*When an exception or interrupt occurs, the processor sets the pc to a specific
memory address.
The address is within a special address range called the vector table.

*The entries in the vector table are instructions that branch to specific
routines designed to handle that particular exception or interrupt.

*Each entry contains a form of branch instruction pointing to the start of a specific
routine:-
-Reset vector (RESET): The location of the first instruction executed by the
processor when power is applied. This instruction branches to the initialization
code.

-Undefined instruction vector (UNDEF): It is used when the processor cannot

decode an instruction.

-Software interrupt vector (SWI): It is used to invoke an operating system

routine.

-Prefetch abort vector (PABT): It occurs when the processor attempts to fetch an
instruction from an address without the correct access permissions.

-Data abort vector (DABT): It occurs when an instruction attempts to access data
memory without the correct access permissions.

-Interrupt request vector (IRQ): It is used by external hardware to interrupt the

normal execution flow of the processor. It can only be raised if IRQs are not
masked in the cpsr.

-Fast interrupt request vector (FIQ): It is similar to the interrupt request but is
reserved for hardware requiring faster response times. It can only be raised if
FIQs are not masked in the cpsr.

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7. Explain the 5-stage pipelining used in ARM. Which ARM core implements 5-
stage pipelining.
• A pipeline is a mechanism RISC processors use to execute instructions.
• Using a pipeline speeds up execution by fetching the next instruction
while other instructions are being decoded and executed.
• The ARM9 core implements 5-stage pipelining.

• Fetch: The instruction is fetched from memory.

• Decode: The instruction is decoded and the data path control signals
prepared for the next cycle.
• Execute: The operands are read from the register bank, shifted,
combined in the ALU.
• Memory: Data memory is accessed (Load-Store).
• Write-back: Write back to the register file.

*As the pipeline length increases, the amount of work done at each stage is reduced, which
allows the processor to attain a higher operating frequency.
This in turn increases the performance.
*This also increases system latency

(OPTIONAL)

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8. What are the various processor modes in ARM? Detail each one.
(Repeated in 13.)

The first 5 bits of the cpsr are signified as mode selection bits.
The processor mode determines which registers are active and the access rights to
the cpsr register itself.

Each processor mode is either privileged or non privileged:

*A privileged mode allows full read-write access to the cpsr.
*A non-privileged mode only allows read access to the control field in the cpsr
but still allows read-write access to the condition flags.

*There are seven processor modes in total: six privileged modes (abort, fast
interrupt request, interrupt request, supervisor, system, and undefined) and one
non privileged mode (user):-

Abort: The processor enters abort mode when there is a failed attempt to access
memory.
Fast interrupt request and interrupt request: These modes correspond to the
two interrupt levels available on the ARM processor.

Supervisor: Supervisor mode is the mode that the processor is in after reset and
is generally the mode that an operating system kernel operates in.

Undefined: Undefined mode is used when the processor encounters an instruction

that is undefined.

User: User mode is used for programs and applications.

System: System mode is a special version of user mode that allows full read-write
access to the cpsr.

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9. Explain Banked Registers in ARM?

Out of all 37 registers in ARM, 20 registers are hidden from a program at

different times.

These registers are called banked registers.

-They are available only when the processor is in a particular mode.
-Every processor mode except user mode can change mode by writing directly
to the mode bits of the cpsr.
-All processor modes except system mode have a set of associated banked registers
that are a subset of the main 16 registers.
-A banked register maps one-to-one onto a user mode register. If the processor
mode is changed, a banked register from the new mode will replace an existing
register.
Eg:

*When the processor is in the interrupt request mode, the user registers r13 and
r14 are banked.
The user registers are replaced with registers r13_irq and r14_irq,
respectively.

*A program still has normal access to the other registers r0 to r12.

A new register appears in interrupt request mode: the Saved Program Status
Register (SPSR), which stores the previous mode’s CPSR.

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10. Draw and detail the complete ARM Register set.

(Write the rest if asked for Ten Marks)

Abort: The processor enters abort mode when there is a failed attempt to access
memory.
-Replaces registers r13 and r14

Fast interrupt request and interrupt request: These modes correspond to the
two interrupt levels available on the ARM processor.
-Fast interrupt request Replaces registers r8 to r14
-Interrupt request only replaces registers r13 to r14

Supervisor: Supervisor mode is the mode that the processor is in after reset and
is generally the mode that an operating system kernel operates in.
-Replaces registers r13 and r14

Undefined: Undefined mode is used when the processor encounters an instruction

that is undefined.
-Replaces registers r13 and r14

User: User mode is used for programs and applications.

-Standard operation, allows access to all registers except spsr

System: System mode is a special version of user mode that allows full read-write
access to the cpsr.
-Aswell as access to the spsr

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11. Differentiate between ARM state and Thumb State in ARM Processor technology.

The state of the core determines which instruction set is being executed. There are three instruction
sets: ARM, Thumb, and Jazelle.
*ARM State:-
-When both J and T bits are 0 in the cpsr, the processor is in ARM state and executes 32-bit ARM
instructions.

*Thumb State:-
-When the T bit is 1, then the processor is in Thumb state.
To change states the core executes a specialized branch instruction
-Once in Thumb state the processor is executing purely Thumb 16-bit instructions.

*Jazelle State:-
-The ARM designers introduced a third instruction-set called Jazelle.
Jazelle executes 8-bit instructions and is a hybrid mix of software and hardware designed to speed up
the execution of Java bytecodes.
-It is important to note that the hardware portion of Jazelle only supports a subset of the Java
bytecodes; the rest are emulated in software.

You cannot intermingle sequential ARM, Thumb, and Jazelle instructions

The following table depicts the differences between ARM, Thumb and Jazelle States

(I think sir only wanted this Table, but Im too lazy :0 to remove the top part )

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12. What are the various condition flags available in ARM processors? Detail each
flag.
*Condition flags are updated by comparisons and the result of ALU operations
that specify the S instruction suffix.

*With processor cores that include the DSP extensions, the Q bit indicates if an overflow or
saturation has occurred in an enhanced DSP instruction.
*The flag is “sticky” in the sense that the hardware only sets this flag.`
*To clear the flag you need to write to the cpsr directly.
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13. What do you understand by Privilege and non-privilege modes in ARM?

*Processor mode determines which registers are active and the access rights to the cpsr
register itself.
*Each processor mode is either privileged or nonprivileged:-
-A privileged mode allows full read-write access to the cpsr.
-A nonprivileged mode only allows read access to the control field in the cpsr but still allows
read-write access to the condition flags.
*There are seven processor modes in total:-
-Six privileged modes (abort, fast interrupt request, interrupt request, supervisor, system, and
undefined) and
-One nonprivileged mode(user).
*The processor enters Abort mode when there is a failed attempt to access memory.
*Fast interrupt request and interrupt request modes correspond to the two interrupt levels
available on the ARM processor.
*Supervisor mode is the mode that the processor is in after reset and is generally the mode
that an operating system kernel operates in.
*System mode is a special version of user mode that allows full read-write access to the cpsr.
*Undefined mode is used when the processor encounters an instruction that is undefined or
not supported by the implementation.
*User mode is used for programs and applications.

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14. Explain the use of Barrel Shifters in ARM Processor with suitable examples?

The wide range of second operand shifts available on arithmetic and logical instructions is a
very powerful feature of the ARM instruction set.
We can illustrate this with an example of the use of the inline barrel shifter
Register r1 is first shifted one location to the left to give the value of twice r1.
The ADD instruction then adds the result of the barrel shift operation to register r1.
The final result transferred into register r0 is equal to three times the value stored in register r1.
PRE
r0 = 0x00000000
r1 = 0x00000005
ADD r0, r1, r1, LSL #1
POST
r0 = 0x0000000f
r1 = 0x00000005
We can see that Multiplication can be done, by a Shift and an ADD instruction. Which takes
advantage of the inline barrel shifter to complete the operation in a Single Cycle.
This is more resource efficient than using the expensive MUL operation.

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15. Explain different Arithmetic Instructions in ARM with suitable examples.

The arithmetic instructions implement addition and subtraction of 32-bit signed and unsigned
values.
Syntax: <instruction>{<cond>}{S} Rd, Rn, N

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16. Explain single register Load-Store addressing mode syntax, table, index mode with an
example.
Load-store instructions transfer data between memory and processor registers
Single Register Load-Store instructions are used for moving a single data item in and out of a
register.
The datatypes supported are signed and unsigned words (32-bit), halfwords (16-bit), and bytes.
Syntax:
<LDR|STR>{<cond>}{B} Rd,addressing1
LDR{<cond>}SB|H|SH Rd, addressing2
STR{<cond>}H Rd, addressing2

The ARM instruction set provides different modes for addressing memory.
These modes incorporate one of the indexing methods:
i) Preindex with writeback: calculates an address from a base register plus address offset and
then updates that address base register with the new address.
Useful for traversing a stack/array
ii) Preindex: The preindex offset is the same as the preindex with writeback but does not update
the base register.
Useful for ACCESSING an element in a datastructure
iii) Postindex: Only updates the base register after the address is used.
Useful for traversing an array

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17. Explain the different Logical Instructions in ARM Processor with an example.
Logical instructions perform bitwise logical operations on the two source registers.
Syntax: <instruction>{<cond>}{S} Rd, Rn, N

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18. Write an ALP to find the sum of the first 10 integer numbers.
AREA SUM10, CODE, READONLY

EXPORT __main

__main

ENTRY

MOV R0, #10

MOV R1, #0

LOOP ADD R1, R1, R0

SUBS R0, R0, #1

BNE LOOP

LDR R3, =RESULT

STR R1, [R3]

STOP B STOP

AREA DATA2, DATA, READWRITE

RESULT DCD 0x0

END

Output:-

R0 ← 0x00000000

R1 ← 0x00000037

R3 ← 0x40000000

Memory-

Address: 0x40000000
 37 00 00 00

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19. Write an ALP to find the smallest number from an array of ten 32-bit numbers.

AREA SMALLEST, CODE, READONLY

EXPORT __main
__main
ENTRY
MOV R5, #9
LDR R1, =VALUE1
LDR R2, [R1], #4
LOOP LDR R4, [R1], #4
CMP R4, R2
BLO LOOP1
MOV R2, R4
LOOP1 SUBS R5, R5, #1
CMP R5, #0
BNE LOOP
LDR R9, =RESULT
STR R2,[R9]
STOP B STOP
VALUE1
DCD 0xBBBBBBBB
DCD 0x33333333
DCD 0x44444444
DCD 0x99999999
DCD 0xEEEEEEEE
DCD 0xDDDDDDDD
DCD 0xFFFFFFFF
DCD 0x22222222
DCD 0x66666666
DCD 0x77777777
AREA DATA2, DATA, READWRITE
RESULT DCD 0x0
END
Output:-

R1 ← 0x00000048

R2 ← 0x22222222

R4 ← 0x77777777

R5 ← 0x00000000

R9 ← 0x40000000

Memory-

Address: 0x40000000
 22 22 22 22

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20. Briefly explain what happens when an IRQ and FIQ exception is raised with an ARM
processor.

-The processor mode is changed by a program by hardware when the core responds to an
exception or interrupt
-Exceptions and interrupts suspend the normal execution of sequential instructions and jump to
a specific location.

-The figure shows the core changing from user mode to interrupt request mode, which happens
when an interrupt request occurs due to an external device raising an interrupt to the
processor core.
-This change causes user registers r13 and r14 to be banked. The user registers are replaced
with registers r13_irq and r14_irq, respectively.
-Figure also shows a new register appearing in interrupt request mode:
the saved program status register (spsr), which stores the previous mode’s cpsr.
You can see in the diagram the cpsr being copied into spsr_irq.
-Note that the spsr can only be modified and read in a privileged mode.
There is no spsr available in user mode.

-After the exception is handled, a special return instruction is used that instructs the core to
restore the original cpsr from the spsr_irq and bank-in the user registers r13 and r14.
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21. Explain code optimization, profiling and cycle counting.

Code Optimization
-Embedded software projects often contain a few key subroutines that dominate system
performance. By optimizing these routines you can reduce the system power consumption and
reduce the clock speed needed for real-time operation.
-Code Optimization can turn an infeasible system into a feasible one, or an uncompetitive
system into a competitive one.

Profiliing
-The first stage of any optimization process is to identify the critical routines and measure their
current performance.
A Profiler is a tool that measures the proportion of time or processing cycles spent in each
subroutine. You use a profiler to identify the most critical routines

Cycle Counting
- A Cycle counter measures the number of cycles taken by a specific routine.
You can measure your success by using a cycle counter to benchmark a given subroutine before
and after an optimization.
ARM implementations do not normally contain cycle-counting hardware, so to easily measure
cycle counts you should use an ARM debugger with ARM simulator.

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22. What are SWI instructions? How is it handled?

A software interrupt instruction(SWI) causes a software interrupt exception, which provides a
mechanism for applications to call operating system routines.
Syntax: SWI{<cond>} SWI_number

-When the processor executes an SWI instruction, it sets the program counter PC to the offset
0x8 in the vector table.
-The instruction also forces the processor mode to SVC, which allows an operating system
routine to be called in a privileged mode.
-Each SWI instruction has an associated SWI number, which is used to represent a particular
function call or feature.

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23. Assuming suitable data explain the SWI handler implementation.
Code called the SWI handler is required to process the SWI call.

The code fragment determines what SWI number is being called and places that number into
register r10.
You can see from this example that the load instruction first copies the complete SWI
instruction into register r10.
The BIC instruction masks off the top bits of the instruction, leaving the SWI number. We
assume the SWI has been called from ARM state.

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24. Explain CMN, CMP, TEQ, TST instructions with suitable examples.
-The comparison instructions are used to compare or test a register with a 32-bit value.
They update the cpsr flag bits according to the result, but do not affect other registers.
-After the bits have been set, the information can then be used to change program flow by using
conditional execution
-You do not need to apply the S suffix for comparison instructions to update the flags
Syntax: <instruction>{<cond>} Rn, N

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25. What are the different types of Unconditional Branch Instructions? Detail each one.
-A branch instruction changes the flow of execution or is used to call a routine.
This type of instruction allows programs to have subroutines.
-The change of execution flow forces the program counter pc to point to a new address.
The ARM instruction set includes four different branch instructions.
*Syntax:
B{<cond>} label
BL{<cond>} label
BX{<cond>} Rm
BLX{<cond>} label | Rm

-The address label is stored in the instruction as a signed pc-relative offset and must be within
approximately 32 MB of the branch instruction.
-T refers to the Thumb bit in the cpsr. When instructions set T, the ARM switches to Thumb state

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26. Explain the following instructions: a) LDR Rd, =constant b) ADR Rd, Label

*There is no ARM instruction to move a 32-bit constant into a register.

Since ARM instructions are 32 bits in size, they obviously cannot specify a general 32-bit
constant.
*To aid programming there are two pseudoinstructions to move a 32-bit value into a register
Syntax: LDR Rd, =constant
ADR Rd, label

*LDR Rd, =constant : Writes a 32-bit constant to a register using whatever instructions are
available. It defaults to a memory read if the constant cannot be encoded using other
instructions.
Example:
LDR r0, =0x12345678 ; Load 0x12345678 into r0
LDR r1, =0x100 ; Load 0x100 into r1

*ADR Rd, label: Writes a relative address into a register, which will be encoded using a pc-
relative expression.
Example:
ADR r2, my_label ; Load the address of 'my_label' into r2
.
.
my_label:
DCD 0xDEADBEEF ; Some data at this address

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27. Assuming suitable data explain the working of the instructions:

a) SWP b) SWPB

-The swap instruction is a special case of a load-store instruction.

It swaps the contents of memory with the contents of a register.
-This instruction is an atomic operation—it reads and writes a location in the same bus
operation, preventing any other instruction from reading or writing to that location until it
completes.
Syntax: SWP{B}{<cond>} Rd, Rm, [Rn]

tmp = mem32[Rn]
mem32[Rn] = Rm
Rd = tmp

SWP : swap a word between memory and a register

SWPB: swap a byte between memory and a register

*Example SWP:- *Example SWPB:-

PRE: PRE:
Mem32[0x9000] = 0x12345678
r0 = 0x00000000 Mem8[0x9000] = 0x78
r1 = 0x11112222 r0 = 0x00000000
r2 = 0x00009000 r1 = 0x000000AA
r2 = 0x00009000
SWP r0, r1, [r2]
SWPB r0, r1, [r2]
POST:
mem32[0x9000] = 0x11112222 POST:
r0 = 0x12345678
r1 = 0x11112222 Mem8[0x9000] = 0xAA
r2 = 0x00009000 r0 = 0x00000078
r1 = 0x000000AA
r2 = 0x00009000

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