ARM

ARCHITECTURE

Dr.Kanimozhi.G

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ARM CORE DATA FLOW
MODEL

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CONT…
 A ARM core is a functional units connected by data buses .
 The arrows represent the flow of data

 The lines represent the buses

 The boxes represent either an operation unit or a storage area

 Data enters the processor core through the Data bus.

 Figure shows a VON Neumann implementation of the

ARM processer.

 The instruction decoder translates instructions before they

are executed. Each instruction executed belongs to a particular
instruction set. 3
 Cont…
 The ARM processor, like all RISC processors, uses a
load-store architecture.

 This means it has two instruction types for transferring data in and out of
the processor:
1) load instructions copy data from memory to registers in the core.
2) store instructions copy data from registers to memory.

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 Cont…
 ARM instructions typically have two source registers, Rn and Rm,
and a single result or destination register, Rd.

 Source operands are read from the register file using the internal
buses A and B, respectively.

 The ALU (arithmetic logic unit) or MAC (multiply-

accumulate unit) takes the register values Rn and Rm from the A and B
buses and computes a result.

 One important feature of the ARM is that register Rm alternatively can

be preprocessed in the barrel shifter before it enters the ALU.
 Together the barrel shifter and ALU can calculate a wide range of
expressions and addresses.
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ARM BASED EMBEDDED DEVICE

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 REGISTERS
 General-purpose registers hold either data or an address.

 All the registers are 32 bits in size.

 They are identified with the letter ‘r’ prefixed to the register
number. For example, r4.

 There are up to 18 active registers: 16 data registers (r0 to r15) and

2 processor status registers : cpsr and spsr (the current and saved
program status registers).

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 CONT…
 The ARM processor has three registers (shaded in fig) assigned to a
particular task or special function: r13, r14, and r15.

 Register r13 is traditionally used as the stack pointer (sp) used as a

pointer to active stack.
 Register r14 is called the link register (lr) used to store the return
address from a subroutine.

 Register r15 is the program counter (pc) used to track the address
of the instruction it is about to execute.

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CONT…

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 CPSR(CURRENT PROGRAM
STATUS REGISTER)
 The ARM core uses the cpsr to monitor and control internal
operations.

 The cpsr is a dedicated 32-bit register and resides in the register file.

 The cpsr is divided into four fields, each 8 bits wide:

 flags
 status
 extension
 control.

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 CONT…
 In current designs the extension and status fields are reserved for
future use.

 The control field contains the

` 1)Processor mode
2) State
3) Interrupt mask bits.

 The flags field contains the Condition flags.

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CONT…

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 PROCESSOR MODES
 The processor mode determines which registers are active.

 Each processor mode is either privileged or non- privileged:

 A privileged mode allows full read-write access to the cpsr.
 A non-privileged mode only allows read access.

 There are seven processor modes in total:

 Six privileged modes (abort, fast interrupt request, interrupt request,
system, supervisor and undefined)
 One non-privileged mode (user).

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BANKED REGISTERS

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 37 registers in the register file
 20 registers are hidden and are called banked registers

 Registers are identified only when the processor in a

particular mode.
 Every processor mode except user mode can change mode by
writing directly to the mode bits of cpsr.

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 STATES
 The state of the core determines which instruction set is being
executed. There are three instruction sets:
1) ARM
2) Thumb
3) Jazelle
 The Jazelle J and Thumb T bits in the cpsr reflect the state of the
processor.

 When both J and T bits are 0, the processor is in ARM state and
executes ARM instructions. When the T bit is 1, then the
processor is in Thumb state.
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 Cont…
 The ARM designers introduced a third instruction set called
Jazelle.

 Jazelle executes 8-bit instructions and is a hybrid mix of software and

hardware designed to speed up the execution of Java byte
codes.

 To execute Java byte codes, Jazelle technology plus a specially

modified version of the Java virtual machine is required.

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 INTERRUPT MASK
 Interrupt masks are used to stop specific interrupt requests from
interrupting the processor.
 There are two interrupt request levels available on the arm processor
core
 Interrupt request (irq)

 Fast interrupt request (fiq).

 The cpsr has two interrupt mask bits, 7 and 6 (or i and f), which control
the masking of irq and fiq, respectively.
 The i bit masks irq when set to binary 1, and similarly the f bit
masks fiq when set to binary 1.
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CONDITION FLAGS

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 PIPELINING

 A pipeline is the mechanism a RISC processor uses to execute

instructions.
 Pipeline speeds up execution by fetching the next instruction
while other instructions are being decoded and executed.
 ARM7 Three-stage pipeline.

Fetch Decode Execute

Fetch loads an instruction from memory.

Decode identifies the instruction to be executed.
Execute processes the instruction and writes the
result back to a register.
 Fetch Decode Execute

Cycle 1 ADD

Time Cycle 2 SUB ADD

Cycle 3 CMP SUB ADD

 5-stage pipeline
• Stages:

Fetch

Decode

Execute

Buffer/data

Write-back
 ARM9TDMI

Instruction ARM or Thumb

Inst Decode Reg
Fetch Shift + ALU Memory
Reg Reg Write
Decode Read Access

FETCH DECODE EXECUTE MEMORY WRITE

•In ARM9TDMI the execute stage has been split out into three
stages to allow greater throughput. The operating frequency is
approximately double for ARM9TDMI over ARM7TDMI on
the same fabrication process. Therefore, at least double the
processing power is available.
 Memory and IO
• The Memory and IO (MEM) stage is responsible for storing
and loading values to and from memory. It also responsible for
input or output from the processor.
• If the current instruction is not of Memory or IO type than the
result from the ALU is passed through to the write back stage.

Write Back(WB)

• The Write Back (WB) stage is responsible for writing the

result of a calculation, memory access or input into the register
file.
ARM7, ARM9 AND ARM 10 PIPELINING

Fig 1: ARM7 three-stage pipeline

Fig 2: ARM9 five-stage pipeline

13% more throughput than the ARM 7 processor

Fig 3: ARM10 six-stage pipeline

34% more throughput than ARM 7 processor
 ARM10 & ARM11 Pipelines
ARM10
Branch ARM or Memory
Prediction Thumb Reg Read Shift + ALU Access Reg
Instruction Instruction Multiply Write
Fetch Decode Multiply Add
FETCH ISSUE DECODE EXECUTE MEMORY WRITE

ARM11
Shift ALU Saturate

Fetch Fetch MAC MAC MAC Write

Decode Issue
1 2 1 2 3 back
Data Data
AddressCache Cache
1 2
Types of Pipelining
• Software Pipelining
1) Can Handle Complex Instructions
2) Allows programs to be reused
• Hardware Pipelining
1) Help designer manage complexity – a complex task
can be divided into smaller, more manageable pieces.
2) Hardware pipelining offers higher performance
 Type of Hardware Pipelines
 Instruction Pipeline - An instruction pipeline is very similar
to a manufacturing assembly line.

• 1st stage receives some parts, performs its assembly task, and
passes the results to the second stage;
• 2nd stage takes the partially assembled product from the first
stage, performs its task, and passes its work to the third stage;
• 3rd stage does its work, passing the results to the last stage,
which completes the task and outputs its results.

 Data Pipeline – data pipeline is designed to pass data from

stage to stage.
 Advantages/Disadvantages

Advantages:
• More efficient use of processor
• Quicker time of execution of large number of
instructions

Disadvantages:
• Pipelining involves adding hardware to the chip
• Inability to continuously run the pipeline
at full speed because of pipeline hazards
which disrupt the smooth execution of the
pipeline.