Alfaisal University

College of Engineering
Department of Software and Electrical Engineering

EE 210/SE223
Digital Design

Chapter 4
Combinational Logic

1
 Outline
• Half adders
• Full adders
• Binary Decoders
• Binary Multiplexers

Design and build simple

combinational and sequential
circuits based on different types of
logic gates, flip-flops and latches.

Outcome 3 2
 Logic Circuits
• There are two types of logic circuits for digital
systems: combinational and sequential.
• Combinational circuits consist of logic gates whose
outputs at any time are determined from only the
present combination of inputs.
– They can be specified logically by a set of Boolean
functions.
• Sequential circuits contain storage elements in
addition to logic gates.
– Their outputs are a function of the inputs and the state of
the storage elements.
– The outputs depend not only on present values of inputs,
but also on past inputs.

3
 Combinational Circuit
• A combinational circuit consists of input
variables, logic gates, and output variables.
• For n input variables, there are 2n possible
binary input combinations.

(From Mano & Ciletti)

4
 Combinational Circuit (cont.)
• For each possible input combination, there is one
possible output value.
• It can be specified with a truth table with n inputs
and m outputs.
• Also, it can be described by m Boolean functions
expressed in terms of n input variables.

(From Mano & Ciletti)

5
 Combinational Circuit Analysis
• Analysis is to determine the function of a
given circuit
• It starts with a given logic diagram and ends
with:
– a set of Boolean functions,
– a truth table,
– or, possibly, an explanation of the circuit
operation.
• It is the opposite way of design process

6
 Combinational Circuit Analysis (cont.)

• The 1st step is to make sure that the given circuit is

combinational and not sequential, meaning:
– There is no memory element in the circuit
– The circuit should not contain feedback paths
• A feedback path is a connection from the output of
one gate to the input of a second gate that forms
part of the input to the first gate.

7
 Analysis Procedure
• To obtain the output Boolean functions:
– Label all nodes with arbitrary symbols.
– Starting from the outputs and using
Boolean algebra to determine the Boolean
functions for the circuit outputs.

8
 Analysis Procedure (example)
• Obtain Boolean functions:
Fi = Tz +Ta

Tz = A B
. . C .

Ts E To
= :

Ti =
A + R+ C .

TH
fc = Th +Ts + To ,

Ty
i
Th I
(From Mano & Ciletti)
I
9
 Analysis Procedure
• To obtain the truth table directly from
the circuit:
– Determine the # of circuit inputs, n à
the truth table has 2n rows
– Starting from inputs, obtain the truth
table of the required nodes until the
truth table of the circuit outputs are
found.

10
 Analysis Procedure (Truth Table)
↑

# A B C F2 F’2 T1 T2 T3 F1
0 0 0 0 O O

1 0 0 1
2 0 1 0 " 8 Ty

T5
3 0 1 1
4 1 0 0
5 1 0 1
i 8
8
To
(From Mano & Ciletti)

i
6 1 1 0
7 1 1 1 I

11
 Design Procedure
It starts from the specification to obtain a logic circuit
diagram or a set of Boolean functions:
1. Determine the required # of inputs and outputs and
assign a symbol to each.
2. Derive the truth table that defines the required
relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each
output as a function of the input variables.
4. Draw the logic diagram and verify the correctness
of the design (manually or by simulation).

12
 Design Procedure (Example)
Input Output
BCD code Excess-3 code
BCD to Excess-3 Code A B C D w x y z
conversion: 0 0 0 0 O O ↓ I
1. Has n=4 inputs (ABCD) and 0 0 0 1 01 00
m=4 outputs (wxyz) 0 0 1 0 o 101
2. Truth table à 0 0 1 1 o I 10
0 1 0 0 0 1 1 I
0 1 0 1 I 00 0
0 1 1 0 10 o
0 1 1 1 1010
1 0 0 0 I o 1 1
1 0 0 1 1100
13
 BCD to Excess-3 Code Conversion
3. Simplified Boolean functions: all outputs have don’t care
conditions ! ", $, %, & = Σ 10,11,12,13,14,15,16 X
0 ", $, %, & = Σ 0,2,4,6,8 y ", $, %, & = Σ 0,3,4,7,8
C C
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 I I 00 I I
01 I I 01 I I
B B
11 X X X X 11 X X X X
A A
10 ↓ X X 10 1 X X

D D
&

D in' + <D

14
 BCD to Excess-3 Code Conversion (cont.)
w ", $, %, & = Σ 5,6,7,8,9 x ", $, %, & = Σ 1,2,3,4,9
C C
CD CD
00 01 11 10 AB 00 01 11 10
AB
00 00 I I I

01 11 1 01 I
B B
X 11 X X X X
11 X X X A
A
10 11 X X 10 A X X

D D

A + BD + BC BID' -D + BC .

15
 BCD to Excess-3 Code Conversion (cont.)
• A two-level AND-OR logic diagram may be obtained
directly from the Boolean expressions
– z=D'
– y = CD + C'D'
– x = B'C + B'D + BC'D'
– w = A + BC + BD
• 7 AND gates with 2x6 + 3 = 15 inputs
• 3 OR gates with 2 + 3 + 3 = 8 inputs
• Total cost: 10 (# of gates) + 23 (gate inputs) = 33

16
 BCD to Excess-3 Code Conversion (cont.)

• The expressions may be manipulated

algebraically for the purpose of using
common gates for two or more outputs.
–z=D'
–y = CD + C'D' = CD + (C+D)'
–x = B'C + B'D + BC'D' = B'(C+D) + BC'D' =
B'(C+D) + B(C+D)'
–w = A + BC + BD = A + B(C+D)

17
 BCD to Excess-3 Code Conversion (cont.)

z=D'
y=CD + (C+D)'
x=B'(C+D) + B(C+D)'
w=A + B(C+D)
• It results in
multiple-level
implementation
(From Mano & Ciletti)
• Assume that B’ and D’ are available:
• 4 AND gates, 4 OR gates and 1 NOT are required.
• What is the cost?
18
 Half Adder (Implementations)
(a) Two-level with AND-OR
(b) Using an XOR gate

(From Mano & Ciletti)

20
 Full Adder (FA)
• A full adder is a combinational circuit that adds
three input bits.
• It consists of n=3 inputs (x, y and z) and m=2
outputs (C and S).
x y z C S
0 0 0 00
I
0 0 1
↑ I

a
O
↓ I I I f
0 1 0 O

0 1 1 10
1 0 0 OI
1 0 1 10
1 1 0 10 C S
1 1 1 1D
NY xyz
yz +
'yz x'yz
nz +
a + +
21
+ ayz .
 Full Adder (2-level Implenentation)
n (y0z)
C = xy + xz + yz S = x'y’z + x'yz’ + xy'z’ + xyz

(From Mano & Ciletti)

22
ayz + x yz + xyz +
xyz
yz)
ric + + x(yz yz) +

y #Z (y(z)
= ((y0z)

- xyz .
 Full Adder (Multi-Level Implenentation)
• Implementation using 2 HA and an OR gate
↑

(From Mano & Ciletti)

• Prove:
=x'y'z+x'yz'+xy'z'+xyz

=xy+xz+yz

23
 Binary Adder
• A binary adder is a digital circuit that produces the
arithmetic sum of two binary numbers
• It adds two n-bit binary numbers A=(An-1…A1A0)2 and
B=(Bn-1…B1B0)2 using n FAs
– In a FA: x=Ai , y=Bi , z=Ci , S=Si , C=Ci+1 , 0≤ i ≤n-1
• e.g.: Adding A=1011, B=0011 à C4=0, S=1110
0 1 0 0 1 1 1 1

0 0 1 1

1 1 1 0

(From Mano & Ciletti) 24

 4 C3 G2 2 Co

#
A As Ar A, .
A
 A Bo As

Hill
,

1) IIIIII

-14bitAir-T-
bit Addr

111 111
S
 Binary Adder (cont.)
• Assume that FAs are implemented in 2 levels, what is the # of
gate levels of an n-bit adder?
• The total propagation time is equal to the propagation delay
of a typical gate times the number of gate levels in the circuit.

(From Mano & Ciletti)

• The longest propagation delay time in an adder is the time it

takes the carry to propagate through the FAs.
• It limits the speed of the adder.
25
 How to Design a Fast Adder?

• Let us define !! = #! ⊕ %! and )! = #! %! signals as

the outputs of the first HA of the ith FA
• Then, *!"# = )! + !! *! and ,! = !! ⊕ *! , 0 ≤ i ≤ n-1

Pili

(From Mano & Ciletti)

• To reduce the carry propagation time in the adder, a
carry lookahead generator is used

26
 Carry Lookahead Generator

• We derive the Boolean function for Ci+1 as a function

of only C0 (not Ci) and other signals
• %!"# = 8! + :! %! (i=0) à ;$ = <% + =% ;%
• i=1 à C2=G1+P1C1=G1+P1(G0+P0C0)=G1+P1G0+P1P0C0
• i=2 à C3=G2+P2C2=G2+P2(G1+P1G0+P1P0C0)
=G2+P2G1+P2P1G0+P2P1P0C0
• The three carry functions are expressed in SOP.
• Then, we can implement them in 2-level AND-OR
implementation
This makes O(n) delay into OC1) .

27
 Carry Lookahead Generator
• C3=G2+P2G1+P2P1G0+P2P1P0C0
• C2=G1+P1G0+P1P0C0
• C1=G0+P0C0

(From Mano & Ciletti)

28
 Binary Adder using Carry Lookahead

• Recall: !! = #! ⊕ %! , )! = #! %! , and ,! = !! ⊕ *!
• How many levels does it have?
• The propagation
delay is independent
of n (the # of bits)

29
(From Mano & Ciletti)
 Unsigned Binary Subtractor
• The subtraction of unsigned binary numbers can be
done by means of complements
• Recall: the subtraction A - B can be done by adding A
to the 2's complement of B:
– 2's comp. of B = 1's comp. of B+1 = (B’n-1…B’1B’0)+(0…01)2
• A≥BàA-B=S
• A < B à 2’s comp. of (B - A)

30
 Co .

AzA ,
Ao
BzB ,
Bo
-

23 Bo to
B, Al
&

BeAz
Il
Il
Il Co

Fanta
IJ
J fr
-

ad Is I
Isn ,
So
A B
- = A + ( B)
-

t Il
Il
IJ
Fan tJ fAg
-

=
Co

I
ad I S2 Is ,
I So
 Signed Binary Subtractor
• Let A and B be signed #s represented in the signed
2’s complement number system.
• The output of previous circuit (S) generates A-B if
there is no overflow (V=0)
– If V=1à there is an overflow

- 1

• So, this circuit can also be used for unsigned

subtraction
31
 Adder-Subtractor
If M=0 (Adder)
=0
$! ⊕ 0 = $! à S=A+B
B3 B2 B1

-
B0

If M=1 (Subtractor) =1

$! ⊕ 1 = $!& à S=A-B B’3 B’2 B’1 B’0

(From Mano & Ciletti) 32

 minterm
Decoder
-

generat
-

zu ,

• A decoder is a combinational circuit that

converts binary information from n input lines
to m ≤ 2n unique output lines.
• In active-high outputs, each output is a
minterm. Example: 3-to-8 line decoder

33
 Decoders
• A n-to-2n line decoder is a circuit that selects
one of the 2n output lines depending on the
combination of n inputs

Each O
Output 0
Combination Input 0 2-4 Output 1
selects one Input 1 decoder Output 2
Output 3
output

A 2-to-4 decoder is usually referred to as a 2X4 decoder

34
 Example of 2-to-4 Active Low Decoder

Ai
1
0 A
1
0 B I
1

peein
AB
0

- ABI

AB
0

35
 Decoder (3x8 decoder)
• It can be used for binary-to-octal conversion
• Each output is a minterm
for a 3-variable function.

(From Mano & Ciletti)

36
 Decoder with Enable
• Design a 2-to-4 decoder with the following truth
table

&
– Active-low outputs
– Active-low enable (E)

In this case
,
the Decoder becomes

maxterm
a
-
- generator .

(From Mano & Ciletti)

37
 Decoder with Enable (cont.)
• Decoders with enable inputs can be connected to
form a larger decoder circuit.
• An example: To form a 4x16 decoder
w x y z D0 D1 … D7 D8 D9 … D15

on high!
↑ snable

(From Mano & Ciletti)

38
 I
24

D
-

000

I
Z

E
o

o10 2
G

106
10
11

Y
-&
2to 4
E
--
.

110
I
11
F = 2( , 3 5 7) , ,
 Combinational Logic Implementation using
Decoders
• A decoder with active-high outputs provides the 2n
minterms of n inputs.
• Example: Implementing a FA using a decoder with
active-high outputs.

-
10 I
(From Mano & Ciletti)
39
 Using a Decoder to Implement Any Function
-
-

• Since each AND gate in the decoder (active

HIGH) represents a minterm we can OR any
combination of minterms to realize any
Boolean function
A B
A
B
A B

A B

A B
1
E 40
Example
Truth Table A B X
0 0 1 AB
0 1 0
1 0 0
1 1 1 AB

A B
A
B
A B
X
A B

A B
1 41
E
 Full adder circuit
• Let’s say we want to design a circuit that adds two
binary digits plus a carry in digit

111 0 1 1
Y X

011
C Full adder Z 001

1 01
S 42
Full adder truth table

X Y Z S C

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

43
 Implementing a full adder using a decoder

0
1
S
X 2
Y 3
Z 3-to-8
decoder 4
5
C
6
7

Note: when more than 2n/2/2 minterms are 1, use F’

minterms and a NOR gate instead of OR gate. 44
 Example: Decoder
• Using a decoder and external gates, design the combinational
circuit defined by:
F1=(y’+x)z, F2=y’z’+xy’+yz’, F3=(x’+y)z

fi =
yz + xz.
=
[(1 ,
5
, 7) .

·
a

45
 =
E(0 ,
2
,
4 5
, ,
6) .

I
yz
800
60 1 &
G 10 I

o 11 O

n
↓ 00

I
10

110 A

Il & O
I
xz +
yz
.

= x(y y'z +

+ (x + a)yt

= x'y z+ x" y'z

+ x yz + nyz

= a 'yz + n'y'z
+ xyt

= [(3 1
1
, 7)
 = xz + yz .

I
xyz

real
-

00
oo D

610
C D
OI
lop
10
110
D
11
 3
-

=
·
2

~
Fi

#
 Exercise

• Use 2-to-4 decoders to implement the

following function: F = S(1, 3, 5, 7)
Hint : How inputs does
many f has
a
and what type of decoder is

needed ?

46
 7-Segment Display
• A 7-segment display is used for displaying any one
of the decimal digits 0 through 9.
• It contains the 7 LED (Light-Emitting Diode)
segments on top of the package controlled by
inputs a, b, c, d, e, f, and g. Vcc=+5v
• The common anode (CA) for all
the LEDs (pin 14) should be
connected to Vcc through a
resistor in order to supply the
proper current to the selected
LED segments. 3052

47
 7-Segment Display (cont.)

• Then, sending a 0 (LOW) signal to the inputs a to g of

the display will turn the corresponding segment on.
– For example: in order to display a small o (shown below),
the inputs should be: Vcc=+5v
– a=b=f=1
– c=d=e=g=0
g

3052

48
 A BCD-to-seven-segment Decoder
• A BCD-to-7-segment decoder (7447) is a combinational circuit
that accepts a decimal digit in BCD (A3A2A1A0) and generates
the corresponding 7-segment code (a to g).
• .

A0
O
BCD A1
input A2
A3
3052

7447 49
i
ABCD f [l/ , 4 3
, , 7)
500 0

As

i
000
0010 of o 11
O O
1 /

0160

010
o 11 O

I o
oo I
I

B + AB'D
i
1016
o 11
CD +
I
1100
1101
1110
111/
[(1 , 2, 3
,
7) a
-

2
-
2

2
-

i 2
-

- -

- -

4 X16
-

-
OR

Decoder q-

10-
-

4 -

12 -

i
-

Note :
For this
function
, you ca also wo

a 3x8 decoder
 Encoder
• An encoder is a digital circuit that performs the
inverse operation of a decoder.
• An encoder has 2n (or fewer) inputs and n outputs.
– The output generates the binary code corresponding to the
input value.

50
 Encoder (cont.)
• This encoder can be implemented with three 4-input
OR gates.
• It has two limitations:
– Only one input can be active at any given time. If D3 and D6
are 1 simultaneously àWhat are xyz=?
– All 0 outputs are generated if all Dis are zero.
•So, an additional output is required to distinguish it from D0=1

51
 Priority Encoder
• A priority encoder is an encoder circuit that includes
the priority function.
• If two or more inputs are equal to 1 at the same
time, the input code having the highest priority will
be generated.
– Determine the highest and lowest priority inputs.

52
 Priority Encoder (cont.)

D2 D2
D2 D3 D2 D3
D0 D1 00 01 11 10 00 01 11 10
D0 D1
00 00
01 01
D1 D1
11 11
D0 D0
10 10
D3 D3

53
 Priority Encoder (cont.)
• y = D3 + D1D’2
• x = D2 + D3
• V = Do + D1 + D2 + D3

(From Mano & Ciletti)

54
 Multiplexer (MUX)
• A multiplexer is a combinational I0
circuit that selects binary I1 0...00
0…01
information from one of 2 inputs
n : Y
lines (Ij’s 0≤j≤2n-1) and directs it I2n-1 1…11
21
to a single output line (Y). 2n-1
…
Sn-1 S1S0
• The selection of a particular input line
is controlled by a set of n selection Sn-1…S1S0 Y
lines (Sn-1…S1S0).
0 … 0 0 I0
• The MUX acts like an electronic switch 0 … 0 1 I1
that selects one of 2n inputs :
1 … 1 1 I2n-1

55
 Operation of a multiplexer

1 0
0 0

S1 S0
1 0 0 1 0
1 4-to-1
1 0 0 1 2 Mux
3

56
 Multiplexer (example)
• Example: A 2-to-1 (2x1) MUX (n=1)
S Y
Y = I0S’ + I1S
0 I0
1 I1
Truth (Function) table

Block diagram

(From Mano & Ciletti) 57

 Example: A 4-to-1 (4 x 1) MUX
I0
00
I1 01
I2 10 Y
I3 11
20
21

S1 S0
Block diagram

Isis + I SiSo + ISS. Logic diagram

- IS ,So (From Mano & Ciletti)

58
 Example
• Using only 2-to-1 multiplexers to build a 4-to-1
multiplexer

Io E
Es.
Il
soh
-
E Si

So
(From Mano & Ciletti)

59
 Example – Multiplexer Expansion
Create an 8x1 multiplexer using two 4x1
multiplexers and a minimum number of
S2SiS
logic gates.
I

i
-

000 O

D
001
· 10 In

110 Et
I

, So
S 60
 Building an 8 X1 MUX

I2 from 2x1 Muxs.

·
Iss

E#
#
Fis
Ko
 Boolean Function Implementation with MUXs
• A Boolean function with n variables can be easily
implemented with a 2nx1 MUX.
• Design F(x, y, z) = S(1, 3, 5, 6) with an 8x1 MUX (n=3)
x y z F
0 0 0 S Z
Y
0 0 1 I e

0 1 0 6

·
0 1 1 I

1 0 0
1 0 1
1 1 0
1 1 1
i
61
- ·
-

F
116
11/
so Y .

-
 Boolean … with MUXs (cont.)
• A more efficient method is to use a 2n-1x1 MUX:
– The first n-1 variables are connected to the selection inputs.
– Let the remaining variable be z. Then, each input of MUX will be either
0, 1, z or z’ based on the function.
• Design F(x, y, z) = S(1, 3, 5, 6) with a 4x1 MUX (n=3)

x y z F
0 0 0 O Y
I
0 0 1 I
0 1 0 O Z
0 1 1 I Z
1 0 0 O Z
1 0 1 I z
1 1 0
1 1 1 ↓

62
 Boolean … with MUXs (cont.)
• Design F(x, y, z) = S(1, 3, 5, 6) with a 2x1 MUX
z z
x y z F y 0 1
I
0 0 0 O 0
0 0 1 I Z y 1
0 1 0 O I0= F(0,y,z)
0 1 1 I I1= F(1,y,z) F(x,y,z)
1 0 0
1 0 1
1 1 0
1 1 1
i yz' + yz x

y
z
0
z
1
0 f
I
y 1

63
·
o 11

158
101

R
 F

-
2yz

001

o 11

158
101
110
111
so
t
C
 Using a multiplexer to realize NAND gates

A B F A
0 0 1
0 1 1
1 0 1 1 0 2x1
F
1 1 0 B 1 Mux

64
 Using a multiplexer to realize XOR gates

A B F A
0 0 0
0 1 1
1 0 1 B 0 2x1
F
1 1 0 1 Mux

65
 Example
• Implement the function F(A,B,C)=A’C’+AB+AC using
(a) a 2-to-1 multiplexer
(b) a 4-to-1 multiplexer
I I
C Cl 00
01
B +C I 10
11
20

A
21

A B .

66
 Using a multiplexer to implement a function
• Ex: use a 4×1 multiplexer to implement the function
F(x,y,z) = S(0,2,4,7)

X Y Z F
Y S0
0 0 0 1 F=Z X S1
0 0 1 0
Z F
0 1 0 1 0 4X1 Mux
F=Z
0 1 1 0 1
2
1 0 0 1
F=Z 3
1 0 1 0
1 1 0 0
F=Z
1 1 1 1 67
 Another example using a multiplexer
• Implement using a 4×1 multiplexer the function
F(x,y,z) = S(3,4,6,7)

X Y Z F
0 0 0 0 Y S0
F=0 X S1
0 0 1 0
Z F
0 1 0 0
F=Z 0 0 4X1 Mux
0 1 1 1 1
1 0 0 1 2
F=Z 1 3
1 0 1 0
1 1 0 1
F=1
1 1 1 1 68
 Example: multiplexer
• Implement F(A,B,C,D) = S(1,2,4,7,8,9,10,11,13,15) with a 4x1 MUX and
external gates. Connect A and B to the selection lines.

↑
o
6101

i B .

69
 Exercise

• Use 4x1 multiplexer to implement the

following function:
F(x,y,z) = S(1, 3, 5, 6)

70
 MUX (cont.)

• Some MUXs provide multiple-bit selection with

common selection inputs.
• Some MUXs have an enable signal. The enable signal
must be active for normal operation.
• Example: A quadruple 2x1 MUX
E (Active-low enable)

4
A 4
4 Y
B
1
S
71
Edabml E
A Quadruple 2x1 MUX

4
A 4
4 Y
B
1
S

(From Mano & Ciletti)

72
 Three-state Gates
• A 3-state gate has an additional control input to
generate 3 states at its output: {0,1,Z}
A0
A1 Output Y=f(A0,A1, … ,An-1) if C=1 (Active-high)
An-1
High-impedance Y=“Z” if C=0
Control input C
• When the control input is active, the gate output is
enabled based on the type of the gate.
– The 2 conventional states of 0 and 1 appear at the gate
output.
• The 3rd state is a high impedance (Z) state when the
control input is not active
– The gate output behaves like an open circuit
• A 3-state buffer:

73
(From Mano & Ciletti)
 Three-state Gates (cont.)
• The outputs of three-state gates can be connected
(not in regular gates) if the control input of at most
one gate is active at any time.
• A MUX can be constructed with 3-state gates:

74
(From Mano & Ciletti)
A Quadruple 2x1 MUX with 3-state outputs
(74257)
• In this IC (used in lab 2), the control (or output
enable) signal is active low

75
 I 11
I 11

(19) 10 000 ↓ 1801

11
(23) ,
oo
0010
+
0

- 1100
4 2 000 0 0110

-
O I O O 0010

4 2
 Y
Y
/
Xo Yo
1111
III IIII (III

·
,
&
J
I BLDAdir -

17-c BCD Addr .

111/

is So
 BCD Adder
• A BCD adder is a combinational circuit that adds two
decimal numbers X and Y, 0≤X,Y≤9, with a “Carry in”
and generates the decimal sum S, 0≤S≤9, with an
Output carry C.
• How many inputs and outputs does it have?
• A systematic design:
– 5 functions of 9 variables
X Y

C=Output carry
BCD Adder Carry in

S 76
 BCD Adder (cont.)
• We want to use binary adders and an additional logic
circuit to implement it.
• First, add X and Y using a 4-bit binary adder.
• What are the range of 5-bit outputs?
X Y
0≤X≤9
0≤Y≤9
Carry out = K
+ 0≤Carry in≤1 4-bit binary adder Carry in
Z8Z4Z2Z1
0≤X+Y+Carry in≤19
Z
à The binary addition of “X+Y+carry in” is
represented by: KZ8Z4Z2Z1
77
 BCD Adder--Addition Rules
• If the result of binary addition ≥ 10
– The Output carry C=1. It will be added to the next decimal
digits
– In order to get a BCD code at S, it should be added with 6:
S8S4S2S1= Z8Z4Z2Z1+0110
• Otherwise, the result of Z are in the BCD format
– Output carry=C=0
– S8S4S2S1= Z8Z4Z2Z1+0000
• The above two cases can be combined as
– S8S4S2S1= Z8Z4Z2Z1+0CC0
• It can be implemented with another 4-bit adder and
a combinational logic that generates C

78
 BCD Adder (cont.)
• To Design C (the
K Z8Z4Z2Z1
combinational logic ≥10):
C(K,Z8,Z4,Z2,Z1)
=∑(10,11,12,…,18,19)+d(20, 21,…,31) ≥10

C
Z2 Z2
Z2 Z1 Z2 Z1 0 0 Z8Z4Z2Z1
Z8Z4 00 01 11 10 Z8Z4 00 01 11 10
00 O · >2 00 he he ha de
01 U
5
b 01 No th 23
+ Xi
7
Z4 Z4
Z8
11 in he is li Z8
11 ↓ X30 4-bit binary adder 0
10 8 a Il ko 10 ↓ ti t bo
Z1 Z1
K=0 K=1 S
E2
+ to .
zo Eu · + R 79
 BCD Adder (cont.)
• Combining all designs: X Y

of

Suraniche
Result
T k-map g
OCCO to 24 EL zv

C
(From Mano & Ciletti) 80
 Binary Multiplier
• An n-bit by m-bit binary multiplier is a combinational
circuit that multiplies two binary numbers and
generates an m+n-bit product
• Example: a 2x2 multiplier

A.B ArBo

Ad
ansAct
AiBit
O
81
(From Mano & Ciletti)
 Binary Multiplier (cont.)
• Example: Design a multiplier of (A2A1A0)x(B3B2B1B0)=
(C6C5C4C3C2C1C0)
B3 B2 B1 B0
A2 A1 A0
#Br
ArBi ABO
ABAR :
Also

82
(From Mano & Ciletti)
 Magnitude Comparator
• A magnitude comparator is a combinational circuit
that compares two numbers, A and B, and
determines their relative magnitudes.
• The outcome of the comparison is specified by three
binary variables (G, E, L) that indicate whether:
(A > B), (A = B), or (A < B)
• It requires a truth table with 2n inputs
A A>B G
n
A=B E
B A<B L
n

83
-
E
11

=
(AGB) "
8

=
O

AB'
,
<= A .
-
⑳

Go 10

00 1 (

G1G o

01o

61 16

o I I(

i
8 00

O 01

-10

o 1 (

IG o

I o

I 16 O

I 11
A
 Magnitude Comparator (cont.)
• Example: Using K-maps, design a magnitude
comparator to 2-bit numbers (n=2)
A=B B1 A>B B1 A<B B1
B1B0 B1B0 B1B0
A1A0 00 01 11 10 A1A0 00 01 11 10 A1A0 00 01 11 10
00 1000 00 0000 00 0 1 1 I

01 Of O O
01 100 0
01 0 0 1 1
A0 A0 A0
11 E G 10 11 1 01 11 G 000
A1 A1 A1
10 00 01 10 110 o
10 G 010

B0 B0 B0

84
 Magnitude Comparator (cont.)
• It becomes hard with n > 2 if a truth table is used
• Let us define a variable xi which is 1 if the pair of bits
in position i are equal, i.e., Ai=Bi
• To obtain E (A=B) à (A3A2A1A0)=(B3B2B1B0)
– A3=B3 and A2=B2 and A1=B1 and A0=B0
Ai Bi xi
0 0
D
(D- 3

S
I
I

T
-

XNOR
0 1 O

-S
S
O
1 0
f
1 1
---

85
 Magnitude Comparator (cont.)
0010 1011
• Let us define another variables gi which becomes 1 if
Ai>Bi
• To obtain G (A>B)à (A3A2A1A0)>(B3B2B1B0)
– A3>B3 or (A3=B3&A2>B2) or (A3=B3&A2=B2&A1>B1) or
(A3=B3&A2=B2&A1=B1&A0>B0)
2

Ai Bi gi T

0 0 O

0 1 O

1 0 I
1 1 ①

86
AXP
AsAzA Ao ,
< By Bz B i
Bo
,

By an Ar < B2)
(As < Bs) or (An =

AiB , <

·
-

AB .
 Magnitude Comparator (cont.)
To obtain L (A<B)à
AB CAA s
(A3A2A1A0)<(B3B2B1B0) ABC
– Swapping all Ais and
Bis from the function
G
AzBa
• It results in multi-
level implementation
Air,

AoB !

(From Mano & Ciletti) 87

Alfaisal University
College of Engineering
Department of Software and Electrical Engineering

EE 210/SE223
Digital Design

Chapter 4
Combinational Logic

1
 Exercise

• Use 2-to-4 decoder to implement the

following function: F = S(1, 3, 5, 7)
This solution
requires building a
3x8 decoder from a
2x4 decoder set
with external gate
usage.

2
 A 0
1
2-to-4 2
B Decoder 3

F
E

4
5
2-to-4 6
Decoder 7

3
 Exercise

• Use 4x1 multiplexer to implement the

following function:
F(x,y,z) = S(1, 3, 5, 6)

4
 x y z F
(S0) (S1) (S2)
0 0 0 0
S0
I0 = z
0 0 1 1 S1
------------------------------------ S2 = z
0 1 0 0
I1 = z 4x1 F
0 1 1 1 I0 MUX
------------------------------------
I1
1 0 0 0
I2
I2 = z
1 0 1 1
------------------------------------ I3
1 1 0 1
I3 = z’
1 1 1 0