Computer Architecture and Organization

Prof. Indranil Sengupta

Department of Computer Science and Engineering
Indian Institute of Technology, Kharagpur

Lecture - 34
Design of Adders (Part II)

We continue with our discussion on Adders. If you recall in our last lecture we looked at
one kind of adder the so called ripple carry adder. And in the ripple carry adder have
observed one very distinct characteristic; that in the worst case the carry input ripples
through all the stage up to the final carry output, this results in an overall worst case
delay of the adder which is proportional to the number of bits or the number of stages.

(Refer Slide Time: 00:59)

So, we continue with our discussion. So, this is what I just now mentioned that the ripple
carry adder that we have seen so far the total propagation delay in the worst case has
been seen to be proportional to n and the primary reason was the rippling effect.

Suppose I consider the full adder at any particular stage, now that full adder is unable to
start the addition until or unless its carry input is available. Now in the ripple carry adder
this carry input is coming sequentially through a rippling effect, because of that the
different full adders was having to wait till the carry input comes. So, this second
approach is another kind of adder that we look here is called carry look ahead adder. So,
as the name implies we are doing some kind of a look ahead to determine the values of
the carry.

If you can do that, then the total time complexity of the adder can reduce from order n
which is roughly proportional to the number of stages to order 1 which means addition
can be done in constant time independent of the number of stages, but this is possible if
somehow we can generate the carry bits in parallel. If you can do that then all the full
adders can perform their addition simultaneously. Here there is no need to wait for the
previous full adder to complete; this is the basic idea behind the carry look ahead adder.
But the only trouble here is that the hardware complexity the amount of gates that will be
required will increase rapidly with the value of n. This is the drawback of carry look
ahead adder.

(Refer Slide Time: 03:18)

So, let us see the basic idea, we look at a full adder in terms of how it works let us
consider the full adder in the i-th stage of a ripple carry adder say where the inputs are
Ai, Bi and Ci and the outputs are Si and Ci+1 . Now we define 2 different kinds of events
one we call as the carry generate, other we call the carry propagate. The idea is similar to
full adder.
(Refer Slide Time: 04:01)

Let us consider full adder at stage i. So, the inputs are A i and Bi , sum is Si and input
carry is Ci and the output carry is Ci+1. Carry generate means that this full adder will be
generating a carry; meaning Ci+1 will be 1 independent of what has happened in the
previous stage.

So, I do not care what the value of C i is; Ci can be 0, Ci can be 1 whatever it depends on
the previous stages, but this Ai and Bi are the present inputs from the numbers which are
coming. So, we can say if Ai is 1 and Bi is 1 then definitely there will be a carry out this
will imply Ci+1 will be 1. This is the scenario for carry generate a carry is generating in
the i-th stage itself irrespective of what has happened in the previous stage. So, you see
the generate function Gi is defined as Ai and Bi.

The second scenario is called carry propagate. Suppose my input carry has come as 1.
So, my question is under what condition this input carry will be propagating to the
output; that means, Ci+1 will be equal to 1 given Ci equal to 1 what are the other
conditions for that? This carry will be propagated under the condition when A i is 1, Bi is
0 or Ai is 0, Bi is 1 because you add this 1 to 1 and 0 it will generate a carry you add this
1 to 0 and 1 it will also generate a carry. So, this condition actually talks about the
exclusive OR function.

So, the carry propagate function is defined as A iBi. So, this is what I have explained so
far Gi equal to 1 represents the condition when a carry is generated in this stage itself
independent of the previous stages, and propagate function will be 1 when an input carry
Ci will be propagated to the output carry Ci+1. Now with respect to this Gi and Pi sub
functions we can write down an expression for Ci+1. we can write the carry output will be
1 if either a carry is generated or the propagate function is true and there was an input
carry. So, if either of these two conditions are true then C i+1 will be 1. So, I can simply
write down the expression for this Ci+1 in terms of Gi and Pi like this.

(Refer Slide Time: 08:29)

Now, this is like a recurrence relation, I am defining the carry of (i+1) in terms of the
input i. So, I can recursively expand this function like what I can write is C i+1 is Gi + PiCi
in a similar way this Ci we can expand as (Gi-1 + Pi-1 Ci-1) , again I have a Ci-1 ,expand the
Ci-1 as Gi-2, plus Pi-2Ci-2multiply them out you continue this multiplication process till you
reach C0. So, in the last term where there is C 0 will be containing the product of all the
p’s.

And there will be several other terms with G i-1, there will be a single Pi, Gi-2 there will be
2 Pi’s, Gi-3 there will be 3 Pi’s and so on. So, it can be expressed in the form of expression
like this. So, if you work this out you will see that this expression and this generalization
they mean the same thing. So, actually I am working this out for a specific case for a 4
bit adder.
(Refer Slide Time: 10:06)

Let us do it. So, let us consider a 4 bit carry look ahead adder where using the same
expressions whatever we have written down here. So, using the same expression C4 can
be written as G3 plus G2 P3, G1 P2 P3, G0, P1 P2 P3 C 0 P 0 P 1 P 2 P 3 this actually
follows from this way expression this you can check C 3 can be similarly expressed like
this, C 2 can be expressed like this, C 1 can be expressed like this and some for a full
adder is nothing.

But the xo XOR gate of the 3 inputs now already the carry propagate function we have
defined carry propagate function is nothing, but the XOR of the inputs. So, this A 0 XOR
B 0 I can replace by P 0 similarly S 1 I can write P 1 XOR C 1 S 2 I can write P 2 XOR
C 2 and so on. So, I have derived some expressions for C 1 C 2 C 3 C 4 in terms of the
carry generate and carry propagate. Suppose I want to implement this how many gates I
will required just check. So, how many 2 input and gates you record is called n 2 n 2
means 2 input and gates I need 4 the why 4 this is 1 2 input.

And function G 2 P 3, P 1 P 2, j 0 P 1 and C 0 p 0 I need 3 3 input and gates worth in

here there is 1 here there are 3 terms you have to do end 1 here, 1 here 3 we need 1 5
input and gate this is 1 5 input and gate 1 2 3 4 5 we need 2 4 input and gate 1 here and 1
here and we need 1 2 input or gate for this we need 1 3 input or gate for this 1 4 input or
gate and 1 5 input or gate and for this some unit 4 XOR gates now in addition you recall
for generating the carry generate and carry propagate signals you need n XOR gates and
n and gates.

(Refer Slide Time: 12:46)

Now, if you do this what you are actually gaining let us try to understand in normal
ripple carry adders that have seen earlier.

So, the inputs were coming carry in was there was this or this some outputs, and they
carry outputs were rippling through right. So, if this was your input carry C 0. So, C 1 C
2, C 3 and C 4 now because of the rippling effect of the carry this full adder they had to
wait till the carry input was available then only it can do the computation and generate
the sum. Now you see what we are saying is that we propose to design a separate
combinational circuit that will be directly generating my C 1, C 2, C 3 and C 4 values
and then I will be having 4 full adders they will be fed with the ab inputs as usual, and if
third carry input can be directly fed from here. So, you see there is no ripple effect
between the full adder stages.

So, after this carries are available. So, these you need just an XOR function here just an
XOR function; that means, just a 3 delta delay. So, when all your sum will be available
and this will be independent of the value of n, this is what we try to show in these
expressions. So, if we use these expressions to generate a combinational circuit we can
directly generate C 1 C 2 C 3 C 4 and if we can do that we can directly feed those carry
inputs. So, that the 4 full adders can directly we do not need the full functions of the full
adder we need just an XOR gates to generate the sums and this can be done in parallel no
rippling effect ok.

So, this expression can be simplified you just look at it one thing this sub expressions G
2 G 1 P 2 this 1 is appearing here also if you take P 3 common from these 4 terms you
will see that this same sub expressions appearing G 2, G 1 P 2, G 0 P 1 P 2, C 0 P 0 P 1 P
2.

(Refer Slide Time: 15:39)

So, if you substitutes C 3 here you this expression gets simplified to C 3 P 3 and if you
do the simplification the advantage you gain is that see here you needed 3 and 3 gates
and 2 and 4 gates here the number of gates are reducing this and 5 gate you do not need
and earlier you required some you needed an or 5 gate 5 terms or odd, but now you need
A 2 input or gate just ok.
(Refer Slide Time: 16:11)

So, your circuit becomes simpler. So, if you simply realize these functions your circuit
will look like this. So, suppose I have my P i G i functions, then using P i G i just
following these expressions you can generate the carries using this kind of a 2 level
circuit and you recall that P i is nothing, but the XOR of the inputs; that means, 1 XOR
gate and G i is nothing, but the end of the input; that means, 1 and gate. So, you need this
much hardware, but one problem is that if we look at this recurrence relation as the
number of n increases this the complexity of this function C 1, C 2, C 3, C 4, C 5, C 6
they will go on increasing.

So, the number of gates will also increase the number of inputs of the gates will also
increase. So, it will become increasingly difficult to implement or realize the function.
So, you may know that as the number of inputs the size of a gate increases the delay also
increases very rapidly. So, you need to control the number of inputs limited to a small
value 2 or 3 let say. So, this is one drawback.
(Refer Slide Time: 17:38)

So, the circuit of this 4 bit carry look ahead adder will overall look like this there will be
1 circuit which will be generating G i and Pi.

(Refer Slide Time: 17:55)

How just as I have said G i is nothing, but and P i is nothing, but XOR. So, how much
delay will take? This XOR takes a delay of thrice delta as I said earlier 3 gate delay.

And gate is a single gate delay. So, the worst case gate delays 3 delta. So, this G i and P i
generator requires the time of 3 delta to generate all the G i P i values right and this fo
this 4 bit carry look at circuit will look like this you say this is just a 2 level and or circuit
simple 2 level and or circuit, but if you implement this like this the no delay increases,
but you implement it in the original form the larger form then toula, but here this C 3 you
are bringing it back. So, it becomes worst case delay of 4 for generating C 4, but I am
assuming the previous approach where you are not doing that simplification. So, it will
be 2 delta, but using the simplification this will become 4 delta right.

And once you have done this after this time all the carry values are available in parallel.
So, you simply do an XOR with the P values to generate this sums and this XOR again
will require 3 delta. So, you see after a constant time of eight delta you have generate this
some bits in parallel. So, that is why we mentioned earlier that we are aiming to reduce
the addition time from order n to order one; that means, proportional to n to constant
time addition right. So, carry look ahead adder helps us in doing this.

(Refer Slide Time: 19:48)

But 4 bit is too less a number let us say we want to design a 16 bit adder, well having a
single 16 bit carry look ahead adder will become impractical as I have just now said;
because the expression for the carries as you would go up to the higher stages will
become exceedingly complex.

So, the product terms will become larger in sizes number of terms will also become very
large requiring a very large or gates. So, 1 alternative may be you can have as a basic
building block 4 bit carry look ahead adder modules just like the once you have designed
they will be taking eight delta eight delta times for addition, and you change them just
like a ripple counter between these stages. So, this is a mix of carry look ahead and ripple
carry adder. So, every 4 bit you can do in parallel, but this C 4 will be generated only
after you just recall this carries will be generated only after 3 delta plus 2 delta 5 delta
time. So, you will have to wait that time for the carry to be generated similarly C 8
similarly C t12 similarly C 16.

So, unless C 4 is available you cannot start addition here, unless C eight is available you
cannot start addition here, but of course, you can do this G i and P i generation in
parallel, but for this carry look ahead circuit you have to wait to lambda and only after
that carry look ahead circuit C 4 will be generated C 8 will be generated C 12 will be
generated right. So, carry propagation between modules is still slowing down the adder
here.

(Refer Slide Time: 21:48)

So, what we propose, we propose that we use a second level of carry look ahead like you
see here we have 4 bit carry look ahead modules, and inside this modules we have a
circuit like this. So, we already have G i P i generator and carry look ahead circuit.

So, what we are saying is that at a higher level let us have another carry look ahead
circuit for which you can derive the equations in a similar way that will be generating C
4, C 8, C 12 and C 16 in parallel in constant time that is quite possible. So, in that case
you can have a 2 level carry look ahead adder module this is what we are saying here use
a second level of carry look ahead mechanism to generate the input carries for the carry
look ahead blocks in parallel, and this second level block will be generating the carries C
4 C 8 C 12 and 16 together in constant time, but if n is larger maybe you will be
requiring more number of levels.

Let us say I need a 64 bit adder, I build 4 bit 4 bit modules 4 such 4 bit modules are
combined to build a 16 bit adder, 4 such 16 bit adders with another 4 bit carry look ahead
module I can use to build up 64 bit adder that is how so, called fast adders are built in
many of the recent computer systems. So, delay calculation is his fairly simple for
original single level carry look ahead adder for 16 bit, the delay was 14 delta, but for 14
delta means I am talking of this circuit because this carry generation will take 2 delta
additional time because of this carry look ahead time 2 delta because this G i P i can be
generated in parallel by only blocks then this 2 2 2 2 this time will come and it will
become 14 delta.

If you do a calculation, but if you do this modified form then you need only 10 delta be a
faster. So, I am not showing the detail of this 2 level multi-level design the conceptually
the idea I mentioned talking of a general k bit adder, I am showing a quick comparison
between a ripple carry adder.

(Refer Slide Time: 24:18)

And a carry look ahead adder with this kind of 4 bit 4 bit look ahead. 4 bit look ahead
means I am just repeating once more that my idea is like this.
(Refer Slide Time: 24:37)

So, I will be using carry look ahead adder 4 CLA 4 blocks; that means, 4 bit carry look
ahead adder. So, I use a higher level carry look ahead module for this will be parallely
generating this carries. So, what I have I have now a block which I can call as CLA 16
16 bit adder.

So, I can have 4 such blocks 16 bit adders, and above that I can have another higher level
4 bit CLA module. So, these will be generating the carry inputs for these high level
adders. So, in multiples of 4 I can do, in 4 bits then 16 bits then 64 bits then 256 bits and
so on well means assuming that 4 is a reasonable number beyond 4 it will be too
expensive to construct a carry look ahead adder this is our assumption. So, from this
calculation the delay for a carry look adder comes like this 6 plus 2 log n to the base 4
sealing of that if you make a simple calculation it will come. The 6 comes 3 for
generating P i and G i and 3 for the final XOR to generate the sum, and 2 into this is for
the carry generations.

And this will be the number of stages look ahead stages if any 64 for example, then this
term is equal to 3. 3 into 6, 6 and 6, 2 12 and in contrast for a ripple carry adder the delay
as you know is 2 n plus 1 delta. So, if I compare you see therefore, ripple carry adder as
n increases the delay increases rapidly, but for carry look ahead adder it does not
increase that much appreciably it remains more or less in the same order 10 12 14 fine.
(Refer Slide Time: 27:01)

Now, let us look at an alternate kind of a adder called carry select adder, this is more like
a philosophy which can make or addition faster. Because the hardware is quite
inexpensive today here we are using 2 adders for every addition, let us say we use 2
ripple carry adders and in addition we use a multiplexer.

So, why you are using 2 adders? Because the idea is that we do not know the input carry
let us say. So, it will take some time for the input carry to be generated. So, I take 2
adders the 2 adders are parallely adding the numbers first one is assuming that the carry
is 0 second 1 is assuming that the carry is one. So, we are generating the 2 sums later on
when the carry is known. So, one of the 2 sums can be selected by using a multiplexer
only after a multiplexer delay that is quite fast this is the basic idea.
(Refer Slide Time: 28:10)

So, I am showing a schematic diagram of a 4 bit can select adder you can see, here I am
assuming there is a ripple carry adder kind of a thing 4 full adders there is another adder
the first 1 is assuming carry in is 0 second 1 is assuming carry in is one.

So, the 2 fall full adders are generating the sums the first one is this orange this is this
brown. So, the 2 additions are fed to a chain of 2 to 1 multiplexers. Later on when the
actual value of key you see in gets known by that time the full adder operations are
already done. So, you can simply select the multiplexer and take out one of the 2
additions sums that you have calculated similarly the carry out.

So, either you take carry out from here or carry out from here depending on the value of
seen. So, this is what carry select adder means basically that you are trying to save time
by carrying out 2 additions bone with a carry in of 0 other with a carry in of 1 and then
later on you select one of the 2 sums based on the actual carry which is generated.
(Refer Slide Time: 29:35)

So, let us take 2 example cascades. So, here we are showing how a 16 bit carry select
adder can be generated by a cascade of 4 such 4 bit adders. Now the least significant
stage you do not need a carry select adder because you know the carry in already. So,
there is no need of any speculation it can be 0 it can be one. So, the last stage there will
be a single ripple carry adder, but in the only other stages there will be a module like to
be 1 we have explained. Now you see so after the addition time of a 4 bit adder is done.
So, all these adders are ready with their some outputs. So, this adder is also ready with its
carry output.

So, once it is done you select the multiplexer take out the correct sum select this
multiplexer take out the correct sum select the multiplexer take out the correct sum. So, it
is just a chain of multiplexers it is quite fast multiplexer means may be to get delays. So,
the total time will be the addition time of a 4 bit adder plus the total delay of this
multiplexers after that time you will be getting all these some bits in parallel. Now there
is an alternate way which can make the performance even better you can make these
adders of variable sizes like the last 1 2 bit.
(Refer Slide Time: 31:09)

Two bit 3 bit 4 bit 5 bit the idea is that there is no point in having all 4 bits; you see 2 bits
is a minimum time you need for this carry to propagate to this multiplexer. Now by the
time this multiplexer propagates the signal this 3 bit addition is also done by the time this
multiplexer propagates the signal this 4 bit addition is already done.

So, like this you have to make a calculation of the full adder delays and also the
multiplexer delays and come up with an optimum configuration this is a so called 2 2 3 4
5, 2 2 3 4 5 configuration for a 16 bit adder now by you by optimizing the sizes of this
adders you can actually minimize the overall addition time right.
(Refer Slide Time: 32:09)

So, the last kind of adder that we look at today is carry save adder. So, the concept is
very simple, in a carry save adder we are adding 3 numbers together I mean if there are
more than 3 numbers we to add then you have to construct a tree of such adders. Now
what is the carry save adder basically carry save adder is basically an independent array
of full adders and only in the last stage we need a parallel adder I will just explain.

(Refer Slide Time: 32:44)

Let us take 2 examples that we want to add 2 numbers x and y let us say we add it twice
here we are generating only the sum with without any carry propagation independently
like the 3 numbers x y z we are adding together.

So, x y z 1 1 1 will generate a sum of 1 one 0 zero will generate a sum of 0 independent
no carry propagation 0 1 1 0 also and also here carry we are generating. So, again
independently this 1 one 1 will generate a carry of 1 10 1 will generate a carry of 1 0 0 0
will generate a carry of 0 and so on.

Later on what we do this sum and carry which you have generated like this we do a shift
of this carry and add them up together this sum and carry will be getting the final correct
sum. So, we are saying is that we are not unnecessarily carrying out carry propagation,
we are living carry and sum as 2 separate words and later on we are adding them together
after proper shifting like 1 bit shift carry will be shifted by 1 place you can add them
together.

(Refer Slide Time: 34:03)

So, a carry save adder technically is just a set of independent full adders without an
interconnection because there are 3 inputs a b and a carry in. So, technically a full adder
is able to add 3 numbers x y z and is generating sum and carry as the outputs.
(Refer Slide Time: 34:24)

So, some examples I am showing here for m equal to 3 you can use a single carry save
adder to add the 3 numbers generate this sum and carry, the last stage use a parallel adder
to add them up to get the final sum. Let us say m equal to 4 numbers you want to add
you use 1 carry save adder to generate 2 to add 3 numbers sum carry and the fourth
number add it with this sum.

And carry this is a parallel adder to finally, get the sum let us say m equal to 6 take 2
CSAs in the first stage to add the 3 numbers and 3 numbers sum carry some carry use
another CSA to add 3 of them, again sum carry take the forth and bring it here again
some carry it mean parallel adder will get the final sum. So, you can have a tree of carry
save adders the last stage you need a parallel adder, the advantage is that the total
addition time can be fast and you can add many such numbers together in parallel.

So, with this we come to the end of our discussion on adders. So, in our next lecture we
shall be starting some discussion on the design of multipliers.

Thank you.