Product Order Technical Tools & Support &

Folder Now Documents Software Community

TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

TPS7A6x-Q1 High-Voltage Ultralow-I(q) Low-Dropout Regulator

1 Features 2 Applications
•
1 Qualified for Automotive Applications • Infotainment Systems With Sleep Mode
• AEC-Q100 Test Guidance With the Following: • Body Control Modules
– Device Temperature Grade 1 • Always-On Battery Applications:
– Device Temperature Grade 0 – Gateway Applications
(TPS7A6650EDGNRQ1 Only) – Remote Keyless Entry Systems
– Device HBM ESD Classification Level H2 – Immobilizers
– Device CDM ESD Classification Level C4
• Device Junction Temperature Range: 3 Description
–40°C to +150°C The TPS7A66-Q1 and TPS7A69-Q1 are low-dropout
• 4-V to 40-V Wide Vin Input Voltage Range With linear regulators designed for up to 40-V Vin
operations. With only 12-µA quiescent current at no
up to 45-V Transient
load, they are quite suitable for standby
• Output Current: 150 mA microprocessor control-unit systems, especially in
• Low Quiescent Current, I(q): automotive applications.
– 2 µA When EN = Low (Shutdown Mode) The devices feature integrated short-circuit and
– 12 µA Typical at Light Loads overcurrent protection. The devices implement reset
delay on power up to indicate the output voltage is
• Low ESR Ceramic Output Stability Capacitor
stable and in regulation. One can program the delay
(2.2 µF–100 µF) with an external capacitor. A low-voltage tracking
• 300-mV Dropout Voltage at 150 mA feature allows for a smaller input capacitor and can
(Typical, V(Vin) = 4 V) possibly eliminate the need of using a boost
• Fixed (3.3-V and 5-V) and Adjustable converter during cold-crank conditions.
(1.5-V to 5-V) Output Voltages The devices operate in the –40°C to 125°C
(Adjustable for TPS7A66-Q1 Only) temperature range. The TPS7A6650EDGNRQ1
• Low Input Voltage Tracking device is qualified to AEC-Q100 grade 0, operating in
• Integrated Power-On Reset: the –40°C to 150°C temperature range. These
features suit the devices well for power supplies in
– Programmable Reset-Pulse Delay various automotive applications.
– Open-Drain Reset Output
• Integrated Fault Protection: Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
– Thermal Shutdown
TPS7A66-Q1 HVSSOP (8) 3.00 mm × 3.00 mm
– Short-Circuit Protection
TPS7A69-Q1 SOIC (8) 4.90 mm × 3.91 mm
• Input Voltage Sense Comparator
(TPS7A69-Q1 Only) (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Packages:
– 8-Pin SOIC-D for TPS7A69-Q1
– 8-Pin HVSSOP-DGN for TPS7A6601-Q1
Hardware-Enable Option Input-Voltage-Sensing Option
TPS7A66-Q1 TPS7A69-Q1
V(bat) V(bat)
1 Vin Vout 8 V(reg) 1 Vin Vout 8 V(reg)

SO 7
2 EN PG 6

2 SI PG 6

4 CT GND 5 4 CT GND 5

Copyright © 2017, Texas Instruments Incorporated Copyright © 2017, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 17
2 Applications ........................................................... 1 8 Application and Implementation ........................ 18
3 Description ............................................................. 1 8.1 Application Information............................................ 18
4 Revision History..................................................... 2 8.2 Typical Applications ................................................ 18
5 Pin Configuration and Functions ......................... 4 9 Power Supply Recommendations...................... 21
6 Specifications......................................................... 4 10 Layout................................................................... 21
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 21
6.2 ESD Ratings.............................................................. 5 10.2 Layout Examples................................................... 21
6.3 Recommended Operating Conditions....................... 5 10.3 Power Dissipation and Thermal Considerations ... 22
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 23
6.5 Electrical Characteristics........................................... 6 11.1 Related Links ........................................................ 23
6.6 Switching Characteristics .......................................... 7 11.2 Receiving Notification of Documentation Updates 23
6.7 Typical Characteristics .............................................. 8 11.3 Community Resources.......................................... 23
7 Detailed Description ............................................ 11 11.4 Trademarks ........................................................... 23
7.1 Overview ................................................................. 11 11.5 Electrostatic Discharge Caution ............................ 23
7.2 Functional Block Diagrams ..................................... 11 11.6 Glossary ................................................................ 23
7.3 Feature Description................................................. 13 12 Mechanical, Packaging, and Orderable
Information ........................................................... 23

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (November 2014) to Revision F Page

• Changed AEC-Q100 Test Guidance Features bullet and deleted temperature range from first two AEC-Q100 sub-bullets 1
• Changed V(Vin) to VIN, Vin to VIN, V(Vout) to VOUT, Vout to VOUT, and V(CT) to VCT throughout document.............................. 1
• Added Device Junction Temperature Range Features bullet ................................................................................................ 1
• Changed associated devices to TPS7A66-Q1 and TPS7A69-Q1 throughout document ..................................................... 1
• Changed MSOP to HVSSOP throughout document ............................................................................................................. 1
• Changed CT, EN, FB/DNC, PG, SO, and VOUT descriptions in Pin Functions table .......................................................... 4
• Changed pin names FB/NU to FB/DNC, Vin to VIN, and Vout to VOUT in Pin Configuration and Functions section .......... 4
• Changed SI parameter name description and added maximum specification to SI and FB, SO, PG rows in Absolute
Maximum Ratings table .......................................................................................................................................................... 4
• Added parameter names to CT and FB, SO, PG rows in Absolute Maximum Ratings table ................................................ 4
• Added lockout to Undervoltage lockout detection parameter name....................................................................................... 6
• Added up to to Ilkg test conditions .......................................................................................................................................... 6
• Added VOUT to unit of V(TH-POR) and V(Thres) .............................................................................................................................. 6
• Added CT to V(th) parameter name......................................................................................................................................... 6
• Added header for first section of Switching Characteristics table .......................................................................................... 7
• Added UVLO Thresholds vs Temperature and Enable Thresholds vs Temperature figures................................................. 8
• Added CT Charging Current (VCT = 0) and CT Charging Threshold figures .......................................................................... 9
• Changed Device Functional Modes section ......................................................................................................................... 17

Changes from Revision D (October 2014) to Revision E Page

• Corrected voltage unit in Handling Ratings table from V to kV ............................................................................................. 5

2 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

Changes from Revision C (December 2013) to Revision D Page

• Changed CDM ESC classification level ................................................................................................................................ 1

• Changed FB/NC pin to FB/NU in Pin Functions table Added NC and NU notes to pinout drawings ................................... 4
• Removed ESD and Tstg specifications from the Absolute Maximum Ratings table ............................................................... 4
• Added ESD Ratings table ...................................................................................................................................................... 5
• Numerous changes throughout the Electrical Characteristics table ...................................................................................... 6
• Added Switching Characteristics table ................................................................................................................................... 7
• Moved an oscilloscope trace to the Applications Information section ................................................................................. 10
• Changed de-glitch time in Power-On Reset (PG) section ................................................................................................... 13
• Changed reset delay timer default delay to 290 µs from 150 µs ........................................................................................ 13
• Changed voltage at which Power-on reset initializes to 91.6% of V(Vout) ............................................................................ 13
• Changed selectable output voltage range and calculation for FB resistor divideer ............................................................. 15

Changes from Revision B (August 2013) to Revision C Page

• Corrected part number in the Description section by adding -Q1 .......................................................................................... 1

• Changed Operating ambient temperature to Operating junction temperature ....................................................................... 4
• Added PSRR graph to Typical Characteristics..................................................................................................................... 10
• Deleted a paragraph from the Thermal Protection section................................................................................................... 16

Changes from Revision A (March 2013) to Revision B Page

• Added two conditions to Vdropout in the Electrical Characteristics table .................................................................................. 6

Changes from Original (December 2012) to Revision A Page

• Deleted the ORDERING INFORMATION table...................................................................................................................... 4

• Changed From: TA Operating ambient temperature range –40 to 125°C To: TJ Operating ambient temperature
range –40 to 150°C ................................................................................................................................................................ 4

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

5 Pin Configuration and Functions

D Package (TPS7A69-Q1)
8-Pin SOIC DGN Package (TPS7A66-Q1)
Top View 8-Pin HVSSOP
Top View
VIN 1 8 VOUT
VIN 1 8 VOUT
SI 2 7 SO EN 2 7 FB/DNC

NC 3 6 PG NC 3 6 PG
CT 4 5 GND
CT 4 5 GND
NC - No internal connection
NC - No internal connection NU - Make no external connection

Pin Functions
PIN NO.
PIN NAME HVSSOP- TYPE DESCRIPTION
SOIC-D
DGN
Reset-pulse delay adjustment. Connecting a capacitor from this pin to GND changes
CT 4 4 O
the PG reset delay; see the Reset Delay Timer (CT) section for more details.
Enable pin. The device enters the standby state when the enable pin becomes lower
EN — 2 I
than the enable threshold.
Feedback pin when using external resistor divider or DNC pin when using the device
FB/DNC — 7 I
with a fixed output voltage.
GND 5 5 G Ground reference
NC 3 3 — Not-connected pin
Power good. This open-drain pin must connect to VOUT via an external resistor. VPG
PG 6 6 O
is logic level high when VOUT is above the power-on-reset threshold.
Sense input pin to supervise input voltage. Connect via an external voltage divider to
SI 2 I
VIN and GND.
Sense output. This open-drain pin must connect to VOUT via an external resistor.
SO 7 O
VSO is logic level low when VSI falls below the sense-low threshold.
VIN 1 1 P Input power-supply voltage
VOUT 8 8 O Regulated output voltage
Thermal
Pad — — Thermal pad for HVSSOP-DGN package
pad

6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
(2) (3)
VIN, EN Unregulated input –0.3 45 V
VOUT Regulated output –0.3 7 V
SI Sense input (2) –0.3 VIN V
CT Reset delay input –0.3 25 V
FB, SO, PG Feedback, sense output, power good –0.3 VOUT V
TJ Operating junction temperature range –40 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND
(3) Absolute maximum voltage, withstand 45 V for 200 ms

4 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

6.2 ESD Ratings

MIN MAX UNIT
Human body model (HBM), per AEC Q100-002 (1) 0 4
V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Corner pins (1, 4, 5, and 8) 0 1 kV
Q100-011 Other pins 0 1

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

spacer

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VIN Unregulated input 4 40 V
VEN, VSI High voltage (I/O) 0 40 V
VCT CT pin voltage 0 20 V
VOUT Regulated output 1.5 5.5 V
VPG, VSO, VFB Low voltage (I/O) 0 5.5 V
CIN Input capacitor (1) 10 µF
COUT Output capacitor (1) 2.2 100 µF
TJ Operating junction temperature –40 150 °C

(1) Values on this row refer to the nominal value of the capacitor.

6.4 Thermal Information

TPS7A66-Q1 TPS7A69-Q1
THERMAL METRIC (1) HVSSOP UNIT
SOIC (8 PINS)
(8 PINS)
RθJA Junction-to-ambient thermal resistance 63.4 113.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.0 59.6 °C/W
RθJB Junction-to-board thermal resistance 37.4 59.57 °C/W
ψJT Junction-to-top characterization parameter 3.7 12.8 °C/W
ψJB Junction-to-board characterization parameter 37.1 52.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 13.5 NA °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

6.5 Electrical Characteristics

VIN = 14 V, 1 mΩ < ESR < 2 Ω, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (VIN)
Fixed 5-V output, IO = 1 mA 5.5 40
VIN Input voltage V
Fixed 3.3-V output, IO = 1 mA 4 40
I(q) Quiescent current VIN = 5.5 V to 40 V, EN = ON, IO = 0.2 mA 12 20 µA
I(Sleep) Input sleep current No load current and EN = OFF 4 µA
I(EN) EN pin current V(EN) = 40 V 1 µA
V(bg) Band gap Reference voltage for FB 1.199 1.223 1.247 V
V(VinUVLO) Undervoltage lockout detection Ramp VIN down until output turns OFF 2.6 V
V(UVLOhys) Undervoltage hysteresis 1 V
ENABLE INPUT (EN)
VIL Logic input low level 0 0.4 V
VIH Logic input high level 1.7 V
REGULATED OUTPUT (VOUT)
IO = 1 mA, TJ = 25°C –1% 1%
VIN = 6 V to 40 V, IO = 1 mA to 150 mA, fixed 5-V version –2% 2%
VOUT Regulated output VIN = 4 V to 40 V, IO = 1 mA to 150 mA, fixed 3.3-V version –2% 2%
VIN = VOUT + 0.45 V and Vin ≥ 4 V, IO = 1 mA to 150 mA,
–2% 2%
adjustable version (1)
V(line-reg) Line regulation VIN = 5.5 V to 40 V, IO = 50 mA 5 mV
V(load-reg) Load regulation IO = 1 mA to 150 mA 20 mV
V(dropout) = VIN – VOUT, IOUT = 80 mA 180 240
VIN – VOUT, IOUT = 150 mA 300 450
V(dropout) Dropout voltage mV
VIN = 3 V, V(dropout) = VIN – VOUT, IO = 5 mA 12 27.5 58
VIN = 3 V, V(dropout) =VIN –VOUT, IO = 30 mA 44 80 145
IO Output current VOUT in regulation 0 150 mA
I(lreg-CL) Output current limit VOUT short to ground 500 800 mA
VIN = 12 V, IL = 10 mA, output capacitance = 2.2 µF
PSRR Power supply ripple rejection (2) Frequency = 100 Hz 60 dB
Frequency = 100 kHz 40
VOLTAGE SENSING PRE-WARNING
VI(S-th) Sense low threshold V(SI) decreasing 1.089 1.123 1.157 V
VI(S-th,hys) Sense threshold hysteresis 50 100 150 mV
VOL(S) Sense output low voltage (V(SI) ≤ 1.06 V, VIN ≥ 4 V, R(SO) = 10 kΩ to VOUT 0.4 V
IOH(S) Sense output leakage (V(SO) = 5 V, V(SI) ≥ 1.5 V) 1 µA
II(S) Sense input current –1 0.1 1 µA
RESET (PG)
VOL Reset output, low voltage IOL = 0.5 mA 0.4 V
Ilkg Leakage current Reset pulled up to VOUT through a 10-kΩ resistor 1 µA
V(TH-POR) Power-on-reset threshold VOUT increasing 89.6 91.6 93.6 % of VOUT
V(Thres) Hysteresis 2 % of VOUT
RESET DELAY (CT)
I(Chg) Delay-capacitor charging current VCT = 0 V 1.4 µA
V(th) CT threshold to release PG high 1 V
OPERATING TEMPERATURE RANGE
TJ Junction temperature –40 150 °C
T(shutdown) Junction shutdown temperature 175 °C
T(hyst) Hysteresis of thermal shutdown 20 °C

(1) Adjustable version with precision external feedback resistor with tolerance of less than ±1%.
(2) Design information – not tested.

6 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIMING FOR SENSE INPUT AND OUTPUT (SI, SO)
t(SDeglitch,rise) SI or SO rising deglitch time 50 260 µs
t(SDeglitch,drop) SI or SO falling deglitch time 30 240 µs
TIMING FOR RESET (PG)
Where C = delay capacitor value; capacitance
t(POR) 50 100 180 ms
Power-on-reset delay C = 100 nF (1)
t(POR-fixed) No capacitor on pin 100 290 650 µs
t(Deglitch) Reset deglitch time 20 250 µs
–6
(1) This information only is not tested in production and equation basis is (C × 1) / 1 × 10 = td (delay time).
Where C = Delay capacitor value. Capacitance C range = 100 pF to 100 nF.

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

6.7 Typical Characteristics

3 1.6
VIL VIH
2.8 1.5

1.4
Undervoltage Lockout (V)

2.6

Enable Threshold (V)

1.3
2.4
1.2
2.2
1.1
2
1
1.8
0.9
1.6 0.8
UVLO Falling UVLO Rising
1.4 0.7
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (qC) Temperature (qC)

Figure 1. UVLO Thresholds vs Temperature Figure 2. Enable Thresholds vs Temperature

92.0 1.0
PG Rising T = ±40ƒC
PG Falling 0.8
91.5 T = 25ƒC
Nominal Output Voltage (%)

Nominal Output Voltage (%)

0.6 T = 125ƒC
91.0 0.4
0.2
90.5
0.0
90.0
±0.2

89.5 ±0.4
±0.6
89.0
±0.8
88.5 ±1.0
±40 ±25 ±10 5 20 35 50 65 80 95 110 125 0 5 10 15 20 25 30 35 40 45
Temperature (ƒC) C001 Input Voltage (V) C002

Figure 3. Power-Good Threshold Voltage vs Temperature Figure 4. Line Regulation (VIN = 14 V, IL = 1 mA)
(VIN = 14 V, No Load)
120 25
T = ±40ƒC T = ±40ƒC
T = 25ƒC T = 25ƒC
100
T = 125ƒC 20 T = 125ƒC
Quiescent Current ( A)

80
IGND ( A)

15
60
10
40

5
20

0 0
0 20 40 60 80 100 0 5 10 15 20 25 30 35 40 45
Output Current (mA) C003 Input Voltage (V) C004

Figure 5. Ground Current vs Output Current (VIN = 14 V) Figure 6. Quiescent Current vs Input Voltage (IL = 0)

8 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

Typical Characteristics (continued)

2.0 350
T = ±40ƒC T = ±40ƒC
1.5 T = 25ƒC 300 T = 25ƒC
Nominal Output Voltage (%)

T = 125ƒC T = 125ƒC
1.0

Dropout Voltage (mV)

250
0.5
200
0.0
150
±0.5
100
±1.0

±1.5 50

±2.0 0
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Output Current (mA) C005 Output Current (mA) C006

Figure 7. Load Regulation (VIN = 14 V) Figure 8. Dropout Voltage vs Output Current (VIN = 4 V)
6 3.5

5 3.0

2.5
Output Voltage (V)

Output Voltage (V)

4
2.0
3
1.5
2
1.0

1 0.5

0 0.0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
Supply Voltage (V) C007 Supply Voltage (V) C008

Figure 9. Output Voltage vs Supply Voltage Figure 10. Output Voltage vs Supply Voltage
(Fixed 5-V Version, IL = 0) (Fixed 3.3-V Version, IL = 0)
2 1
Delay-Capacitor Charging Current ( PA)

1.9 0.975
1.8 0.95
1.7 0.925
CT Threshold (V)

1.6 0.9
1.5 0.875
1.4 0.85
1.3 0.825
1.2 0.8
1.1 0.775
1 0.75
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (qC) Temperature (qC)

Figure 11. CT Charging Current (VCT = 0) Figure 12. CT Charging Threshold

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

Typical Characteristics (continued)

100.0 120

100
80.0
80

PSRR (dB)
CLOAD ( F)

60.0
60
Stable Region
40.0 40

20
20.0
0

2.2
0.0 ±20
0.001
0.0 0.5 1.0 1.5 2.0 10 100 1k 10k 100k 1M 10M 100M
ESR of Cout ( ) C009 Frequency (Hz) C010

Figure 13. Load Capacitance vs ESR Stability Figure 14. Power-Supply Rejection Ratio vs Frequency

All oscilloscope waveforms were taken at room temperature. All oscilloscope waveforms were taken at room temperature.

Figure 15. Load Transient Response, 10 ms/div Figure 16. Load Transient Response, 10 ms/div

All oscilloscope waveforms were taken at room temperature. All oscilloscope waveforms were taken at room temperature.

Figure 17. Line Transient Response, IL = 1 mA, 1 V/µs Figure 18. Line Transient Response, IL = 10 mA, 1 V/µs

10 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

7 Detailed Description

7.1 Overview
This device is a combination of a low-dropout linear regulator with reset function. The power-on reset initializes
once the VOUT output exceeds 91.6% of the target value. The power-on-reset delay is a function of the value set
by an external capacitor on the CT pin before releasing the PG pin high.

7.2 Functional Block Diagrams

TPS7A66-Q1

UVLO
Comp Vref(3)

Vin
Band Gap 1 V(bat)
22 μF 0.1 μF

Vref1

Overcurrent
Detection

Logic Thermal
EN 2
Control Shutdown

Regulator
Control

Vout
8 V(reg)

Vref(1) 4.7 μF
+
V(reg)
GND
5

10 kΩ
PG
6

CT Reset
4
Control

Copyright © 2017, Texas Instruments Incorporated

Figure 19. TPS7A66-Q1 Functional Block Diagram

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

Functional Block Diagrams (continued)

TPS7A69-Q1

UVLO
Comp Vref3

Vin
Band Gap 1 V(bat)
22 μF 0.1 μF

Vref(1)

Overcurrent
Detection

Logic Thermal
Control Shutdown

Regulator
Control

Vout
8 V(reg)

Vref(1) 4.7 μF
+
V(reg)
GND
5

10 kΩ
PG
6

CT Reset
4
Control
V(reg)

V(bat) 10 kΩ
SO
7

SI
2
Vref(1) +

Copyright © 2017, Texas Instruments Incorporated

Figure 20. TPS7A69-Q1 Functional Block Diagram

12 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

7.3 Feature Description

7.3.1 Enable (EN)
This is a high-voltage-tolerant pin; high input activates the device and turns the regulator ON. One can connect
this input to the VIN pin for self-bias applications.

7.3.2 Regulated Output (VOUT)

This is the regulated output based on the required voltage. The output has current limitation. During initial power
up, the regulator has a soft start incorporated to control initial current through the pass element and the output
capacitor.
In the event the regulator drops out of regulation, the output tracks the input minus a drop based on the load
current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage
recovers above the minimum start-up level.

7.3.3 Power-On Reset (PG)

This is an output with an external pullup resistor to the regulated supply. The output remains low until the
regulated VOUT has exceeded approximately 90% of the set value and the power-on-reset delay has expired. The
on-chip oscillator presets the delay. The regulated output falling below the 90% level asserts this output low after
a short de-glitch time of approximately 250 µs (typical).

7.3.4 Reset Delay Timer (CT)

An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output
current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this
pin is open, the default delay time is 290 µs (typ). After releasing the PG pin high, the capacitor on this pin
discharges, thus allowing the capacitor to charge from approximately 0.2 V for the next power-on-reset delay-
timer function.
An external capacitor, CT, defines the reset-pulse delay time, t(POR), with the charge time of:
C(CT) ´ 1 V
t (POR) =
1 mA (1)
The power-on reset initializes once the output VOUT exceeds 91.6% of the programmed value. The power-on-
reset delay is a function of the value set by an external capacitor on the CT pin before the releasing of the PG
pin high.

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

Feature Description (continued)

Vin

t < t(Deglitch)

VTH(POR)
V(Thres)
Vout

V(th) V(th)
CT

t(POR) t(POR)
t(Deglitch)

PG

t(Deglitch)

Figure 21. Conditions for Activation of Reset

Vin

0.9 × V (th)

Vout

CT V(th)

t(POR)

PG

Figure 22. External Programmable Reset Delay

14 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

Feature Description (continued)

7.3.5 Sense Comparator (SI and SO for TPS7A69-Q1)
The sense comparator compares the input signal with an internal voltage reference of 1.223 V for rising and
1.123 V for falling threshold. The use of an external voltage divider makes this comparator very flexible in the
application.
The device can supervise the input voltage either before or after the protection diode and give additional
information to the microprocessor, like low-voltage warnings.
The regulator operates in low-power mode when the output load is below 2 mA (typical, 1-mA to 10-mA range).
In this mode, the regulator output tolerance is approximately VOUT ± 1%.

7.3.6 Adjustable Output Voltage (FB for TPS7A6601-Q1)

One can select an output voltage between 1.5 V and 5 V by using an external resistor divider. Calculate the
output voltage using the following equation, where V(FB) = 1.223 V. The recommendation for R1 and R2 is that
both be less than 100 kΩ.
æ R1 ö
V(Vout) = V(FB) ´ ç 1 +
è R2 ÷ø (2)

TPS7A6601-Q1

V(bat)
1 Vin Vout 8 V(reg)

C1 C2

R1

2 EN FB/NU 7 R3

R2

PG 6

4 CT GND 5
C3

Figure 23. External Feedback Resistor Divider

7.3.7 Undervoltage Shutdown

There is an internally fixed undervoltage shutdown threshold. Undervoltage shutdown activates when the input
voltage on VIN drops below V(VinUVLO). This ensures the regulator is not latched into an unknown state during low
input supply voltage. If the input voltage has a negative transient which drops below the UVLO threshold and
recovers, the regulator shuts down and powers up with a normal power-up sequence once the input voltage is
above the required levels.

7.3.8 Low-Voltage Tracking

At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage
based on the load current (IO) and switch resistance (R(SW)). This allows for a smaller input capacitor and can
possibly eliminate the need of using a boost convertor during cold-crank conditions.

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

Feature Description (continued)

7.3.9 Thermal Shutdown
These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous
normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point, the
output turns on again.
Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the
device to cool. Cooling of the junction temperature to approximately 150°C enables the output circuitry.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
The purpose of the design of the internal protection circuitry of the TPS7A66-Q1, TPS7A69-Q1 is for protection
against overload conditions, not as a replacement for proper heat-sinking. Continuously running the TPS7A66-
Q1 or TPS7A69-Q1 into thermal shutdown degrades device reliability.

16 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

7.4 Device Functional Modes

Table 1 provides a quick comparison between the regulation, disabled, and current limit modes of operation.

Table 1. Device Functional Modes Comparison

PARAMETER
OPERATING MODE
VIN EN (1) IO TJ
Regulation (2) VIN > VOUT(nom) + V(dropout) VEN > VIH IO < I(Ireg-CL) TJ ≤ TJ(maximum)
Disabled (3) VIN < V(VinUVLO) VEN < VIL — TJ > Tsd
Current limit operation — — IO ≥ I(Ireg-CL) —

(1) EN is only required for the TPS7A66-Q1 devices.

(2) All table conditions must be met.
(3) The device is disabled when any condition is met.

7.4.1 Regulation
The device regulates the output to the nominal output voltage when all the conditions in Table 1 are met.

7.4.2 Disabled
When disabled, the pass device is turned off and the internal circuits are shut down.

7.4.3 Operation With V(VinUVLO)< VIN < VIN(min)

When the input voltage is ramping up the device typically turns on when the input voltage is greater than
V(VinUVLO) plus V(UVLOhys). When the input voltage is ramping down the device is specified to turn off when the
input voltage becomes less than or equal to V(VinUVLO).

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS7A66-Q1 and TPS7A69-Q1 devices are 150-mA low-dropout linear regulators designed for up to 40-V
VIN operation with only 12 µA quiescent current at no load. One can use the Pspice transient model, which is
downloadable from the product folder (see Related Links), for evaluating the base function of the devices. in
addition, there are specific EVMs designed for these devices. Both the EVM and its user guide are available on
the product folder as well.

8.2 Typical Applications

Figure 24 and Figure 26 depict typical application circuits for the TPS7A66-Q1 and TPS7A69-Q1, respectively.
One may use different values of external components, depending on the end application. An application may
require a larger output capacitor during fast load steps in order to prevent reset from occurring. TI recommends a
low-ESR ceramic capacitor with dielectric of type X5R or X7R.

8.2.1 TPS7A66-Q1 Typical Application

TPS7A66-Q1

V(bat)
1 Vin Vout 8 V(reg)

1 μF 2.2 μF

10 kΩ

2 EN
PG 6

4 CT
1 nF GND 5

Copyright © 2017, Texas Instruments Incorporated

Figure 24. Typical Application Schematic for TPS7A66-Q1

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the design parameters.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 4 V to 40 V
Output voltage 3.3 V
Output current rating 150 mA
Output capacitor range 2.2 µF to 100 µF
Output capacitor ESR range 1 mΩ to 2 Ω
CT capacitor range 100 pF to 100 nF

18 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

8.2.1.2 Detailed Design Procedure

To begin the design process, determine the following:
• Input voltage range
• Output voltage
• Output current rating
• Input capacitor
• Output capacitor
• Power-up-reset delay time

8.2.1.2.1 Input Capacitor

The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 10 µF. The voltage rating must be greater than the maximum
input voltage.

8.2.1.2.2 Output Capacitor

The device requires an output capacitor to stablize the output voltage. The capacitor value should be between
2.2 µF and 100 µF. The ESR range should be between 1 mΩ and 2 Ω. TI recommends to selecting a ceramic
capacitor with low ESR to improve the load transient response.

8.2.1.3 Application Curve

Figure 25. Power Up (5 V), 20 ms/div, IL = 20 mA

8.2.2 TPS7A69-Q1 Typical Application

TPS7A69-Q1

V(bat)
1 Vin Vout 8 V(reg)

1 μF 2.2 μF

10 kΩ
R3

SO 7 10 kΩ
2 SI
2.2 μF
R4 PG 6

4 CT GND 5
1 nF

Copyright © 2017, Texas Instruments Incorporated

Figure 26. Typical Application Schematic for TPS7A69-Q1

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

8.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 4 V to 40 V
Output voltage 3.3 V
Output current rating 150 mA
Output capacitor range 2.2 µF to 100 µF
Output capacitor ESR range 1 mΩ to 2 Ω
CT capacitor range 100 pF to 100 nF
Low-voltage tracking threshold 6 V to 9 V

8.2.2.2 Detailed Design Procedure

To begin the design process, determine the following:
• Input voltage range
• Output voltage
• Output current rating
• Input capacitor
• Output capacitor
• Power-up-reset delay time
• Low-voltage tracking threshold

8.2.2.2.1 Low-Voltage Tracking Threshold

After determining the low-voltage tracking threshold, calculate the ratio of the resistor divider connected to VIN,
SI, and GND by the following equation:
R3 V(LT)
= -1
R4 1.223 (3)
TI recommends that the values of both R3 and R4 be less than 100 kΩ.

8.2.2.3 Application Curve

Figure 27. Power Up (5 V), 20 ms/div, IL = 20 mA

20 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

9 Power Supply Recommendations

Design of the device is for operation from an input voltage supply with a range between 4 V and 28 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS7A66-Q1 or
TPS7A69-Q1 device, TI recommends adding an electrolytic capacitor with a value of 22 µF and a ceramic
bypass capacitor at the input.

10 Layout

10.1 Layout Guidelines

The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple
undesirable signals from nearby components (especially from logic and digital devices, such as microcontrollers
and microprocessors); these capacitive-coupled signals may produce undesirable output voltage transients. In
these cases, TI recommends the use of a fixed-voltage version of the TPS7A66-Q1, or isolation of the FB node
by flooding the local PCB area with ground-plane copper to minimize any undesirable signal coupling.

10.1.1 Package Mounting

Solder pad footprint recommendations for the TPS7A66-Q1 and TPS7A69-Q1 are available at the end of this
product data sheet and at www.ti.com.

10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance

For the layout of TPS7A66-Q1 and TPS7A69-Q1, place the input and output capacitors close to the devices as
shown in Figure 28 and Figure 29, respectively. In order to enhance the thermal performance, TI recommends
surrounding the device with some vias.
To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board
design with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin
of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin
of the device.
Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability.
Place every capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces because they may impact system performance negatively
and even cause instability.
If possible, and to ensure the maximum performance specified in this product data sheet, use the same layout
pattern used for the TPS7A66-Q1 and TPS7A69-Q1 evaluation board, available at www.ti.com.

10.2 Layout Examples

Vin Vout

EN FB/NU

NC PG

CT GND

Power Ground

Figure 28. TPS7A66-Q1 Board Layout Diagram

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

Layout Examples (continued)

Vin Vout

SI SO

NC PG

CT GND

Power Ground

Figure 29. TPS7A69-Q1 Board Layout Diagram

10.3 Power Dissipation and Thermal Considerations

Calculate power dissipated in the device using Equation 4.
space
PD = I O ´ (V(Vin) - V(Vout) ) + I (q) ´ V(Vin) (4)
where:
PD = continuous power dissipation
IO = output current
VIN = input voltage
VOUT = output voltage
As I(q) << IO, therefore ignore the term I(q) × VIN in Equation 4.
For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ)
using Equation 5.
space
T J = TA + (R qJA ´ PD) ) (5)
where:
RθJA = junction-to-ambient air thermal impedance
space
DT = TJ - TA = (R qJA ´ PD) ) (6)

22 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

11 Device and Documentation Support

11.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.

Table 4. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
TPS7A66-Q1 Click here Click here Click here Click here Click here
TPS7A69-Q1 Click here Click here Click here Click here Click here

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

PACKAGE OUTLINE
TM
DGN0008G SCALE 4.000
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
2.15
1.95 9 1.1 MAX

8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

1.846
TYPICAL
1.646

4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com

24 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 TPS7A66-Q1, TPS7A69-Q1
www.ti.com SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017

EXAMPLE BOARD LAYOUT

TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.846)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(2.15)
6X (0.65) (1.22)
5
4

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4225480/A 11/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TPS7A66-Q1 TPS7A69-Q1
TPS7A66-Q1, TPS7A69-Q1
SLVSBL0F – DECEMBER 2012 – REVISED DECEMBER 2017 www.ti.com

EXAMPLE STENCIL DESIGN

TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(2.15)
SYMM BASED ON
0.125 THICK
STENCIL

6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.06 X 2.40
0.125 1.846 X 2.15 (SHOWN)
0.15 1.69 X 1.96
0.175 1.56 X 1.82

4225480/A 11/2019
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
26 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: TPS7A66-Q1 TPS7A69-Q1

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS7A6601QDGNRQ1 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PA4Q

TPS7A6633QDGNRQ1 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PA2Q

TPS7A6650QDGNRQ1 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PA1Q

TPS7A6933QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 6933

TPS7A6950QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 6950

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A6601QDGNRQ1 HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS7A6633QDGNRQ1 HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS7A6650QDGNRQ1 HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS7A6933QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS7A6950QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7A6601QDGNRQ1 HVSSOP DGN 8 2500 366.0 364.0 50.0
TPS7A6633QDGNRQ1 HVSSOP DGN 8 2500 366.0 364.0 50.0
TPS7A6650QDGNRQ1 HVSSOP DGN 8 2500 366.0 364.0 50.0
TPS7A6933QDRQ1 SOIC D 8 2500 356.0 356.0 35.0
TPS7A6950QDRQ1 SOIC D 8 2500 356.0 356.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
TM
DGN 8 PowerPAD HVSSOP - 1.1 mm max height
3 x 3, 0.65 mm pitch SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225482/B

www.ti.com
 PACKAGE OUTLINE
TM
DGN0008G SCALE 4.000
PowerPAD HVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
2.15
1.95 9 1.1 MAX

8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

1.846
TYPICAL
1.646

4225480/C 11/2024
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGN0008G PowerPAD HVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.57)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(1.89)

6X (0.65) (1.22)
5
4

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4225480/C 11/2024
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGN0008G PowerPAD HVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(1.89)
SYMM BASED ON
0.125 THICK
STENCIL
6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 1.76 X 2.11
0.125 1.57 X 1.89 (SHOWN)
0.15 1.43 X 1.73
0.175 1.33 X 1.60

4225480/C 11/2024
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2025, Texas Instruments Incorporated