1.Convert the following flip-flop : i.D-Flip-Flop to SR-Flip-Flop ii.

T-Flip-Flop to JK-Flip-
Flop
Ans.
2.Design Ring Counter for 1100 bits and analyze how many Flip flop required and
jus fy why D flip flop used in Ring counter?
Ans.
1.Direct Data Transfer:
D flip-flops have a dedicated data input (D) that directly receives the state of the
previous flip-flop in the ring. This simplifies the connec on within the counter, as
each flip-flop's output directly feeds into the next flip-flop's input.
2. Synchronous Opera on:
D flip-flops are synchronous, meaning they update their state only on the rising (or
falling) edge of the clock signal. This ensures that all flip-flops in the ring counter
change their states simultaneously, maintaining a consistent and predictable
sequence of states.
3. Clock Edge Triggering:
The clock edge triggering of D flip-flops ensures that transi ons occur only at
specific clock edges, reducing the possibility of glitches or errors due to signal
propaga on delays. This makes them more reliable in ring counter applica ons.
4. Simple Implementa on:
D flip-flops are rela vely simple in their design and logic, making them easier to
implement in hardware compared to other types of flip-flops. This contributes to
their cost-effec veness and widespread use in ring counter circuits.
5. No Addi onal Logic:
Unlike some other flip-flops (like JK flip-flops), D flip-flops don't require addi onal
logic gates to control their state transi ons based on exis ng inputs. This simplifies
the overall design of the ring counter, reducing its complexity and poten al for
errors.

3.Design 3 Bit Ayschronus down counter using T flip flop analyze how many Flip flop
required.
Ans.
The block diagram of 3-bit Asynchronous binary down counter is similar to the
block diagram of 3-bit Asynchronous binary up counter. But, the only
difference is that instead of connecting the normal outputs of one stage flip-
flop as clock signal for next stage flip-flop, connect the complemented outputs of
one stage flip-flop as clock signal for next stage flip-flop. Complemented
output goes from 1 to 0 is same as the normal output goes from 0 to 1.

Assume the initial status of T flip-flops from rightmost to leftmost

is Q2Q1Q0=000. Here, Q2 & Q0 are MSB & LSB respectively. We can understand
the working of 3-bit asynchronous binary down counter from the following
table.

No of negative edge of Clock Q0 LSB Q1 Q2MSB

0 0 0

1 1 1 1

2 0 1 1

3 1 0 1

4 0 0 1

5 1 1 0

6 0 1 0

7 1 0 0
Here Q0 toggled for every negative edge of clock signal. Q1 toggled for
every Q0 that goes from 0 to 1, otherwise remained in the previous state.
Similarly, Q2toggled for every Q1 that goes from 0 to 1, otherwise remained in the
previous state.

The initial status of the T flip-flops in the absence of clock signal is Q2Q1Q0=000.
This is decremented by one for every negative edge of clock signal and reaches to
the same value at 8th negative edge of clock signal. This pattern repeats when
further negative edges of clock signal are applied.

4.Compare combina onal circuit and sequen al circuit.

Sequential Circuits Combinational Circuit
1. In this output depends upon present 1.In this output depends only upon
as well as past input. present input.
2. Speed is slow. 2.Speed is fast.
3. It is designed tough as compared to 3.It is designed easy.
combina onal circuits.
4. There exists a feedback path 4.There is no feedback between input
between input and output. and output.
5. This is me dependent. 5.This is me independent.
6. Elementary building blocks: Flip- 6.Elementary building blocks: Logic
flops gates
7. Mainly used for storing data. 7.Used for arithme c as well as
boolean opera ons.
8. Sequen al circuits have capability to 8.Combina onal circuits don’t have
store any state or to retain earlier capability to store any state.
state.
9. As sequen al circuits are clock 9.As combina onal circuits don’t have
dependent they need triggering. clock, they don’t require triggering.
10. These circuits have memory 10.These circuits do not have any
element. memory element.
11. It is not easy to use and handle. 11.It is easy to use and handle.

5.Differen ate between edge triggering and level triggering

Ans.
 Edge Triggering Level Triggering

Level triggering is based

Edge triggering is based on detecting a sharp edge
on recognizing a specified signal
in the input signal.
level.

Level triggering is frequently

employed in applications that call
Edge triggering is frequently used in synchronous
for continuous monitoring of an
circuits,
input signal,
such as counters and flip-flops.
such as data acquisition and
control systems.

Edge triggering is particularly helpful in applications Level triggering lacks the ability to
that need precise timing. regulate precise timing.

When edge triggering is used, the output signal is

In level triggering, the output
activated when the trigger edge is detected and
signal will remain in the triggered
changes to the opposing state. As long as the input
condition.
signal is at or above the trigger level.

6.What is shi register and explain its types

Ans. A group of flip flops which is used to store mul ple bits of data and the data
is moved from one flip flop to another is known as Shi Register. The bits stored in
registers shi ed when the clock pulse is applied within and inside or outside the
registers. To form an n-bit shi register, we have to connect n number of flip flops.
A Shi Register, which shi s the bit to the le , is known as "Shi le register", and
it shi s the bit to the right, known as "Right le register".

Serial IN Serial OUT

Serial IN Parallel OUT
Parallel IN Serial OUT

Parallel IN Parallel OUT

7.Dis nguish between latch and flip-flop.
Ans.
Parameter Flip-Flop Latch

Basic Principle Flip-flop utilizes an edge triggering Latch follows a level triggering
approach. approach.

Clock Signal The clock signal is present. The clock signal is absent.

Designed Using You can design it using Latches along You can design it using Logic gates.
with a clock.

Sensitivity Flip-flop is sensitive to the applied input Latches are sensitive to the applied
and the clock signal. input signal- only when enabled.

Operating It has a slow operating speed. It has comparatively fast operating

Speed speed.

Classification You can classify a flip-flop into a A user cannot classify the Latch this
synchronous or asynchronous flip-flop. way.

Working Flip-Flops work using the binary input Latches operate only using binary
and the clock signal. inputs.

Power It requires more power. It requires comparatively less power.

Requirement

Analysis of It is quite easy to perform circuit analysis. Analyzing the circuit is quite complex.
Circuit
8.What is counter ? Design Mod 10 counter using IC7490?

Counter is a sequential circuit. A digital circuit which is used for a counting

pulses is known counter. Counter is the widest application of flip-flops. It is
a group of flip-flops with a clock signal applied.

9.What is race around condi on? How to avoid race condi on?
Ans. For J-K flip-flop, if J=K=1, and if clk=1 for a long period of me, then Q output
will toggle as long as CLK is high, which makes the output of the flip-flop unstable
or uncertain. This problem is called race around condi on in J-K flip-flop.
The Master-Slave Flip-Flop is basically a combina on of two JK flip-flops connected
together in a series configura on. Out of these, one acts as the “master” and the
other as a “slave”. The output from the master flip flop is connected to the two
inputs of the slave flip flop whose output is fed back to inputs of the master flip
flop. In addi on to these two flip-flops, the circuit also includes an inverter. The
inverter is connected to clock pulse in such a way that the inverted clock pulse is
given to the slave flip-flop. In other words if CP=0 for a master flip-flop, then CP=1
for a slave flip-flop and if CP=1 for master flip flop then it becomes 0 for slave flip
flop.

10.Explain 3-bit synchronous up/down counter.

Ans. •Up Counter:
The up counter counts binary form 0 to7 i.e.(000 to 111).It counts from
small to large number. It’s O/P goes on increasing as they receive clock pulse
•Down Counter:
This down counter counts binary from 7-0 i.e.(111-000).It counts from
large to small number. It’s O/P goes on increasing as they receive clock pulse
• Excita on Table:- The tabular representa on of the opera on of flip flop.

Present State Next State J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

For M = 0, it acts as an Up counter and for M =1 as an Down counter.

State Table for 3 bit Up-Down Synchronous Counter:
Control Present State Next State Input for Flip-flop
input M QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA
0 0 0 0 0 0 1 0 X 0 X 1 X
0 0 0 1 0 1 0 0 X 1 X X 1
0 0 1 0 0 1 1 0 X X 0 1 X
0 0 1 1 1 0 0 1 X X 1 X 1
0 1 0 0 1 0 1 X 0 0 X 1 X
0 1 0 1 1 1 0 X 0 1 X X 1
0 1 1 0 1 1 1 X 0 X 0 1 X
0 1 1 1 0 0 0 X 1 X 1 X 1
1 0 0 0 1 1 1 1 X 1 X X 1
1 0 0 1 0 0 0 0 X 0 X 1 X
1 0 1 0 0 0 1 0 X X 1 X 1
1 0 1 1 0 1 0 0 X X 0 1 X
1 1 0 0 0 1 1 X 1 1 X X 1
1 1 0 1 1 0 0 X 0 0 X 1 X
1 1 1 0 1 0 1 X 0 X 1 X 1
1 1 1 1 1 1 0 X 0 X 0 1 X
11.Explain 4-bit ring counter using D-Flip fliop.
Ans. A ring counter is a special type of applica on of the Serial IN Serial
OUT Shi register. The only difference between the shi register and the ring
counter is that the last flip flop outcome is taken as the output in the shi register.
But in the ring counter, this outcome is passed to the first flip flop as an input. All
of the remaining things in the ring counter are the same as the shi register.
No. of states in Ring counter = No. of lip- lop used

Below is the block diagram of the 4-bit ring counter. Here, we use 4 D flip flops. The
same clock pulse is passed to the clock input of all the flip flops as a synchronous
counter. The Overriding input(ORI) is used to design this circuit.

The Overriding input is used as clear and pre-set.

Working

The ORI input is passed to the PR input of the first flip flop, i.e., FF-0, and it is also
passed to the clear input of the remaining three flip flops, i.e., FF-1, FF-2, and FF-3.
The pre-set input set to 0 for the first flip flop. So, the output of the first flip flop is
one, and the outputs of the remaining flip flops are 0. The output of the first flip flop
is used to form the ring in the ring counter and referred to as Pre-set 1.

12.Compare synchonous and Asychronous counter?what are the draw back of

Asynchonous counter over the synchornous counter?

Ans.
S.NO Synchronous Counter Asynchronous Counter

In synchronous counter we use a In asynchronous counter main clock is

1. universal clock that is common to only applied to the first flip flop and then
 all flip flops through out the for rest of flip flops the output of previous
circuit. flip flop is taken as a clock.

Synchronous Counter is faster in Asynchronous Counter is slower as

operation as compared to compared to synchronous counter in
2. Asynchronous Counter. operation.

Synchronous Counter does not Asynchronous Counter produces decoding

3. produce any decoding errors. error.

Synchronous Counter is also Asynchronous Counter is also called Serial

4. called Parallel Counter. Counter.

Synchronous Counter designing as

well implementation are complex
due to increasing the number of Asynchronous Counter designing as well
5. states. as implementation is very easy.

Synchronous Counter will operate Asynchronous Counter will operate only in

6. in any desired count sequence. fixed count sequence (UP/DOWN).

Asynchronous Counter examples

Synchronous Counter examples are: Ripple UP counter, Ripple DOWN
7. are: Ring counter, Johnson counter. counter.

In synchronous counter, In asynchronous counter, there is high

8. propagation delay is less. propagation delay.

One of the main disadvantages of asynchronous counters is that they can be slower
and less reliable than synchronous counters, since they have more propagation
delay and glitches that can cause errors. Another disadvantage is that they can be
more limited and inflexible than synchronous counters, since they have a fixed
counting sequence and mode.

It's easier to design than the Asynchronous counter. It acts simultaneously. No

propagation delay associated with it. Count sequence is controlled using logic gates,
error chances are lower. Faster operation than the Asynchronous counter. All flip
flops in synchronous counter are driven by a single, common clock pulse. They
require large components and circuitry than asynchronous counters.
13.Explain and Design 3bit synchronus up counter usinf JK FF?

Ans.
Step 1: Find the number of flip flops.

A flip flop stores only one bit, hence for a 3 bit counter, 3 flip flops(n=3) are needed to design
the counter.

Number of states = 2n = 23 = 8 states(000, 001, 010, 011, 100, 101, 110, 111)

Step 2: Choose the type of flip flop.

Since the type of flip flop is given in the problem, let us use JK flip flops.

Step 3: Draw state diagram for the counter

Step 4: Obtain excitation table for the counter.

The excitation table is framed for 8 states of the counter. Since 3 flip-flops are used in the
design, the present state, next state and flip flop inputs for each flip flop are considered.

Step 5: Derive the flip flop input functions.

Using Karnaugh maps, the input functions for the 3 flip flops are derived. The present states
are the input for all the flip-flops. Since there are three inputs(QC, QB, QA), 8 cell K-map is
used.
Step 6: Draw the logic diagram of the counter.
14.Design Mod-24 counter using 7490
Ans.

15.Design a sequence detector using MS J-K flip-flop sequence is 1101

Ans. The Johnson counter is similar to the Ring counter. The only difference
between the Johnson counter and the ring counter is that the outcome of the last
flip flop is passed to the first flip flop as an input. But in Johnson counter, the
inverted outcome Q' of the last flip flop is passed as an input. The remaining work
of the Johnson counter is the same as a ring counter. The Johnson counter is also
referred to as the Creeping counter.
1. No. of states in Johnson counter = No. of flip-flop used
2. Number of used states=2n
3. Number of unused states=2n - 2*n