ECE411/EEE411

VLSI Design
• A MOSFET is ON/OFF depends on voltage difference
between Gate and Body
• VGB does not ensure current in MOSFET
• The current is controlled by VDS
• VGB controls ON/OFF
• VDS controls the amount of current.
 The effect of VDS
NMOS for normal operation

𝑄𝑄𝑏𝑏𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜
G

---------------- ++++++++ ----------------

S ---------------- ++++++++ ---------------- D 𝑣𝑣𝐺𝐺𝐺𝐺 = 𝑣𝑣𝐺𝐺𝑠𝑠
---------------- ++++++++ ----------------
n-------------- p+++++++ n-------------- 𝑣𝑣𝑇𝑇𝑇𝑇

B
𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺𝐺𝐺

𝑣𝑣𝐷𝐷𝐷𝐷 𝑉𝑉𝐺𝐺𝑆𝑆 = 𝑉𝑉𝐺𝐺𝐺𝐺 > 𝑉𝑉𝑇𝑇𝑇𝑇

Each voltage source needs a ground. And there can be only 𝑄𝑄𝐺𝐺𝐺𝐺 = (−)
one ground. So negative terminals are considered as ground.
When 𝑉𝑉𝐷𝐷𝐷𝐷 is small
• 𝑉𝑉𝐺𝐺𝐷𝐷 = 𝑉𝑉𝐺𝐺𝑆𝑆 - 𝑉𝑉𝐷𝐷𝐷𝐷
• when 𝑉𝑉𝐷𝐷𝐷𝐷 is small 𝑉𝑉𝐺𝐺𝐺𝐺 ~ 𝑉𝑉𝐺𝐺𝐺𝐺
G
• Therefore, the bottom plate charge
at the source side is equal to the
bottom plate charge at the drain
---------------- ---------------- ---------------- 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺𝑠𝑠 side.
S ---------------- ++++++++ ---------------- D • As a result, the total bottom plate
---------------- ++++++++ ---------------- charge looks like a rectangle.
n-------------- p+++++++ n-------------- • It acts as constant resistance.
𝑉𝑉
B • Therefore, 𝐼𝐼𝐷𝐷𝐷𝐷 = 𝑅𝑅𝐷𝐷𝐷𝐷
𝐼𝐼𝐷𝐷𝐷𝐷 • Current increases linearly with 𝑉𝑉𝐷𝐷𝐷𝐷 .

𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠

𝑉𝑉𝐷𝐷𝐷𝐷
 𝑄𝑄𝑏𝑏𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 > 𝑄𝑄𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝐷𝐷
• When 𝑣𝑣𝐷𝐷𝐷𝐷 is medium,
• 𝑉𝑉𝐺𝐺𝐷𝐷 = 𝑉𝑉𝐺𝐺𝐺𝐺 - 𝑉𝑉𝐷𝐷𝐷𝐷
• Now, we cannot ignore 𝑉𝑉𝐷𝐷𝐷𝐷 , 𝑉𝑉𝐺𝐺𝐺𝐺 < 𝑉𝑉𝐺𝐺𝐺𝐺 G

𝑄𝑄𝑏𝑏𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 ----------------
S ----------------
----------------- ---------------- 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺𝑠𝑠
------ ++++ ---------------- D
---------------- ++++++++ ----------------
n-------------- p+++++++ n--------------
𝑉𝑉𝑇𝑇𝑇𝑇
B
𝑉𝑉𝐺𝐺𝐺𝐺
𝑉𝑉𝐺𝐺𝐷𝐷 V
𝑉𝑉𝐷𝐷𝐷𝐷 𝐼𝐼𝐷𝐷𝐷𝐷

𝑉𝑉𝐷𝐷𝐷𝐷 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑉𝑉𝐷𝐷𝐷𝐷 𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚

Shape of bottom charge is trapezoid. Because X
section on right is smaller than left. So resistance
increase
𝑉𝑉𝐷𝐷𝐷𝐷
 𝑣𝑣𝐷𝐷𝐷𝐷
𝐼𝐼𝐷𝐷𝐷𝐷 ↓= As a result, current does not increase linearly anymore and slows down,
𝑅𝑅 ↑

𝑣𝑣𝐷𝐷𝐷𝐷 𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚
𝑣𝑣𝐷𝐷𝐷𝐷 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠

𝑣𝑣𝐷𝐷𝐷𝐷

When 𝒗𝒗𝑫𝑫𝑫𝑫 is large,

𝑣𝑣𝐺𝐺𝐺𝐺 = 𝑣𝑣𝐺𝐺𝐺𝐺 −𝑣𝑣𝐷𝐷𝐷𝐷
𝑣𝑣𝐷𝐷𝐷𝐷 is as large, 𝑣𝑣𝐷𝐷𝐷𝐷 > 𝑣𝑣𝐺𝐺𝐺𝐺
𝑣𝑣𝐺𝐺𝑆𝑆 −𝑣𝑣𝐷𝐷𝐷𝐷 <0
𝑣𝑣𝐺𝐺𝐺𝐺 <0
𝑣𝑣𝐺𝐺𝐺𝐺 < 𝑣𝑣𝐺𝐺𝑆𝑆
When 𝑽𝑽𝑫𝑫𝑫𝑫 is large,
𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝐷𝐷𝐷𝐷
𝑉𝑉𝐷𝐷𝐷𝐷 is as large, 𝑉𝑉𝐷𝐷𝐷𝐷 > 𝑉𝑉𝐺𝐺𝐺𝐺
𝑉𝑉𝐺𝐺𝑆𝑆 − 𝑉𝑉𝐷𝐷𝐷𝐷 < 0
𝑉𝑉𝐺𝐺𝐺𝐺 <0
𝑉𝑉𝐺𝐺𝐺𝐺 < 𝑉𝑉𝐺𝐺𝑆𝑆

𝑄𝑄𝑏𝑏𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜
G

(+)
𝑣𝑣𝑇𝑇𝑇𝑇 ---------------- -----------+++ ---------------- 𝑉𝑉𝐺𝐺𝐺𝐺
S ---------------- ---------------- D = 𝑉𝑉𝐺𝐺𝑠𝑠
----- +++++
𝑉𝑉𝐺𝐺𝑆𝑆 ---------------- ++++++++ ----------------
V
𝑉𝑉𝐺𝐺𝐺𝐺 n-------------- p+++++++ n--------------
(−)
B

𝑄𝑄𝑏𝑏𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 = Negative
𝑉𝑉𝐷𝐷𝐷𝐷
𝑄𝑄𝑏𝑏𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 = Positive
• Current should not flow under this condition.
• However, the distance between the (-) regions is very V
small. As a result, electrons jump from one side to the
other due to tunneling.
• Therefore, the origin of carriers is tunneling.
• After tunneling, carriers experience a large electric
field due to the high 𝑉𝑉𝐷𝐷𝐷𝐷
• The velocity of carriers becomes constant at high
electric fields.
E
Now, J=nqv
• n is carrier concentration from the tunneling constant.
• q is the charge of each carrier constant.
• v is the velocity of the carrier constant due to the
large electric field.
• All parameters are constant, so the current is also
constant.
𝐼𝐼𝐷𝐷𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷 𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙
𝑉𝑉𝐷𝐷𝐷𝐷 𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚

𝑉𝑉𝐷𝐷𝐷𝐷 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠

𝑉𝑉𝐷𝐷𝐷𝐷
 • So far we haven’t modified VGS
• If VGS is changed, we will another plot.
𝐼𝐼𝐷𝐷𝐷𝐷

𝑉𝑉𝐺𝐺𝑆𝑆2
𝑉𝑉𝐺𝐺𝑆𝑆2 > 𝑉𝑉𝐺𝐺𝐺𝐺1
𝑉𝑉𝐺𝐺𝑆𝑆1

𝑣𝑣𝐷𝐷𝐷𝐷

• Why does 𝐼𝐼𝐷𝐷𝐷𝐷 increase with the increase of 𝑣𝑣𝐺𝐺𝐺𝐺 ?

• When 𝑣𝑣𝐺𝐺𝐺𝐺 increased, it attracts more charge in source side. More charge means less resistance

𝑉𝑉𝐷𝐷𝐷𝐷
𝐼𝐼𝐷𝐷𝐷𝐷 ↑=
𝑅𝑅 ↓
 Universal gates.
I. NOT gate II. NOR gate III. NAND gate.
NOT gate:
The gate can be implemented in many ways. Historically, an NMOS
in series with a resistor represents NOT gate.

VDD
Graphical representation,
VDD= I X R+ Vout
I R Vout=VDS
VDD= I X R+
Vout I=(VDD - VDS)/R

Vin
 I is the MOSFET current.
MOSFET I vs 𝑉𝑉𝐷𝐷𝐷𝐷
𝑉𝑉𝑉𝑉𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷
𝐼𝐼 = −
𝑅𝑅 𝑅𝑅

VDD and R are constant. 𝑉𝑉𝑉𝑉𝑉𝑉

𝑅𝑅
1 𝑉𝑉𝑉𝑉𝑉𝑉
𝐼𝐼 = − . 𝑉𝑉𝐷𝐷𝐷𝐷 +
𝑅𝑅 𝑅𝑅

y = m x+ c

𝑣𝑣𝑇𝑇𝑇𝑇 = 𝑉𝑉𝐺𝐺𝑆𝑆
𝑉𝑉𝑉𝑉𝑉𝑉
 VDD

Need to find Vout= VDS, for given Vin=VGS I R

VGS4>VGS3>VGS2>VGS1
Vout
Vin
Vout= VDS

VDD
Vin=VGS=0, I=0 Vout=VDS= VDD
VGS1>0, I ↑
VDD=↑ I X R + VDS ↓
When VDD constant,
VDS ↓ = Vout ↓
VGS2>VGS1, I ↑↑, VDS ↓ ↓ = Vout ↓↓
Vin=VGS
VGS1 VGS2 VGS3 VGS4 VGS5
 Vout

Why not Zero?

Vin=VGS

IDS

@ High VGS current is high. However, for load line the

Vin=VGS intercept point VDS=Vout≠ 0
P=VDD X IDS
When Vin is high lot power loss

P=VDD x IDS
But circuit is singular and easy make
Vin=VGS
 Vout

Another version PMOS with Resistor. VDD Why not VDD?

Vout<VDD

Vin

R
 Pull-up OFF(1) Pull-up ON(0)

Same problem with power loss. Pull-down Z(float) 1

How to Reduce Power loss? OFF(0)
NMOS → pull down Pull-down 0 X
PMOS → pull up ON(1)

• The problem is resistor

• It can limit current, but it cannot stop current, I>0
• The resistor need to be replaced by switch
• Transistor can be used as switch

pMOS
pull-up
network
inputs
output
R
nMOS
pull-down
network
CMOS Inverter

A Y
0 1
1 0

A Y
Series and Parallel g1
a
0
a
0
a
1
a
1
a

g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

a a a a
◦ nMOS: 1 = ON a
0 0 1 1
g1
◦ pMOS: 0 = ON g2
0 1 0 1
b
◦ Series: both must be ON b b b b
(b) ON OFF OFF OFF

◦ Parallel: either can be ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF
Determine Series and Parallel

1. Find unique output from truth table

2. Conditions
a. A and B = 1; Y = 0
↓ ↓
series NMOS (pull down)
a. A and B = 0; Y = 1
↓ ↓
series PMOS (pull up)
3. Connections
a. NMOS – series; PMOS – parallel
b. NMOS – parallel; PMOS – series
 CMOS NAND Gate g1
a
0
a
0
a
1
a
1
a

g2
0 1 0 1
b b b b b
A B Y (a) OFF OFF OFF ON
1. Find unique output from truth table
2. Conditions a a a a a

a. A and B = 1; Y = 0 0 0 1 g1
0 0 1 1

↓ ↓ g2
0 1 0 1
series NMOS (pull down) 0 1 1 b b b b b
a. A and B = 0; Y = 1 (b) ON OFF OFF OFF
↓ ↓
series PMOS (pull up) 1 0 1 a
3. Connections
a a a a

a. NMOS – series; PMOS – parallel g1 g2

b. NMOS – parallel; PMOS – series

1 1 0 b
0 0 0 1 1 0 1 1

b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF
 CMOS NOR Gate g1
a
0
a
0
a
1
a
1
a

g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

1. Find unique output from truth table A B Y a a a a

2. Conditions a
0 0 1 1
a. A and B = 1; Y = 0 g1

↓ ↓ 0 0 1 g2
0 1 0 1
series NMOS (pull down) b b b b b
a. A and B = 0; Y = 1 0 1 0 (b) ON OFF OFF OFF
↓ ↓
series PMOS (pull up) a a a a a
3. Connections 1 0 0 g1 g2
a. NMOS – series; PMOS – parallel 0 0 0 1 1 0 1 1

b. NMOS – parallel; PMOS – series b

1 1 0 (c)
b

OFF
b

ON
b

ON
b

ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF
Conduction Complement

◦ Complementary CMOS gates always produce 0 or 1

◦ Ex: NAND gate
◦ Series nMOS: Y=0 when both inputs are 1
◦ Thus Y=1 when either input is 0
Y
◦ Requires parallel pMOS A
◦ Rule of Conduction Complements
◦ Pull-up network is complemented of pull-down B
◦ Parallel -> series, series -> parallel
Designing CMOS Circuit from Boolean
Expression
• Convert the function as SOP or POS
• If the expression is not in NOR format. Convert SOP to NOR format
◦ 𝑌𝑌 = 𝐴𝐴. 𝐵𝐵 + 𝐶𝐶. 𝐷𝐷 • Make series NMOS for each product term
• Make parallel PMOS for each product term
• Connect all NMOS branches in parallel
• Connect all PMOS branches in series
• If the expression is not in NAND format. Convert POS to NAND format
• Make parallel NMOS for each sum term
• Make series PMOS for each sum term
• Connect all NMOS branches in series
• Connect all PMOS branches in parallel