VLSI Design

MODULE 2
Dr. Shashank M Gowda
Associate Professor,
Department of ECE, YIT, Moodbidri
 Introduction
◼ It all started in 1958
◼ First IC with 2 transistors at Texas Instruments.
◼ Flip-Flop by Jack Kilby- Nobel Prize for IC in 2000

◼ As on 2023
◼ 134 billion transistors in Apple Microprocessor
◼ 153 billion transistors in AMD’s GPU
◼ TSMC's 5 nm semiconductor manufacturing process.
1 billion is equivalent to 100 crores

◼ Reason
◼ As transistors became smaller
◼ They became faster Became Cheaper to Manufacture
◼ Dissipate less power Consumed Less Power
Introduction
◼ First was point contact transistor.
◼ Bipolar Junction Transistor
◼ Reliable, less noisy, and more power efficient
◼ Power dissipated by the base currents was more even when the
device is not switching
◼ Field Effect Transistor’s
◼ MOSFET’s found its way in 1960’s.
◼ Zero Control current in idle state.
▪ Types- nMOS and pMOS

◼ CMOS Logic
◼ Complementary MOS
◼ nMOS Logic Gates- Intel’s nMOS technology
A Brief History
Invention of the Transistor
◼ Vacuum tubes ruled in first half of 20th century
◼ Large, Expensive, Power- hungry, Unreliable.
◼ 1947: First point contact transistor (3 terminal devices)
◼ Shockley, Bardeen and Brattain at Bell Labs
A Brief History

❑ 1958: First Integrated Circuit

◼ Flip- Flop using two transistors.
◼ Built by Jack Kilby (Nobel Laureate) at Texas Instruments.
◼ Robert Noyce (Fairchild) is also considered as a co-inventor.

Kilby’s IC
A Brief History
◼ First Planer IC built in 1961

◼ 2003
◼ Intel Pentium 4 processor (55 million transistors)
◼ 512 Mbit DRAM (> 0.5 billion transistors)
◼ 53% compound annual growth rate over 45 years
◼ No other technology has grown so fast so long
◼ Driven by miniaturization of transistors
◼ Smaller is cheaper, faster, lower in power!
◼ Revolutionary effects on society
MOS Integrated Circuits
❑ 1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
❑ 1980s-present: CMOS processes for low idle power

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

Moore’s Law
◼ 1965: Gordon Moore plotted transistor on each chip
◼ Fit straight line on semilog scale
◼ Transistor counts have doubled every two years.
Pentium 4 Processor
• Modern transistors are few microns wide and approximately
0.1 micron or less in length
• Human hair is 80-90 microns in diameter
Evolution in Logic Complexity in IC’s
Features of Integrated Circuits
Silicon Semiconductors
◼ Modern electronic chips are built mostly on silicon substrates
◼ Silicon is a Group IV semiconducting material
◼ crystal lattice: covalent bonds hold each atom to four neighbours

Si Si Si

Si Si Si

Si Si Si
 Dopants
◼ Silicon is a semiconductor at room temperature
◼ Pure silicon has few free carriers and conducts poorly
◼ Adding dopants increases the conductivity drastically
◼ Dopant from Group V (e.g. As, P): extra electron (n-type)
◼ Dopant from Group III (e.g. B, Al): missing electron, called
hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si
p-n Junctions
◼ First semiconductor (two terminal) devices
◼ A junction between p-type and n-type
semiconductor forms a diode.
◼ Current flows only in one direction

p-type n-type

anode cathode
Transistor Types
◼ Bipolar transistors
◼ npn or pnp silicon structure
◼ Small current into very thin base layer controls large
currents between emitter and collector
◼ Base currents limit integration density

◼ Metal Oxide Semiconductor Field Effect Transistors

◼ nMOS and pMOS MOSFETS
◼ Voltage applied to insulated gate controls current
between source and drain
◼ Low power allows very high integration
◼ First patent in the ’20s in USA and Germany
◼ Not widely used until the ’60s or ’70s
Simplified View of MOSFET
 MOS Transistors
◼ Four terminal device: gate, source, drain, body
◼ Gate – oxide – body stack looks like a capacitor
◼ Gate and body are conductors (body is also called the substrate)
◼ SiO2 (oxide) is a “good” insulator (separates the gate from the body
◼ Called metal–oxide–semiconductor (MOS) capacitor, even though
gate is mostly made of poly-crystalline silicon (polysilicon)

Source Gate Drain Source Gate Drain

Polysilicon Polysilicon
SiO 2 SiO 2

n+ n+ p+ p+
p bulk Si n bulk Si

NMOS PMOS
NMOS Operation
◼ Body is commonly tied to ground (0 V)
◼ Drain is at a higher voltage than Source
◼ When the gate is at a low voltage:
◼ P-type body is at low voltage
◼ Source-body and drain-body “diodes” are OFF
◼ No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si
NMOS Operation Cont.
◼ When the gate is at a high voltage: Positive charge
on gate of MOS capacitor
◼ Negative charge is attracted to body under the gate
◼ Inverts a channel under gate to “n-type” (N-channel, hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
◼ Now current can flow through “n-type” silicon from source
through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si
PMOS Transistor
◼ Similar, but doping and voltages reversed
◼ Body tied to high voltage (VDD)
◼ Drain is at a lower voltage than the Source
◼ Gate low: transistor ON
◼ Gate high: transistor OFF
◼ Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO 2

p+ p+

n bulk Si
Power Supply Voltage
◼ GND = 0 V

◼ In 1980’s, VDD = 5V

◼ VDD has decreased in modern processes

◼ High VDD would damage modern tiny
transistors
◼ Lower VDD saves power

◼ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

Transistors as Switches
◼ In Digital circuits, MOS transistors are
electrically controlled switches.

◼ Voltage at gate controls path from source to

drain. g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
CMOS Logic
→ A static CMOS gate has
→ An nMOS pull-down network to connect the output to 0 (GND)
→ An pMOS pull-up network to connect the output to 1 (VDD)
 CMOS Logic
→ When both pull-up and pull-down are OFF, the highimpedance or floating Z
output state results.
→ This is of importance in multiplexers, memory elements, and tristate bus
drivers.
→ The crowbarred (or contention) X level exists when both pull-up and pull-
down are simultaneously turned ON.
→ Contention between the two networks results in an indeterminate output level
and dissipates static power.
→ It is usually an unwanted condition.
CMOS Logic
Connection and behavior of series and parallel transistors
CMOS Logic
Connection and behavior of series and parallel transistors
CMOS Inverter

A Y
0
1

A Y
CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
CMOS Inverter

A Y
VDD
0
1

A Y

A Y
GND
CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0
ON Y is pulled low by the
turned on NMOS
Device. Hence
A Y NMOS is the pull-
down device.
GND
BACK
CMOS Inverter

A Y VDD Y is pulled high by

0 1 the turned on PMOS
Device. Hence PMOS

1 0 ON is the pull-up device.

A=0 Y=1
OFF
A Y
GND
CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
CMOS NAND Gate
A B Y
0 0 1
0 1 1 Y
1 0 1 A
1 1 0
B
CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
1 0
A=0 OFF
1 1
B=0
OFF
CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
1 0
A=0 OFF
1 1
B=1
ON
CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
1 0 1
A=1 ON
1 1
B=0
OFF
CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
1 0 1
A=1 ON
1 1 0
B=1
ON
CMOS NAND Gate
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y
3-input NAND Gate
◼ Y is pulled low if ALL inputs are 1
◼ Y is pulled high if ANY input is 0
3-input NAND Gate
◼ Y is pulled low if ALL inputs are 1
◼ Y is pulled high if ANY input is 0

Y
A
B
C
3-input NOR Gate
→ If any input is high, the output is pulled low through the nMOS
transistors.
→ If all inputs are low, the output is pulled high through the pMOS
transistors.
3-input NOR Gate
→ If any input is high, the output is pulled low through the parallel nMOS
transistors.
→ If all inputs are low, the output is pulled high through the series pMOS
transistors.
 Compound Gates
→More complex logic function in a single stage of logic.
→Using a combination of series and parallel switch structures.

→Example

Y = (A · B) + (C · D)

AND-OR-INVERT-22, or AOI22
 Compound Gates
→ The AND expressions (A · B) and (C · D) may be
implemented by series connections of switches.
 Compound Gates
→ Now ORing the result requires the parallel connection of these two
structures.

→ For the pMOS pull-up network, we must compute the complementary

expression using switches that turn on with inverted polarity.

→ Transistors that appear in series in the pull-down network must appear in

parallel in the pull-up network.
 Compound Gates
→ Putting the networks together yields the full schematic conduction
complements
OR-AND-INVERT-3-1 or OAI31
Y = (A + B + C) · D
OR-AND-INVERT-3-1 or OAI31
Y = (A + B + C) · D
Signal Strength
→The strength of a signal is measured by how closely it
approximates an ideal voltage source.

→The power supplies, or rails, (VDD and GND) are the

source of the strongest 1s and 0s.

→nMOS passes a strong 0, weak 1.

→pMOS passes a strong 1, weak 0.

Weak 1: HIGH voltage level is somewhat less than VDD .

Weak 0: LOW voltage level is somewhat greater than 0 .
Signal Strength

Note that both the control input and its complement are required by the
transmission gate. This is called double rail logic.
 VIDEO LINK
nmos ON → g=1
pmos ON → g=0
Transmission gate
→ When an nMOS or pMOS is used alone as an imperfect switch. Single nmos
or pmos is also called as pass transistor.
→ By combining an nMOS and a pMOS transistor in parallel we get a
transmission gate or pass gate.
 Multiplexers
→A multiplexer chooses the output from among several
inputs based on a select signal.

→A 2-input, or 2:1 multiplexer,

→Chooses input D0 when the select is 0
→Chooses input D1 when the select is 1.

→The logic function is

Multiplexers
 MOS transistor symbols
D
e-
G Ids nMOS

D
e-
G Ids
pMOS

S
→ The MOS transistor is a majority-carrier device in which the current in a
conducting channel between the source and drain is controlled by a voltage applied
to the gate.
→ nMOS → Electrons
→ pMOS → Holes
Isolated MOS Structure
→ Isolated MOS structure with a gate and body
but no source or drain.

Polysilicon Gate
Silicon Dioxide Insulator

+ + + + + + + + + + +
+ + + + + + + + + + +
+ + + + + + + + + + + P-type Body

+ + + + + + + + + + +
+ + + + + + + + + + +
Majority Charge Carriers - Holes
Minority Charge Carriers - Electrons
Accumulation Mode
→ A negative voltage is applied to the gate.

→ There is negative charge on the gate.

→ The mobile positively charged holes are attracted to the region

beneath the gate.
 Depletion Mode
→ A small positive voltage is applied to the gate.

→ This results in some positive charge on the gate.

→ The holes in the body are repelled from the region directly beneath
the gate

→ This results in a depletion region forming below the gate.

Vg > 0

Vg < Vt
 Inversion Mode
→ A higher positive potential exceeding a critical threshold voltage Vt is
applied

→ This higher positive voltage, attracts more positive charge to the gate.
→ The holes are repelled further and some free electrons in the body are
attracted to the region beneath the gate.
→ This conductive layer of electrons in the p-type body is called the
inversion layer.
nMOS transistor
 That small amounts of leakage
currents through OFF transistors
can become significant, especially
Cutoff when multiplied by millions or
billions of transistors on a chip.

→ the gate-to-source voltage Vgs is less than the threshold voltage.

→ The source and drain have free electrons.
→ The body has free holes but no free electrons.
→ If the source is grounded, the junctions between the body and the
source or drain are reverse-biased, so little or no current flows.

→ We say the transistor is OFF, and this mode of operation is called

cutoff.
 Linear
→ The gate voltage is greater than the threshold voltage.
→ Now an inversion region of electrons (majority carriers) called the
channel connects the source and drain.
→ It creates a conductive path and turning the transistor ON.
→ The number of carriers and the conductivity increases with the
gate voltage.
 Linear
→ The potential difference between drain and source is

→ There is no electric field tending to push current from drain to source.

 Linear
→ When a small positive potential Vds is applied to the drain.
→ Current Ids flows through the channel from drain to source.
→ The current increases with increase in both the drain voltage and gate
voltage.
→ This mode is called
→ Linear
→ Resistive →Triode
→ Nonsaturated →Unsaturated
 Saturation
→ If Vds becomes sufficiently large that
Vgd < Vt

→ The channel is no longer inverted near the drain and becomes pinched off

→ However, conduction is still brought about by the drift of electrons under the
influence of the positive drain voltage.
 Saturation
→ As electrons reach the end of the channel
→ They are injected into the depletion region near the drain and
accelerated toward the drain.

→ Above this drain voltage the current Ids is controlled only by the gate
voltage and ceases to be influenced by the drain.

→ This mode is called saturation.

 Summary
→The nMOS transistor has three modes of operation.

→ If Vgs < Vt , the transistor is cutoff (OFF). CUTOFF

→ If Vgs > Vt , the transistor turns ON. LINEAR

→ If Vds is small, the transistor acts as a linear resistor in which
the current flow is proportional to Vds.

→ If Vgs > Vt and Vds is large, the transistor acts as a current source
in which the current flow becomes independent of Vds .
SATURATION
Summary
Vgs versus Ids
Threshold Voltage
◼ The threshold voltage, Vt, for an MOS
transistor can be defined as
◼ The voltage applied between the gate and source
of an MOS device below which the drain-to-source
current Ids, drops to zero.

◼ In general, the threshold voltage is a function

of a number of parameters including the
following:
◼ gate material, gate insulation material, gate
insulator thickness, channel doping, impurities at
silicon-insulator interface, voltage between source
and substrate Vsb.
Threshold Voltage Adjustment
(Vt Adjustment)
◼ The threshold voltage (Vt) of a MOS
transistor can be adjusted to ensure proper
operation. This is done using two main
techniques:
◼ Ion Implantation – Changing the doping
concentration at the silicon-insulator interface.

◼ Dual Dielectric Layers – Using different

insulating materials for the gate.
Threshold Voltage Adjustment
(Vt Adjustment)
◼ In the dual dielectric approach, a layer of
silicon nitride (Si₃N₄) (which has a higher
permittivity of 7.5) is combined with silicon
dioxide (SiO₂) (permittivity 3.9).

◼ This combination creates an effective

permittivity of about 6, making the
insulating layer act like a thinner SiO₂ layer
while keeping the same physical properties.
 Long- Channel I-V Characterstics
→ To derive a Model relating the current and voltage (I-V) for an nMOS
transistor in each of the three regions.

→ The model assumes that the channel length is long enough that the lateral
electric field i.e., the field between source and drain, is relatively low.

→ This model is variously known as the long-channel, ideal, first-order, or

Shockley model.

→ The long-channel model assumes that the current through an OFF

transistor is 0.

→ When a transistor turns ON (Vgs > Vt), the gate attracts carriers (electrons)
to form a channel.

→ The electrons drift from source to drain at a rate proportional to the

electric field between these regions.
Long- Channel I-V Characterstics
Long- Channel I-V Characterstics
Long- Channel I-V Characterstics
Long- Channel I-V Characterstics

The current in the three regions,

Long- Channel I-V Characterstics

I- V Characteristics of Ideal nMOS Transistor

Long- Channel I-V Characterstics

I- V Characteristics of Ideal pMOS Transistor

DC Transfer Characteristics
 DC Transfer Characteristics
→Digital circuits are merely analog circuits used over
a special portion of their range.

→The DC transfer characteristics of a circuit relate the

output voltage to the input voltage.
→Assuming the input changes slowly enough that
capacitances have plenty of time to charge or discharge.

→ Specific ranges of input and output voltages are

defined as valid 0 and 1 logic levels.
Static CMOS Inverter DC
Characteristics

WORKING OF THE CMOS INVERTER WHEN INPUT IS 1

WORKING OF THE CMOS INVERTER WHEN INPUT IS 0

Static CMOS Inverter DC
Characteristics
Static CMOS Inverter DC
Characteristics
→Vtn is the threshold voltage of the n-channel device (+ve Voltage)

→Vtp is the threshold voltage of the p-channel device (-ve Voltage)

→The equations are given both in terms of Vgs /Vds and Vin /Vout.

→As the source of the nMOS transistor is grounded,

→Vgsn =(Vg - Vs)n = (Vg - 0)n= (Vg)n = Vin
→Vdsn = (Vd - Vs)n = (Vd - 0)n= (Vd)n = Vout

→ As the source of the pMOS transistor is tied to VDD,

→Vgsp = (Vg - Vs)p = Vin – VDD
→Vdsp = (Vd - Vs)p = Vout – VDD.
Static CMOS Inverter DC
Characteristics
Relationships between voltages for the three regions of operation of a CMOS inverter
Static CMOS Inverter DC
Characteristics
Relationships between voltages for the three regions of operation of a CMOS inverter
Static CMOS Inverter DC
Characteristics
→ Assume

→Vtp = –Vtn

→ The pMOS transistor is 2–3 times as wide as the

nMOS transistor so βn = βp.
Static CMOS Inverter DC
Characteristics
Static CMOS Inverter DC
Characteristics
→ The supply current IDD = Idsn = |Idsp| is also plotted against Vin in
Figure showing that both transistors are momentarily ON as Vin
passes through voltages between GND and VDD
Static CMOS Inverter DC
Characteristics
Static CMOS Inverter DC
Characteristics
→The operation of the CMOS inverter can be divided
into five regions.

→ Region A
→ The nMOS transistor is OFF so the pMOS
transistor pulls the output to VDD.

→ Region B
→ The nMOS transistor starts to turn ON, pulling
the output down.
Static CMOS Inverter DC
Characteristics
→Region C
→Both transistors are in saturation.

→ Region D
→The pMOS transistor is partially ON

→ Region E
→ The pMOS transistor is completely OFF
Static CMOS Inverter DC
Characteristics
 Beta Ratio Effects
→We have seen that for βp = βn, the inverter threshold voltage
Vin=VDD/2.

→Inverters with different beta ratios r = β p / β n are called

skewed inverters.
→If r > 1, the inverter is HI-skewed.

→If r < 1, the inverter is LO-skewed.

→If r = 1, the inverter has normal skew or is unskewed.

→As the beta ratio is changed, the switching threshold moves.

Beta Ratio Effects

Transfer characteristics of skewed inverters

 Noise Margin
→It allows you to determine the allowable noise voltage on
the input of a gate so that the output will not be corrupted.

→The noise margin of an Inverter is Defined by the Noice

Margin Low (NML) and Noise Margin High (NMH)

→The LOW noise margin, NML

→The HIGH noise margin, NMH

Noise Margin
Wafer Processing
• The primary raw material in semiconductor
fabrication is a silicon wafer.

• Wafers are thin disks of silicon with

diameters ranging from 75 mm to 150 mm
and thickness less than 1 mm.

• Wafers are cut from single crystal silicon

ingots, grown using the Czochralski
method.
Czochralski (CZ) Method for
Single Crystal Growth
• Silicon ingots are pulled from a melt of pure molten polycrystalline
silicon.

• Controlled impurities (dopants) are added to the melt to provide the

desired electrical properties.

• A seed crystal is dipped into the melt to initiate single crystal growth.

• The molten silicon is held in a quartz crucible, surrounded by a graphite

radiator.

• The graphite is heated by Radio frequency (RF) induction to maintain

the temperature just above 1425°C (melting point of silicon).

• The atmosphere above the melt is usually helium or argon to prevent

contamination.
Wafer Processing
Wafer Processing
• The seed crystal is gradually withdrawn vertically while rotating.

• As it is withdrawn, refreezing occurs, and the solidified silicon inherits

the crystal structure of the seed.

• The process continues until the melt is consumed.

• Diameter of the ingot is controlled by adjusting the withdrawal rate and

rotation speed.

• Growth rates range from 30 to 180 mm per hour.

• Ingot is sliced into wafers using internal cutting edge diamond blades.

• Wafer thickness typically varies between 0.25 mm and 1.0 mm,

depending on diameter.

• At least one face of the wafer is polished to a flat, scratch-free mirror

finish to prepare it for further semiconductor processing.
Oxidation in Silicon Processing
• Oxidation is a crucial step in the fabrication of silicon
integrated circuits (ICs).

• It involves forming a layer of silicon dioxide (SiO₂)

on the surface of a silicon wafer.

• Silicon dioxide is essential in IC manufacturing due to

its insulating properties, used in MOSFETs,
passivation layers, and field oxides.
Oxidation in Silicon Processing
• Silicon wafers are heated in an oxidizing atmosphere to form SiO₂.

• The two main oxidation techniques are:

◼ A. Wet Oxidation
• The oxidizing atmosphere contains water vapor (H₂O).
• Temperature range: 900°C to 1000°C.
• Faster oxidation rate compared to dry oxidation.
• Used for thicker oxide layers such as field oxides.

◼ B. Dry Oxidation
• The oxidizing atmosphere consists of pure oxygen (O₂).
• Temperature range: ~1200°C to achieve an acceptable growth rate.
• Slower oxidation rate, but results in a higher quality, denser SiO₂
layer.
• Used for thin gate oxides in MOS devices.
Oxidation in Silicon Processing
• The oxidation process consumes silicon as
it forms SiO₂.

• Since SiO₂ has approximately twice the

volume of silicon, the oxide layer grows in
both upward and downward directions.

• This effect is important in MOSFET

fabrication, where field oxide extends above
and below the unoxidized silicon surface.
Oxidation in Silicon Processing
Selective Diffusion
• Selective diffusion is a process used to
introduce dopant atoms into specific
regions of a silicon wafer.

• It ensures precise placement and sizing of

doped regions.

• Silicon dioxide (SiO₂) acts as a barrier

against dopants, allowing controlled diffusion.
Steps in Selective Diffusion
A. Masking with SiO₂
• A SiO₂ layer is grown on the wafer surface.

• This oxide layer acts as a mask, blocking dopants

from penetrating areas covered by SiO₂.

• Areas without SiO₂ allow dopants to diffuse into the

silicon.
Steps in Selective Diffusion
B. Opening Diffusion Windows
• Windows are created in the SiO₂ layer to
expose selected silicon regions.
• This is done by etching the SiO₂ using a
photoresist (PR) coating and UV light
exposure.
Steps in Selective Diffusion
c. Etching Process
• The photoresist (PR) coating protects certain areas
of SiO₂ while allowing others to be removed.

• UV light exposure through a patterned mask

polymerizes selected areas of PR.

• Unpolymerized areas are dissolved in a solvent,

leaving behind the desired pattern.

• The exposed SiO₂ is etched away, creating diffusion

windows.
Steps in Selective Diffusion
D. Doping the Exposed Silicon
• The wafer is exposed to a dopant source,
which penetrates only through the diffusion
windows.

• This modifies the electrical properties of

the exposed silicon areas.
Silicon Gate Process
(MOS Transistor Fabrication)
• Polysilicon (polycrystalline silicon) is used
as the gate electrode in MOS transistors.

• It helps in precise source and drain

formation with minimal overlap, improving
circuit performance.

• Polysilicon can also serve as

interconnections in ICs and can be doped to
reduce resistivity.
Steps in the Silicon Gate Process
Step 1: Formation of Field Oxide
• The wafer is initially covered with a thick
SiO₂ layer called field oxide.

• Field oxide is etched away in areas where

MOS transistors will be placed.
Steps in the Silicon Gate Process
Step 2: Growth of Gate Oxide (Thinox)
• A thin, highly controlled SiO₂ layer (gate
oxide or thinox) is grown on the exposed
silicon surface.

• This thin oxide acts as the insulating layer

between the gate and the silicon substrate.
Steps in the Silicon Gate Process
Step 3: Deposition and Etching of Polysilicon Gate

• Polysilicon is deposited over the entire

wafer.

• It is then etched to form:

• Gate electrodes for transistors.
• Interconnections between components.
Steps in the Silicon Gate Process
Step 4: Doping of Source, Drain, and Polysilicon
• The wafer is exposed to a dopant source,
leading to two effects:
• Diffusion junctions (source & drain) form in
the substrate where polysilicon does not cover
the silicon.
• Polysilicon is doped, reducing its resistivity.
• This process is self-aligned since the source
and drain do not extend under the gate.
Steps in the Silicon Gate Process
Step 5: Oxide Deposition and Contact Hole Etching

• The entire structure is covered with a new

SiO₂ layer.

• Contact holes are etched to expose

necessary regions for electrical connections.
Steps in the Silicon Gate Process
Step 6: Metal Interconnect Formation
• Aluminum (or another metal) is deposited
and etched to form electrical connections.

• This completes the MOS transistor

fabrication.
P-Well CMOS Process
• P-Well Process is a method used in CMOS
fabrication where:
• A moderately doped n-type substrate is
used.
• A p-type well (p-well) is created for n-
channel transistors.
• P-channel transistors are built directly in the
n-type substrate.

• CMOS technology originally used metal

(aluminum) gates, but now polysilicon
gates are used for better performance.
Step-by-Step P-Well CMOS
Fabrication
• First mask (p-well mask) defines the area for the p-well.
• Field oxide (FOX) is etched away to allow a deep p-type
diffusion.
• This creates a region where n-channel transistors will be
fabricated.
Step-by-Step P-Well CMOS
Fabrication
• Second mask (thin oxide or thinox mask) defines areas
where:
• Thin gate oxide is needed for transistor gates.
• Diffusion regions (source/drain) will be implanted.
• Field oxide is etched, and a thin layer of SiO₂ (gate oxide) is
grown.
Step-by-Step P-Well CMOS
Fabrication
• Polysilicon is deposited over the wafer and etched
to define the gate electrodes.

• The "self-aligned" process ensures that source and

drain regions are aligned with the gate.
Step-by-Step P-Well CMOS
Fabrication
• P+ mask is used to define areas that will receive p-type
doping.
• If this p+ doping is in the n-substrate, it forms:
• P-channel transistors or
• P-type wires for circuit connections.
• If the p+ region is inside the p-well, it creates an ohmic
contact (low-resistance electrical connection).
Step-by-Step P-Well CMOS
Fabrication
• N+ doping is applied to the areas not covered by p+
doping.
• In the p-well, this forms n-channel transistors and
connections.
• In the n-substrate, this creates ohmic contacts for
electrical pathways.
• After this step, the wafer surface is covered with SiO₂.
Step-by-Step P-Well CMOS
Fabrication
• Contact holes are etched through the SiO₂
layer to expose required regions.
• These contacts will later allow metal
connections to reach diffusion and
polysilicon regions.
Step-by-Step P-Well CMOS
Fabrication
• Metal (typically aluminum) is deposited
over the wafer.
• It is etched to form electrical connections
between different components.
P-Well CMOS Fabrication
Cross-Section of the P-Well CMOS Process
• Provides a detailed vertical cut of the fabricated CMOS
structure.

• Highlights how the p-well contains n-channel transistors

while the n-substrate contains p-channel transistors.
P-Well CMOS Fabrication
• Layout of the CMOS Transistors
• Illustrates the physical arrangement of transistors on the
wafer.

• Shows how diffusion, polysilicon, and metal interconnects

are placed to form a working CMOS circuit.
P-Well CMOS Fabrication
• Shows the circuit representation of the nMOS and pMOS transistors.

• The pMOS transistor (in the n-type substrate) is connected in series

with the nMOS transistor (in the p-well).

• This forms a CMOS inverter, a fundamental digital logic gate.

P-Well CMOS process
Purpose of Substrate Contacts
• In a p-well CMOS process, proper electrical
connections to the substrate and well are
necessary for reliable circuit operation.

• Two types of substrate contacts are used:

• VDD Substrate Contact → Connects the n-type
substrate to the positive supply (VDD).

• VSS Substrate Contact → Connects the p-well

to the negative supply (VSS or ground).
P-Well CMOS process
How These Contacts Are Formed
• VSS Contacts → Created by placing p+
regions inside the p-well.

• VDD Contacts → Created by placing n+

regions in the n-type substrate.

• These contacts ensure proper biasing and

help prevent unwanted electrical behavior
such as floating substrate effects.
Module 3 Part 2
◼ MOS structures consist of multiple layers:
◼ Conducting
◼ Insulating
◼ Transistor-forming materials
◼ Key regions in a conventional MOS device:
◼ Gate-forming region
◼ Source/Drain diffusion regions
◼ Layers include:
◼ Polysilicon, Metal, Diffusion
Electrical Characteristics of MOS
Layers
◼ Each layer contributes to:
◼ Resistance (R)
◼ Capacitance (C)
◼ Negligible Inductance (L)

◼ These elements affect:

◼ Signal delay
◼ Power dissipation
◼ Overall system performance
Resistance Calculations

Total resistance depends on:

• Sheet resistance (Rₛ)
• Geometry (L/W)
Resistance Calculations
Capacitance Estimation in MOS
Systems
◼ Switching speed of MOS circuits is highly
affected by parasitic capacitances

◼ Total output load capacitance includes:

◼ Gate capacitance (fan-out gates)
◼ Diffusion capacitance (drain regions)
◼ Routing capacitance (metal/poly
interconnects)

◼ Parasitic capacitances + resistances = RC

delay
Importance of Capacitance
Estimation
▪ Accurate estimation critical for:
▪ Timing analysis
▪ Power dissipation
▪ System performance optimization

▪ Parasitics vary with:

▪ Layout geometry
▪ Process technology
▪ Interconnect length and width
Introduction to MOS Capacitor
• MOS capacitor behavior depends on gate
voltage (Vg)
• Three regions based on surface condition:
• Accumulation: Vg < 0 (for p-substrate)
• Depletion: Moderate positive Vg
• Inversion: Vg >> 0 (n-channel forms)
Accumulation Region
◼ Accumulation Region
• For p-substrate, when Vg < 0:
• Holes accumulate at the surface
• Structure behaves like a parallel-plate
capacitor
• Capacitance approximated as:
Depletion Region in MOS
Capacitor
• For an n-MOS device on p-substrate:
• Applying a small positive gate voltage →
holes repelled
• A depletion region forms under the gate

• Depletion region = negatively charged,

carrier-free

• Formation of Depletion Layer

• Gate voltage increases → depletion region deepens (d)
Formation of Depletion Layer
Gate Capacitance in Depletion
Mode
Capacitance Behavior Summary
MOS Parasitic Capacitances
• In self-aligned silicon gate processes (1st-
order model):
• No overlap of gate over source/drain
• Main capacitance components:
• Cgs​, Cgd​: Gate to channel (source/drain)
capacitances
• Csb​, Cdb​: Source/drain to bulk (junction)
capacitances
• Cgb​: Gate to bulk (substrate) capacitance
Gate Capacitance Across
Operating Regions
◼ The behavior of gate capacitance Cg​ varies
with the MOSFET's mode of operation:
1. OFF Region

2. Linear (Triode) Region

3. Saturation Region
Total gate capacitance Cg​:
Cg=Cgb + Cgs + Cgd​
Cut-Off Region
Linear Region
◼ Linear Region
• Condition: Vgs > Vth​ and Vds < Vgs−Vth
• A channel is formed → conduction begins
• Capacitance behavior:
Saturation Region
Diffusion Capacitance
• Diffusion capacitance Cd​ arises from:
• Source and Drain diffusions of nMOS and
pMOS devices
• Diffusion wires used for interconnections

• It represents the capacitance between diffusion

region and substrate

• Strongly influenced by:

• Voltage across diffusion–substrate junction
• Junction area and depletion region depth

• Cd ∝ Area of junction (A)

Diffusion Capacitance
Diffusion Capacitance
CMOS Switching Characteristics
• The switching speed of a CMOS gate
depends on:
• Time taken to charge/discharge load
capacitance CL​

• Input transition causes:

• Output to charge CL toward VDD​, or
• Discharge CL toward VSS​
Important Timing Terms
•Rise time tr​:
Time for output to rise from 10% to 90% of its
final value

•Fall time tf​:

Time for output to fall from 90% to 10%

•Delay time td​:

Time from input 50% level to output 50% level
•Also called propagation delay
Timing Terms
◼ Rise time tr​

◼ Fall time tf
Delay Time τd
Average Gate Delay
Power Consumption in CMOS
Circuits
◼ Two main components of power
dissipation in CMOS:
1. Static Dissipation
1. Due to leakage current in transistors

2. Dynamic Dissipation
1. (a) Switching transient currents
2. (b) Charging and discharging of load
capacitances
Static Power Dissipation in CMOS
◼ Behavior of a CMOS Inverter

• When Input = ‘0’:

• nMOS is OFF, pMOS is ON

• Output is pulled up to VDD

Static Power Dissipation in CMOS
◼ Behavior of a CMOS Inverter

• When Input = ‘1’:

• nMOS is ON, pMOS is OFF

• Output is pulled up to Vss

Static Power Dissipiation Ps
Modeling Charge Sharing in
CMOS Buses
◼ Bus as a Capacitive Load
• In many digital systems, a bus line can be modeled as a
capacitor (Cb), as it accumulates charge and holds voltage.

• Often, the voltage on the bus is sampled (latched) to

determine the logic state of a signal.

◼ Charge Sharing Model

◼ Sampling using a Switch and Capacitors
• Sampling operation can be represented using:
• Bus Capacitance: Cb
• Sampling Capacitance: Cs
• Switch: Connects the two capacitances during sampling
Charge Sharing Model
◼ Initial Charges Before Closing the Switch
• Charge on Bus Capacitance:
• Qb = Cb ⋅ Vb​

• Charge on Sampling Capacitance:

• Qs = Cs ⋅ Vs
Yield in VLSI Manufacturing
Importance of Yield

•Yield is not a performance metric, but a critical

manufacturing concern.

•Influenced by:
• Technology
• Chip area
• Layout
Yield Definition
Yield Models
◼ Two models are commonly used:
◼ 1. Seed’s Model (for large chips, yield < 30%)

◼ 2. Murphy’s Model (for small chips, yield > 30%)

Seed’s Model
Murphy’s Model
Clocked CMOS Logic (C²MOS)

A typical clocked CMOS gate consists of:

Clocked CMOS Logic (C²MOS)
Cascade Voltage Switch Logic
(CVSL)
Cascade Voltage Switch Logic
(CVSL)
Cascade Voltage Switch Logic
(CVSL)
Pass Transistor Logic
nMOS Pass Transistor Logic
CMOS Pass Transistor Logic
Electrical and Physical Design of
Logic Gates
Electrical and Physical Design of
Logic Gates
Standard Layout of CMOS Inverter
Layout of CMOS Inverter with
horizontal transistors
NAND Gate
Basic layout translation of a
2-input NAND gate
NOR Gate Layout
Euler’s Graph
◼ https://www.youtube.com/watch?v=UYVyJGB
w074
Sequential MOS Logic Circuits
Sequential MOS Logic Circuits
Types of Regenerative Circuits
Types of Regenerative Circuits
Importance of Bistable Circuits
Behaviour of Bistable Elements
Voltage Transfer Characteristics
(VTC)
Energy Landscape Analogy
 CMOS Two-Inverter Bistable
Element
• These inverters are connected in a positive feedback loop — the
output of the first inverter is the input to the second, and vice versa.

• This configuration creates a system with two stable states and one
unstable state.
CMOS Two-Inverter Bistable
Element
The SR Latch Circuit
The SR Latch Circuit
CMOS SR latch circuit based on NOR2 gates
The SR Latch Circuit
CMOS SR latch circuit based on NOR2 gates
The SR Latch Circuit
CMOS SR latch circuit based on NOR2 gates
Operating Conditions
How Transistors Turn ON or OFF
in CMOS SR Latch
Capacitance at Output Nodes
Capacitance at Output Nodes
Capacitance at Output Nodes
NAND-Based SR Latch
NAND-Based SR Latch
NAND-Based SR Latch
Comparison of NAND SR Latch
with NOR SR Latch
 Depletion Load Implementation of
SR Latch

Depletion-load nMOS SR latch circuit Depletion-load nMOS SR latch circuit

based on NOR2 gates based on NAND2 gates
Implementation Comparison
Between CMOS and nMOS Depletion-Load
Clocked SR Latch
◼ Introduction
Clocked NOR-Based SR Latch
CMOS Implementation
Clocked NAND-Based SR Latch
(Active-Low Inputs)
Clocked NAND-Based SR Latch
(Active-High Inputs)
Clocked JK Latch
JK Latch: Structure and Working
Principle
NOR-based JK Latch
Implementation
Introduction to VLSI Design Styles
Introduction to VLSI Design Styles
Design Flow Approaches
Design Flow Approaches
Contemporary Design Flow

Ideal Design Flow

Testing
◼ Testing must be incorporated during the
design phase itself and should proceed
concurrently with architectural
development.
Testing Combinational Circuits
Testing Sequential Circuits
Practical Illustration of Testing
Complexity
Important Areas of Testing
Three key areas are critical for effective testing:
1. Test Generation
Test generation is the process of creating input patterns (test
vectors) that can effectively verify whether a digital circuit
operates correctly.
2. Test Verification
Test verification checks how effective the generated test
vectors are at detecting faults.
Faults (like stuck-at or open circuits) are inserted into a circuit
model, and the test vectors are applied.
3. Design for Test (DFT)
DFT is the practice of designing circuits with testing in mind,
making faults easier to detect and isolate.
Sources of Test Inputs
Fault Models in Digital Testing
◼ A fault model is a simplified representation of
a possible defect or error in a digital circuit.

◼ It helps designers and test engineers predict

how a real-world hardware fault would
behave logically and design test vectors
accordingly.

◼ Helps evaluate fault coverage (i.e., how many

potential faults can be detected)
Stuck-At Fault Model (SAF)
◼ This is the most common fault model used in
digital circuit testing.

◼ A node (input or output of a gate) is assumed

to be stuck permanently at logic 0 (S-A-0) or
logic 1 (S-A-1), regardless of the actual input
signal.

◼ The goal is to create test vectors that can

detect whether this fault is present.
Stuck-At Fault Model (SAF)
◼ Consider a simple 2-input AND gate with inputs A
and B and output Y
◼ Ideal logic: Y = A · B
◼ Suppose input A is S-A-0:
◼ No matter what value is applied to A, the gate will
behave as if A = 0.
◼ So even if A = 1 and B = 1, the output Y = 0 (should be
1).
◼ This deviation from expected output reveals the fault.

◼ Fault Coverage is the percentage of S-A faults

detected by a given set of test vectors.
◼ High fault coverage means better test effectiveness.
Limitations of Stuck-At Fault
Models
◼ Not all physical defects behave like S-A-0 or
S-A-1.
◼ Real defects include opens, shorts, bridging
faults, and transistor-level defects.
◼ Open Circuits
◼ An open connection in a CMOS gate could cause
floating nodes or indeterminate outputs, not
modeled by S-A faults.
◼ Hidden Faults
◼ In CMOS, internal nodes (like intermediate points
in series nMOS paths) are not visible at the
schematic level.
Limitations of Stuck-At Fault
Models
◼ Figure drawn below
illustrates this with
examples:
◼ Short S1 behaves like a
S-A-0 fault at input A.
◼ Short S2 changes the
actual logic function of the
gate.

◼ Hence, it is necessary to
model faults at the
transistor level, where the
complete structure is
visible.
Design for Testability
Approaches to Design for
Testability
◼ There are three main approaches
to designing circuits that are
testable:
◼ Ad Hoc Testing
◼ Structured Design for Testability
◼ Self-Test and Built-In Testing
Ad Hoc Testing
Structured Design for Testability
Self-Test and Built-In Testing