Centre Candidate

Surname
Number Number
Other Names 2

GCE A LEVEL – NEW

A490U20-1 S19-A490U20-1

ELECTRONICS – A level component 2

Application of Electronics

MONDAY, 10 JUNE 2019 – AFTERNOON

2 hours 45 minutes

For Examiner’s use only

A 49 0U201
Maximum Mark
Question
Mark Awarded

01
1. 13
2. 17
3. 20
4. 14
5. 19
6. 16
7. 11

ADDITIONAL MATERIALS 8. 14

In addition to this examination paper, you will 9. 16

require a calculator and a Data Booklet. Total 140

INSTRUCTIONS TO CANDIDATES
Use black ink or black ball-point pen.
Answer all questions.
Write your name, centre number and candidate number in the spaces at the top of this page.
Write your answers in the spaces provided in this booklet.

INFORMATION FOR CANDIDATES

The number of marks is given in brackets at the end of each question or part-question.
The assessment of the quality of extended response (QER) will take place in question 3(c).

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Answer all questions.

1. (a) The state diagram for a sequence generator is shown in the diagram:

S6

S0

S5 S1 S7

S4 S2

S3

(i) The sequence is controlled by a 2 Hz clock.

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The sequence generator has been running for a while.
How long does it take to complete each cycle of the main sequence? [2]

03
(ii) States S6 and S7 are both unused. Explain the difference between them. [2]

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(b) Part of the truth table for a different sequence generator is given below:

Current Outputs Next Outputs

State
C B A DC DB DA
0 1 0 1 1
1 0 1 0 0
2 1 0 0 1
3 0 1 1 0
4 0 0 0 1 0 1
5 0 0 1 1 0 1
6 1 1 0 1 0 0
7 1 1 1 1 0 0

(i) Complete the table. [1]

(ii) Write down a Boolean expression for DB in terms of C, B and A.

Then simplify it so that it uses only two gates. [2]
Raw expression:

DB = . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BA

.................................................................................................... C 00 01 11 10

....................................................................................................
0

.................................................................................................... 1

....................................................................................................

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(c) The circuit diagram for a third sequence generator is shown below:

C B A

DC Q DB Q DA Q

Q Q Q

Clock
input

(i) Use this diagram to obtain Boolean expressions for DC, DB and DA in terms of C,

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B and A. [3]

05
DC = . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB = . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DA = . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(ii) On power up, the system starts in the state C = 1, B = 0, A = 1.

The clock then inputs one pulse. What state is the system now in? [3]

C = .................................................

B = .................................................

A = .................................................

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2. (a) The block diagram for a PIC microcontroller is shown below:

Memory

Input Output
CPU
port port

Clock

(i) Which block contains the whole program? [1]

(ii) Which block has the task of synchronising data transfer and manipulation? [1]

(b) A student designs a direction indicator system for a bicycle.

Switches

Indicators Indicators

It has:
• four LED lamps - two, at the ends of the handlebars, pointing forwards and two, either
side of the rear wheel, pointing backwards;
• three switches, mounted at the centre of the handlebars;
• one to operate the front and rear left-hand LED lamps, to indicate a left turn;
• one to operate the front and rear right-hand lamps, to indicate a right turn;
• one to turn on all LED lamps as a ‘hazard warning’.

When a LED lamp is switched on, it flashes at a frequency of 2 Hz.

Pressing either ‘turn’ switch makes the corresponding LED lamp flash ten times and then
stop.
Pressing the ‘hazard’ switch immediately flashes all four LED lamps.

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(i) The ‘left-turn’ switch is connected to bit 0 of the input port, PORT A.
When the switch is pressed, it outputs a logic 1 signal.

The ‘right-turn switch’ is connected to bit 1 of PORT A.

Again, when pressed, the switch outputs a logic 1 signal.

The program checks whether the ‘left-turn’ or ‘right-turn’ switch has been pressed.
The subroutine ‘FLASH_LEFT’ causes the left-hand indicators to flash on and off
ten times.
The subroutine ‘FLASH_RIGHT’ has the same effect on the right-hand indicators.

Complete the code for that section: [5]

LOOP btfsc PORTA, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

call FLASH_LEFT

.............................. ..............................

call ..............................

goto ..............................

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07

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(ii) The following code gives the subroutine which is called to operate the left-hand
LED lamps. It uses a quarter-second delay subroutine called QUART.

FLASH_LEFT
movwf WSTORE
movlw d’10’
REPEAT movwf COUNT
movlw d’5’
movwf PORTB
call QUART
clrf PORTB
call QUART
decfsz COUNT,F
goto REPEAT
movf WSTORE,W
return

I. Identify which port and which pins of that port are connected to the left-hand
LED lamps. Explain how you arrive at your answer. [3]

II. Why are the instructions ‘movwf WSTORE’ and ‘movf WSTORE,W’ needed?
[1]

III. What value is stored in the register ‘COUNT’ when the program completes
the subroutine and returns to the main program? [1]

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(c) (i) The ‘hazard’ switch is connected to cause an interrupt when pressed.
Why is it important that it is connected in this way, rather than it be polled during the
main program? [2]

(ii) Complete the circuit diagram to show how the ‘hazard’ switch and any other
component(s) needed are connected to the microprocessor. The switch is a ‘push-
to-make’ type. [3]

+5 V
PIC16F88

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09
0V

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3. The following diagram shows the structure of an audio system.

Pre-
Input 1
amplifier
Tone Power Loud
Mixer
control amp speaker
Pre-
Input 2 amplifier

(a) The preamplifier for Input 1 consists of two non-inverting amplifiers, as the diagram
shows:

A B
Input 1 GA GB To mixer

The circuit diagram for each is given below:

750 kΩ

30 kΩ

0V

(i) The op-amps used have a gain-bandwidth product of 3 MHz.

What is the overall voltage gain and bandwidth of the preamplifier? [5]

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(ii) The preamplifier includes three capacitors. What is their function in this circuit? [1]

A first order active filter is used in the tone control block to boost those parts of the signal
(b)
with frequencies below 200 Hz.
The filter gives all frequencies above this limit a voltage gain of 2.

(i) Use this information and the axes provided to sketch the frequency response of this
filter. [3]

Voltage gain

100

50

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11
10

1
10 50 100 500 1000 5000 10000
Frequency / Hz

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(ii) Design a suitable circuit for this filter to create the best possible fit to the specification,
using the following components (and no others):
• an op-amp;
• a 39 kΩ resistor;
• a 82 kΩ resistor;
• a 10 nF capacitor.

Complete the circuit diagram for your design. [5]

Input Output

0V

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(c) Here is the specification for the audio system mixer:

Number of channels 2
Input impedance (both channels) >10 kΩ
Voltage gain (both channels) variable from 2× to 20×

The following circuit is proposed as a suitable solution.

300 kΩ

Channel 1
100 kΩ 15 kΩ

Output
Channel 2
100 kΩ 15 kΩ

0V
Evaluate this circuit as a solution that meets the specification given above. [6 QER]

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4. A shop owner wants a buzzer to sound every time someone opens the shop door.

One way to achieve this is to drive the buzzer from a NOT gate which is triggered by an input
sub-system consisting of a RC network and a switch S, attached to the shop door frame.

(a) The RC network uses a 120 μF capacitor and a 36 kΩ resistor.

When the switch contacts close, the capacitor charges up immediately to +12 V.

+12 V

120 μF VC 36 kΩ

0V

(i) Calculate the time constant of the RC network. [2]

(ii) Switch S is momentarily closed and then opened at time t = 0.

Determine the time taken for VC to reach 6.0 V. [2]

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(b) When the shop door is closed, the switch contacts are open. When the door opens, the
contacts close.

The NOT gate has a switching threshold of 6 V.

(i) Complete the circuit diagram by adding the NOT gate and buzzer. [2]

+12 V

120 μF VC 36 kΩ

0V

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(ii) The shop door opens for five seconds, and then closes.
For how long does the buzzer sound? Explain your answer. [2]

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(c) After using the system for a while, the shop owner decides it would be more desirable to
pulse the buzzer, rather than have it sound continuously.

The circuit is modified accordingly, using the astable circuit shown below.

(i) Calculate the frequency and mark:space ratio of this astable . [4]

12 V

12 kΩ

74 8

555
6 3 Output
12 kΩ
2
1 5

+ +
120 μF

0V

Frequency = . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hz Mark:space ratio ......................................

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(ii) Using the axes provided, sketch a graph to show two cycles of the output signal
produced by this astable, given that it pulses between 12 V and 0 V. [2]

Voltage / V

12

0 Time / s
0 1 2 3 4 5 6

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5. The following diagram shows an incomplete half-wave rectified power supply circuit.

50 Hz
mains VSEC 1000 μF V0 Load
supply

(a) (i) The peak value of the transformer secondary voltage, VSEC, is 21.2 V.
Calculate the rms value of VSEC.
[2]

(ii) Complete the circuit diagram. [2]

(iii) Calculate the peak voltage of the output voltage, V0, when the switch is open. [1]

(iv) Calculate the ripple voltage when the load current is 0.2 A. [3]

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(v) On the axes provided, draw a graph of the voltage V0 when there is a load current
of 0.2 A. [3]

The voltage, VSEC, across the transformer secondary is shown as a dashed line.

Voltage / V

20

10

0 Time
_ 10

_ VSEC
20

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(b) By modifying the power supply as shown, it provides improved line regulation and some
load regulation. It uses a 7.5 V zener diode.

VR
10 kΩ
From
half-wave
rectified
V0 VOUT
power supply

VZ = 7.5 V 10 kΩ

(i) Complete the definitions for line and load regulation: [2]

Line regulation means that the output voltage of the power supply remains

unchanged when . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Load regulation means that the output voltage of the power supply remains

unchanged when . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(ii) Write an equation linking the quantities VR, VZ and V0. [1]

(iii) Explain how this circuit delivers line regulation. [2]

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(iv) Calculate the maximum and minimum values of VOUT obtained by adjusting the
variable resistor. [3]

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6. (a) The behaviour of a thyristor depends on the signal applied to the gate terminal and the
voltage bias applied between its anode and cathode.

The table lists six combinations of these conditions, labelled A to F.

Input to gate Bias

V
Reverse
A
biased
t
V t Forward
B
biased

V
C Forward
t biased

V t Reverse
D
biased

V
E Forward
biased
t
V
F Reverse
biased
t

Select the two combinations which cause the thyristor to switch on. [2]

Combinations ....................................... and .......................................

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(b) A high-powered DC load is controlled by a thyristor.
The circuit diagram for the control system is shown below.

24 V

Load R2

S1 P Q
R1
S2

0V

(i) Here is an extract from the data sheet for the thyristor:

Characteristic Value

Minimum gate voltage 1.2 V

Holding current 200 m A

Minimum gate current 100 m A

Calculate the maximum resistance for the resistor R1. [3]

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(ii) The graphs show the signals at points P and Q over a period of time:

Voltage / V

30
Signal
at P 20

10

0 Time / s
5 10 15 20
– 10

– 20

– 30
Voltage / V
30
Signal
at Q
20

10

0 Time / s
0 5 10 15 20

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Explain what is happening to the switches and to the thyristor at:

• time = 2 s; [2]

• time = 5 s; [2]

• time = 10 s; [2]

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(c) A triac is used to control the brightness of a lamp, using a phase control sub-system.
The circuit diagram is shown below:

Phase
12 V shift
AC sub-system
X

(i) Identify component X and describe its function in this system [2]

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(ii) The graph shows the signal obtained at one point in the circuit:

Voltage

VS

QR QR
Time
P P

I. Which component does this signal appear across? …........................................ [1]

II. Explain what is happening to the triac and to the lamp:

between points P and Q; [1]

between points Q and R; [1]

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7. (a) Pulse-code modulation (PCM) is used to convert a signal from analogue into digital
format, which can then be transmitted over a digital communication system.

The first part of the process is to sample the analogue signal to produce pulse-amplitude
modulation (PAM).

Complete the third graph to illustrate this process for the given analogue signal and pulse
train. [2]

Voltage / V
5
4

Analogue 3
signal 2
1
0 Time
Voltage / V
5
4

Sampling gate 3
clock 2
1
0 Time
Voltage / V
5
4
3
Resulting
PAM 2
signal
1
0 Time

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(b) Complete the block diagram for a PCM receiver, using the following sub-systems:

• clock;
• DAC;
• low pass filter;
• Schmitt trigger;
• SIPO shift register. [4]

PCM Analogue
input output

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(i)
Complete the circuit diagram for a 4-bit serial-in-parallel out (SIPO) shift register
(c)
based on D-type flip-flops.
Data is inputted starting with the most-significant bit (msb).
Label:
• the most-significant bit (msb) of the output, D;
• the least-significant bit (lsb) of the output, A;
• the serial input of the shift register. [3]

D Q D Q D Q D Q

Q Q Q Q

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(ii) The shift register is reset so that outputs A, B, C, and D are logic 0. A logic 1 signal
is maintained at the serial input.

Complete the table to show the state of the outputs as four clock pulses are applied.
[2]

Serial
A B C D
input
Reset 1 0 0 0 0

After one clock pulse 1

After two clock pulses 1

After three clock pulses 1

After four clock pulses 1

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8. (a) The following circuit diagram shows a dedicated 4-bit asynchronous (ripple) counter.

LSB
D C B A
Pulse
generator Counter
R

(i) Distinguish between asynchronous (ripple) counters and synchronous counters.

[2]

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(ii) The counter is falling-edge triggered and is initially reset.

Complete the timing diagram to show the effect of the subsequent six clock pulses
on counter outputs B and A. [3]

Clock

0 Time

0 Time

0 Time

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(b) A system based on a dedicated 4-bit counter and
combinational logic system is required to produce the LED X Y Z
following light sequence:
Key 1
LED on
2
LED off
3

Design the system by completing:

• the truth table; [2]
• Boolean expressions for the outputs X, Y and Z; [3]
• the circuit diagram for the system. [4]

C B A X Y Z
0 0 0 0 0 0 .....................................................................................................................................

.....................................................................................................................................

.....................................................................................................................................

LSB
D C B A
Pulse
generator Counter
R

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9. (a) Digital data is transmitted to the head office of a bank from one of its branch offices via
an optical fibre link. Amplifiers X and Y are used to boost the signal amplitude.

Input power = 2.5 mW

Optical fibre Amp Y
Amp X

Input Input
25 km

Amplifiers X and Y both have a gain of +30 dB.

The optical fibre link has an attenuation of 2 dB km–1 and is 25 km long.

At the transmitter, the input power is 2.5 mW.

Calculate:

(i) the overall gain of the system in decibels; [2]

(ii) the output power in milliwatts; [2]

(b) The diagram shows the typical structure of an optical fibre cable.

(i) Identify the components labelled X and Y. [2]

X = . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Y = . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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(ii) The signal travels from amplifier X to amplifier Y using total internal reflection.
Describe two conditions necessary for this to occur in this fibre. [2]

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(c) The signal received at the output is converted back to an electrical signal, which is then
regenerated by a Schmitt trigger sub-system.

The following graph shows the characteristics for this Schmitt trigger.

Voltage / V

12

0 Voltage / V
– 12 –8 –4 0 4 8 12
–4

–8

– 12

(i) Design a Schmitt trigger circuit, based on a single op-amp, that has these
characteristics. [5]

Draw the circuit diagram for your design in the space below.

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(ii) Complete the second graph to show the effect of this Schmitt trigger on the signal
given in the first graph. [3]

Voltage / V

12

Test 0 Time
signal
–4

–8

– 12

Voltage / V

12

Resulting 0 Time
output
–4

–8

– 12

END OF PAPER

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