DEPARTMENT OF PHYSICS WITH COMPUTER APPLICATIONS

Subject Name: Electronics Sub. CODE: 138C1B

Unit I

2 Marks

1. What is the use of Boolean algebra?

 Digital Logic Design
 Telecommunications
 Computer Science
2. What is meant by combinational logic?
A combinational logic circuit is a circuit whose outputs only depend on the current state
of its inputs. These circuits realize Boolean functions and deal with digitized signals,
usually denoted by 0s and 1s.
3. Show that ( A +CB) =( A + B)( A +C)

(A + B)(A + C) = AA + AC + AB + BC Distributive law

= A + AC + AB + BC Rule 7: AA = A
= A( 1 + C) + AB + BC Rule 2: 1 + C = 1
= A. 1 + AB + BC Factoring (distributive law)
= A(1 + B) + BC Rule 2: 1 + B = 1
= A. 1 + BC Rule 4: A . 1 = A
= A + BC
4. How does Karnaugh map differ from the truth table?
A K-map can be thought of as a special version of a truth table that makes it easier to
map out parameter values and arrive at a simplified Boolean expression. A K-map is best
suited for Functions with two to four variables.
5. State De Morgan’s Laws.

𝐴 + 𝐵 = 𝐴. 𝐵
𝐴. 𝐵 = 𝐴 + 𝐵
 6. Distinguish between a half adder and a full adder.

S.No. Criteria Half Adder Full Adder

1 Basics The half adder has two inputs and The full adder has three inputs and one
one output output
2 Input There are two input operands in half There are three input operands in full
adder adder
3 Output The half adder produces the sum of The full adder produces the sum of the
the two input operands as its output three input operands as its output
4 Operation The half adder adds the two input The full adder adds the three input
operands and outputs their sum operands and outputs their sum
7. Give the truth table, Boolean expression and symbol for XOR gate.

5 Marks

1. What is a logic gate? With neat logic diagrams and truth tables, show that NAND
gate may be used as OR, NOR, EX-OR and EX-NOR logic gates.

A logic gate is a device that performs a Boolean function on binary inputs to produce a binary
output. The NAND gate is a logic gate that can be used to implement any Boolean function,
including OR, NOR, EX-OR, and EX-NOR. This is because the NAND gate is a combination of
an AND gate and a NOT gate, and is also known as a universal gate.

2. 𝒀 = 𝑨. 𝑩
3. OR Gate using NAND Gate

4. 𝒀=𝑨+𝑩
5. EX-OR Gate using NAND Gate

6.
7. Prove that (A + C) (AD + AD’) + AC + C = A + C and also show that A + CB = (A +
B) (A + C) using Boolean’s laws.

(A + B)(A + C) = AA + AC + AB + BC Distributive law

= A + AC + AB + BC Rule 7: AA = A
= A( 1 + C) + AB + BC Rule 2: 1 + C = 1
= A. 1 + AB + BC Factoring (distributive law)
= A(1 + B) + BC Rule 2: 1 + B = 1
= A. 1 + BC Rule 4: A . 1 = A
= A + BC
8. Obtain the sum-of products for the logic function f=(A+C+DC) (B+BC+D)
(A+C+DC) (B+BC+D) =( A+D(1+C))(C(1+B)+D)
= (A+D) (C+D)
= A.C+A.D+D.C+D.D
= AC+A.D+D.C+D
9. Discuss the function of half adder with suitable logic circuit.
 The half adder is a basic building block for more complex adder circuits such as full adders
and multiple-bit adders. It performs binary addition of two single-bit inputs, A and B, and
provides two outputs, SUM and CARRY.
The SUM output is the least significant bit (LSB) of the result, which is the XOR of the two
inputs A and B. The XOR gate implements the addition operation for binary digits, where a
“1” is generated in the SUM output only when one of the inputs is “1”.
The CARRY output is the most significant bit (MSB) of the result, indicating whether there
was a carry-over from the addition of the two inputs. The CARRY output is the AND of the
two inputs A and B. The AND gate generates a “1” in the CARRY output only when both
inputs are “1”.
Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic circuit
that adds two numbers and produces a sum bit (s) and carry bit (c) both as output. The addition
of 2 bits is done using a combination circuit called a Half adder. The input variables are augend
and addend bits and output variables are sum & carry bits. A and B are the two input bits.
let us consider two input bits A and B, then sum bit (s) is the X-OR of A and B. it is evident from
the function of a half adder that it requires one X-OR gate and one AND gate for its construction.
Truth Table

Here we perform two operations Sum and Carry, thus we need two K-maps one for each to
derive the expression.
Logical Expression
For Sum
Sum = A XOR B
For Carry

Carry = A AND B
Implementation

10. State and Prove De Morgan’s theorem.

There are two theorems -

De Morgan's First Theorem: -
Statement - The complement of a logical sum equals the logical product of the complements.
Logic equation -
𝐴 + 𝐵 = 𝐴. 𝐵
Proof -

De Morgan's Second Theorem: -

Statement - The complement of a logical product equals the logical sum of the complements.

Logic equation -
𝐴. 𝐵 = 𝐴 + 𝐵
Proof -

NAND gate is equivalent to bubbled OR gate.

Truth Table to prove De Morgan's Theorem:-

11. Explain the working of ripple counter.

Ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop drives
the clock input of the following flip-flop. The number of flip flops in the cascaded arrangement
depends upon the number of different logic states that it goes through before it repeats the sequence
a parameter known as the modulus of the counter. A n-bit ripple counter can count up to 2n states.
It is also known as MOD n counter. It is known as ripple counter because of the way the clock
pulse ripples its way through the flip-flops. Some of the features of ripple counter are:
 It is an asynchronous counter.
 Different flip-flops are used with a different clock pulse.
 All the flip-flops are used in toggle mode.
 Only one flip-flop is applied with an external clock pulse and another flip-flop clock is
obtained from the output of the previous flip-flop.
 The flip-flop applied with an external clock pulse act as LSB (Least Significant Bit) in the
counting sequence.
A counter may be an up counter that counts upwards or can be a down counter that counts
downwards or can do both i.e.count up as well as count downwards depending on the input control.
The sequence of counting usually gets repeated after a limit. When counting up, for the n-bit
counter the count sequence goes from 000, 001, 010, … 110, 111, 000, 001, … etc. When counting
down the count sequence goes in the opposite manner: 111, 110, … 010, 001, 000, 111, 110, …
etc.
A 3-bit Ripple counter using a JK flip-flop is as follows:

In the circuit shown in the above figure, Q0(LSB) will toggle for every clock pulse because JK
flip-flop works in toggle mode when both J and K are applied 1, 1, or high input. The following
counter will toggle when the previous one changes from 1 to 0.
Truth Table is as follows:

The 3-bit ripple counter used in the circuit above has eight different states, each one of which
represents a count value.

12. Draw the logic circuit for Y = ABC + AB’C and simplify the equation with Boolean
algebra and draw the simplified logic circuit.
Y=ABC+AB′CY=ABC+AB′C
=AC(B+B′)=AC(B+B′)
=AC(1)
 13. Explain how AND gate, OR gate and EXOR gate can be obtained from NOR logic
gate.

XOR(EX-OR) Gate from NOR

10 Marks

1. Describe the function of a Full Adder and obtain expressions for the SUM and the
CARRY output.
Full Adder is the adder which adds three inputs and produces two outputs. The first two
inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM. A full adder
logic is designed in such a manner that can take eight inputs together to create a byte-wide
adder and cascade the carry bit from one adder to the another.
Full Adder Truth Table:

CARRY = (A B)C+AB
 2. Show that NAND and NOR as universal logic gate.

A universal gate, such as a NOR gate and NAND gate, can perform any Boolean
function independently. This means these gates can form any logical Boolean expression on
their own, simplifying circuit design.
In practice, this is advantageous since NOR and NAND gates are economical and easier to
fabricate than other logic gates. So much so that an AND gate is typically implemented as a
NAND gate followed by an inverter (not the other way around)! Similarly, an OR gate is
typically realised as a NOR gate followed by an inverter.
NAND Gate As A Universal Gate

The below diagram is of a two-input NAND gate. The first part is an AND gate and the second
part is a dot after it represents a NOT gate.

In a NAND gate, the inputs initially pass through an AND gate. The output is then inverted,
resulting in the final output. Now we will look at the truth table of NAND gate.
We will consider the truth table of the above NAND gate i.e. a two-input NAND gate. The two
inputs are A and B.

Now we will see how this gate can be used to make other gates.
This is the circuit diagram of a NAND gate used to make work like a NOT gate, the original
logic gate diagram of NOT gate is given besides the circuit diagram below.

The above diagram is of an OR gate made from combinations of NAND gates, arranged in a
proper manner. The truth table of an OR gate is also given beside the diagram.
Now we will see the design of an AND gate from NAND gates.

The above diagram is of an AND gate made from NAND gate. So we can see that all the three
basic gates can be made by only using NAND gates, that’s why this gate is called Universal
Gate, and it is appropriate.
NOR Gate As A Universal Gate
Similar to the NAND gate, the NOR gate can also independently form the three basic gates:
AND, OR, and NOT.

The above diagram is of an OR gate made by only using NOR gates. The output of this gate is
exactly similar to that of a single OR gate. We can see the circuit arrangement of OR gate using,
NOR gate is similar to that of AND gate using NAND gates.
The above diagram as the name suggests is of AND gate using only NOR gate, again we can see
that the circuit diagram of AND gate using only NOR gate is exactly similar to that of OR gate
using only NAND gates. Now we will finally see how we can make a NOT gate by using only
NOR gates.

The above diagram is of a NOT gate made by using a NOR gate. The circuit diagram is similar
to that of NOT gate made by using only NAND gate. As demonstrated, the NOR gate alone can
configure AND, OR, and NOT gates, affirming its universal gate status.

3. Simplify the Boolean function using four variable Karnaugh map.

F (A, B, C, D) = Σ (3, 7, 11, 13, 14, 15)
 4. Explain the operation of (a) Half adder (b) Full adder circuit with the help of logic
diagram and truth table.
There are two types of Adder Circuits in Digital Electronics–
 Half Adders
 Full Adders
Half Adder
Half Adder is a digital circuit to calculate the arithmetic binary addition of two single-bit
numbers. It is a circuit with two inputs and two outputs.
For two single-bit binary numbers A and B, half adder produces two single-bit binary outputs S
and C, where S is the Sum and C is the carry.

The sum is for the least significant bit (LSB) and carry is for the most significant bit (MSB).

Operation and Truth Table for Half Adder

Operation:
Case 1: A= 0, B= 0;
According to Binary addition, the sum of these numbers is 0 with no carry bit generation.
0
+ 0
一一一一一
0
一一一一一
Hence, S= 0, C= 0
Case 2: A= 0, B= 1;
As per Binary addition, the sum of these numbers is 1 with no carry bit generation.
0
+ 1
一一一一一
 1
一一一一一
Hence, S= 1, C= 0
Case 3: A= 1, B= 0;
As per Binary addition, the sum of these numbers is 1 with no carry bit generation.
1
+ 0
一一一一一
1
一一一一一
Hence, S= 1, C= 0
Case 4: A= 1, B= 1;
According to Binary addition, the sum of these numbers is 1 with a carry bit generation of 1.
1
1
+ 1
一一一一一
0
一一一一一
Hence, S= 0, C= 1

Half Adder Truth Table:

A B Sum (S) Carry (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Designing Half Adder
With the help of the Truth Table, We can design a Karnaugh Map or K-Map for Half Adder to
obtain a Boolean Expression.

Karnaugh Map for Sum:

By solving this,
S= A’B + AB’

Karnaugh Map for Carry:

By looking at the K-map, We can conclude;

This Boolean expression helps us to design a half adder with an XOR Gate and AND gate.
Full Adder is the adder which adds three inputs and produces two outputs. The first two
inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM. A full adder
logic is designed in such a manner that can take eight inputs together to create a byte-wide
adder and cascade the carry bit from one adder to the another.

Full Adder Truth Table:

CARRY = (A B)C+AB
 Unit II

2 Marks

1. What do you mean by flip-flops?

The flip-flop is a circuit that maintains a state until directed by input to change the state.
A basic flip-flop can be constructed using four-NAND or four-NOR gates. Flip-flop is
popularly known as the basic digital memory circuit. It has its two states as logic 1(High)
and logic 0(low) states. A flip flop is a sequential circuit which consist of single binary
state of information or data.
2. What is meant by synchronous counter?
A Synchronous counter is the counter in which the clock input with all the flip-flops uses
the same source and produces the output at the same time.
3. What is meant by asynchronous counter?
The counters whose output doesn't depend on a single clock signal. There are different
clock signals provided to produce the output called Asynchronous Counters.
4. Why do we need sequential circuits?
Sequential circuits are digital circuits that store and use previous state information to
determine their next state. They are commonly used in digital systems to implement state
machines, timers, counters, and memory elements and are essential components in digital
systems design.
5. What is ring counter? Why is it called so?
A ring counter is a type of counter composed of flip-flops connected into a shift register,
with the output of the last flip-flop fed to the input of the first, making a "circular" or
"ring" structure.
6. How many flip-flops are needed for a mod-16 counter?
For a mod 16 counter, 16=2^4. So again 4 flip flops are required
7. What do you know about counter?
A counter is a device that stores and displays the number of times a specific event has
occurred. Counters are often used in digital circuits and are made up of flip-flops that
change state in response to pulses. Counters can be designed to count in different
sequences, such as from 0 to 10, 2 to 6, or 3 to 9
8. Draw the basic flip-flop circuit with NOR gates and write the truth table.
 9. Draw the circuit diagram of 4-bit binary synchronous counter, with D-flip-flop.

5 Marks

1. Explain the working principles of ring counter.

 A ring counter is a typical application of the Shift register. The ring counter is almost the
same as the shift counter. The only change is that the output of the last flip-flop is connected
to the input of the first flip-flop in the case of the ring counter but in the case of the shift
register it is taken as output. Except for this, all the other things are the same.

No. of states in Ring counter = No. of flip-flop used

So, for designing a 4-bit Ring counter we need 4 flip-flops.

In this diagram, we can see that the clock pulse (CLK) is applied to all the flip-flops
simultaneously. Therefore, it is a Synchronous Counter. Also, here we use Overriding input
(ORI) for each flip-flop. Preset (PR) and Clear (CLR) are used as ORI. When PR is 0, then the
output is 1. And when CLR is 0, then the output is 0. Both PR and CLR are active low signal that
always works in value 0.

PR = 0, Q = 1

CLR = 0, Q = 0

These two values are always fixed. They are independent of the value of input D and the Clock
pulse (CLK). Working – Here, ORI is connected to Preset (PR) in FF-0 and it is connected to
Clear (CLR) in FF-1, FF-2, and FF-3. Thus, output Q = 1 is generated at FF-0, and the rest of the
flip-flop generates output Q = 0. This output Q = 1 at FF-0 is known as Pre-set 1 which is used to
form the ring in the Ring Counter.
This Preseted 1 is generated by making ORI low and that time Clock (CLK) becomes don’t care.
After that ORI is made to high and apply low clock pulse signal as the Clock (CLK) is negative
edge triggered. After that, at each clock pulse, the preseted 1 is shifted to the next flip-flop and
thus forms a Ring. From the above table, we can say that there are 4 states in a 4-bit Ring
Counter.

4 states are:

1000

0100

0010

0001

In this way can design a 4-bit Ring Counter using four D flip-flops.

2. Explain the action of a D flip-flop.

D Flip Flop
D flip flop is an electronic device that is known as “delay flip flop” or “data flip flop” which
is used to store single bit of data. D flip flops are synchronous or asynchronous. The clock single
required for the synchronous version of D flip flops but not for the asynchronous one. The D flip
flop has two inputs, data and clock input which controls the flip flop. when clock input is high, the
data is transferred to the output of the flip flop and when the clock input is low, the output of the
flip flop is held in its previous state.
Working of D Flip Flop
D flip flop consist of a single input D and two outputs (Q and Q’). The basic working of D Flip
Flop is as follows:
 When the clock signal is low, the flip flop holds its current state and ignores the D input.
 When the clock signal is high, the flip flop samples and stores D input.
 The value that was previously fed into the D input is reflected at the flip flop’s Q output.
o If D = 0 then Q will be 0.
o If D = 1 then Q will be 1.
 The Q’ output of the flip flop is complemented by the Q output.
o If Q = 0 then Q’ will be 1.
o If Q = 1 then Q’ will be 0.
3. Difference between Synchronous and Asynchronous Counter.

S.No. Synchronous Counter Asynchronous Counter

In asynchronous counter main clock is only

In synchronous counter we use a applied to the first flip flop and then for rest of
universal clock that is common to all flip flops the output of previous flip flop is
1. flip flops throughout the circuit. taken as a clock.

Synchronous Counter is faster in

operation as compared to Asynchronous Counter is slower as compared
2. Asynchronous Counter. to synchronous counter in operation.
 Synchronous Counter does not Asynchronous Counter produces decoding
3. produce any decoding errors. error.

Synchronous Counter is also called Asynchronous Counter is also called Serial

4. Parallel Counter. Counter.

Synchronous Counter designing as

well implementation are complex due Asynchronous Counter designing as well as
5. to increasing the number of states. implementation is very easy.

Synchronous Counter will operate in Asynchronous Counter will operate only in

6. any desired count sequence. fixed count sequence (UP/DOWN).

Asynchronous Counter examples

Synchronous Counter examples are: Ripple UP counter, Ripple DOWN
7. are: Ring counter, Johnson counter. counter.

In synchronous counter, propagation In asynchronous counter, there is high

8. delay is less. propagation delay.

4. Draw the logic circuit for J.K. flip flop and explain its function.

Operations of J-K Flip Flop

Given Below is the Operations of J-K Flip Flop
 Case 1 (PR=CLR=0 ):This condition is in its invalid state.
 Case 2 (PR=0 and CLR=1): The PR is activated which means the output in the Q is set to 1.
Therefore, the flip flop is in the set state.
 Case 3 (PR=1 and CLR=0): The CLR is activated which means the output in the Q’ is set to
1. Therefore, the flip flop is in the reset state.
 Case 4 (PR=CLR=1): In this condition the flip flop works in its normal way whereas the PR
and CLR gets deactivated.
Race Around Condition in J-K Flip Flop
When the J and K both are set to 1, the input remains high for a longer duration of time, then the
output keeps on toggling. Toggle means that switching in the output instantly i.e. Q=0, Q’=1 will
immediately change to Q=1 and Q’=0 and this continuation keeps on changing. This change in
output leads to race around condition.
Characteristics Equation for JK Flip Flop
QN+1 = JQ’N + K’QN
10 Marks

1. Describe J-K Master-Slave flip-flop. (OR)

Explain the action of J-K Master-Slave flip-flop, giving truth table. What are its
advantages.

Operations of J-K Flip Flop

Given Below is the Operations of J-K Flip Flop
 Case 1 (PR=CLR=0 ):This condition is in its invalid state.
 Case 2 (PR=0 and CLR=1):The PR is activated which means the output in the Q is set to 1.
Therefore, the flip flop is in the set state.
 Case 3 (PR=1 and CLR=0): The CLR is activated which means the output in the Q’ is set to
1. Therefore, the flip flop is in the reset state.
 Case 4 (PR=CLR=1): In this condition the flip flop works in its normal way whereas the PR
and CLR gets deactivated.
Race Around Condition in J-K Flip Flop
When the J and K both are set to 1, the input remains high for a longer duration of time, then the
output keeps on toggling. Toggle means that switching in the output instantly i.e. Q=0, Q’=1 will
immediately change to Q=1 and Q’=0 and this continuation keeps on changing. This change in
output leads to race around condition.
Characteristics Equation for JK Flip Flop
QN+1 = JQ’N + K’QN
Applications of Flip-Flops
These are the various types of flip-flops being used in digital electronic circuits and the
applications of Flip-flops are as specified below.
 Counters: The Flip Flop are used in the Counter Circuits for Counting pulse or events.
 Frequency Dividers: The Flip Flop are used in Frequency Dividers to divide the frequency of
a input signal by a specific factor.
 Shift Registers: The Shift registers consist of interconnected flip-flops that shift data serially.
 Storage Registers: The Storage Resistor uses Flip Flop to store data in binary information.
 Bounce elimination switch: The Flip Flop are used in Bounce elimination switch to eliminate
the contact bounce.
 Data storage: The Flip Flop are used in the Data Storage to store binary data temporarily or
permanently.
 Data transfer: The Flip Flops are used for data transfer in different electronic parts.
 Latch: The Latches are the Sequential circuit which uses Flip Flop for temporary storage of
data
 Registers: The Registers are mode from the array of flip flop which are used to store data
temporarily.
 Memory: The Flip Flops are the main components in the memory unit for data storage.
2. Explain the 4 bit asynchronous ripple counter with necessary diagram and wave forms.
Ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop drives
the clock input of the following flip-flop. The number of flip flops in the cascaded arrangement
depends upon the number of different logic states that it goes through before it repeats the sequence
a parameter known as the modulus of the counter. A n-bit ripple counter can count up to 2n states.
It is also known as MOD n counter. It is known as ripple counter because of the way the clock
pulse ripples its way through the flip-flops. Some of the features of ripple counter are:
 It is an asynchronous counter.
 Different flip-flops are used with a different clock pulse.
 All the flip-flops are used in toggle mode.
 Only one flip-flop is applied with an external clock pulse and another flip-flop clock is
obtained from the output of the previous flip-flop.
 The flip-flop applied with an external clock pulse act as LSB (Least Significant Bit) in the
counting sequence.
A counter may be an up counter that counts upwards or can be a down counter that counts
downwards or can do both i.e.count up as well as count downwards depending on the input control.
The sequence of counting usually gets repeated after a limit. When counting up, for the n-bit
counter the count sequence goes from 000, 001, 010, … 110, 111, 000, 001, … etc. When counting
down the count sequence goes in the opposite manner: 111, 110, … 010, 001, 000, 111, 110, …
etc.
A 3-bit Ripple counter using a JK flip-flop is as follows:

In the circuit shown in the above figure, Q0(LSB) will toggle for every clock pulse because JK
flip-flop works in toggle mode when both J and K are applied 1, 1, or high input. The following
counter will toggle when the previous one changes from 1 to 0.
Truth Table is as follows:
The 3-bit ripple counter used in the circuit above has eight different states, each one of which
represents a count value. Similarly, a counter having n flip-flops can have a maximum of 2 to the
power n states. The number of states that a counter owns is known as its mod (modulo) number.
Hence a 3-bit counter is a mod-8 counter. A mod-n counter may also be described as a divide-by-
n counter. This is because the most significant flip-flop (the furthest flip-flop from the original
clock pulse) produces one pulse for every n pulses at the clock input of the least significant flip-
flop (the one triggers by the clock pulse). Thus, the above counter is an example of a divide-by-4
counter.
Timing diagram
Let us assume that the clock is negative edge triggered so the above the counter will act as an up
counter because the clock is negative edge triggered and output is taken from Q.

Counters are used very frequently to divide clock frequencies and their uses mainly involve digital
clocks and in multiplexing. The widely known example of the counter is parallel to serial data
conversion logic.
Advantages of Ripple Counter in Digital Logic
 Can be easily designed by T flip-flop or D flip-flop.
 Can be used in low speed circuits & divide by n-counters.
 Used as Truncated counters to design any mode number counters (i.e. Mod 4, Mod 3)
Disadvantages of Ripple Counter in Digital Logic
 Extra flip-flop is needed to do resynchronization.
 To count the sequence of truncated counters, additional feedback logic is needed.
 Propagation delay of asynchronous counters is very large, while counting the large number of
bits.
 Counting errors may occur due to propagation delay for high clock frequencies.