Basic Electronics [BBEE203]

Module - 2
BJT and FET

Syllabus:
Bipolar Junction Transistors: Introduction BJT Voltages & Currents, BJT Amplification,
Common Base Characteristics, Common Emitter Characteristics, Common Collector
Characteristics, BJT Biasing: Introduction, DC Load line and Bias point (Text 1: 4.2, 4.3,
4.5,4.6, 5.1)
Field Effect Transistor: Junction Field Effect Transistor, JFET Characteristics, MOSFETs:
Enhancement MOSFETs, Depletion Enhancement MOSFETs (Text 1: 9.1,9.2,9.5)

Bipolar Junction Transistor

Structure of pnp and npn transistor

 A bipolar transistor is simply a sandwich of one type of semiconductor material (p-type
or n-type) between two layers of the opposite type.
 An npn transistor has a p-type material between two layers of n-type as shown in fig.4.1.

Fig.2.1: npn transistor

 An pnp transistor has a n-type material between two layers of p-type as shown in fig.4.2.

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Fig.2.2: pnp transistor

 The BJT has three layers called base (B), emitter (E), collector (C) and it consists of
two pn-junctions: collector-base junction and emitter-base junction.
Emitter
a. The left hand side layer is Emitter.
b. It is moderate size and is heavily doped as its main function is to supply a
number of majority carriers, i.e. either electrons or holes.
c. As it emits electrons or holes, it is called as an Emitter.
d. This is simply indicated with the letter E.
Base
a. The middle layer is the Base.
b. This is thin and lightly doped.
c. Its main function is to pass the majority carriers from the emitter to the
collector.
d. This is indicated by the letter B.
Collector
a. The right side layer is Collector.
b. Its name implies its function of collecting the carriers.
c. This is a bit larger in size than emitter and base. It is moderately doped.
d. This is indicated by the letter C.
 Circuit symbols of pnp and npn transistor are shown in fig.4.3. The arrowhead identifies
the emitter terminal and indicates the direction of conventional current.

Transistor Biasing
 BJT has two pn junctions. One junction is between the emitter and base, that is called
as Emitter-Base junction and the other is between the collector and base, that is called
as Collector-Base junction.
 Biasing is controlling the operation of the transistor by providing power supply. The
function of both the PN junctions is controlled by providing bias to the circuit through
some dc supply. Fig.4.4. shows how a npn transistor or pnp transistor is biased.





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Fig.2.4: Biasing of pnp transistor and npn transistor

 By applying the power, the emitter base junction is always forward biased as the
emitter resistance is very small. The collector base junction is reverse biased and its
resistance is a bit higher.

Operation NPN Transistor

 The operation of an npn transistor is shown in the fig.4.5, in which emitter-base junction
is forward biased and collector-base junction is reverse biased.
 The voltage VEE provides a negative potential at the emitter which repels the electrons
in the n-type material and these electrons cross the emitter-base junction, to reach the
base region.
 There a very low percent of electrons recombine with free holes of P-region. This
provides very low current which constitutes the base current IB.
 The remaining holes cross the collector-base junction, to constitute the collector
current IC.

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Fig.2.5: npn operation

 As an electron reaches out of the collector terminal, and enters the positive terminal of
the battery, an electron from the negative terminal of the battery VEE enters the emitter
region. This flow slowly increases and the electron current flows through the transistor.
 Therefore
i. The conduction in a NPN transistor takes place through electrons.
ii. The collector current is higher than the emitter current.
iii. The increase or decrease in the emitter current affects the collector current.

Operation PNP Transistor

 The operation of an npn transistor is shown in the fig.4.6, in which emitter-base junction
is forward biased and collector-base junction is reverse biased.

Fig.2.6: pnp operation

 The voltage VEE provides a positive potential at the emitter which repels the holes in

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the P-type material and these holes cross the emitter-base junction, to reach the base
region.
 There a very low percent of holes recombine with free electrons of N-region. This
provides very low current which constitutes the base current IB.
 The remaining holes cross the collector-base junction, to constitute collector current IC,
which is the hole current.
 As a hole reaches the collector terminal, an electron from the battery negative terminal
fills the space in the collector. This flow slowly increases and the electron minority
current flows through the emitter, where each electron entering the positive terminal
of VEE, is replaced by a hole by moving towards the emitter junction. This constitutes
emitter current IE.
 Therefore
i. The conduction in a PNP transistor takes place through holes.
ii. The collector current is slightly less than the emitter current.
iii. The increase or decrease in the emitter current affects the collector current.

Transistor currents
 For a pnp transistor, emitter current IE flows into the transistor. The base current IB and
collector current IC, flows out of the transistor as shown in the fig.4.7.

Fig.2.7: Terminal currents of a pnp transistor

IE = IC + IB
 Almost all of emitter current IE crosses to collector and only a small portion flow out
of the base terminal.
IC = αdcIE
IC
αdc =
IE
where αdc is defined as the ratio of the collector current to emitter current or

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emitter to collector current gain.

 Collector current IC can also be expressed by using equations as
IC = αdc(IC + IB)
IC − αdcIC = αdcIB
IC(1 − αdc) = αdcIB
αdc
IC = IB
1−α
IC = βdcIB
IC αdc
βdc = =
IB 1 − αdc
where βdc is defined as the ratio of the collector current to base current or base
to collector current gain. βdc is also defined as hFE based on the h-parameter
analysis of a transistor.
 Terminal currents derived for a pnp device will apply for npn transistor, only difference
is IB and IC flows into transistor and IE flows out of the transistor as shown in the fig.4.8

Fig.2.8: Terminal currents of a npn transistor

Problems
1. Calculate IC and IE for a transistor that has αdc = 0.98 and IB = 100µA. determine
the value of βdc for the transistor.
Collector current is given by
IC = βdcIB
αdc
IC = IB
1−α
0.98
IC = ∗ 100μ
1 − 0.98
𝐈𝐂 = 𝟒. 𝟗𝐦𝐀
Emitter current is expressed as
IC = αdcIE
IC 4.98m
IE = =
αdc 0.98
𝐈𝐄 = 𝟓𝐦𝐀

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ratio of the collector current to base current is

IC αdc
βdc = =
IB 1 − αdc
0.98
βdc =
1 − 0.98
𝛃𝐝𝐜 = 𝟒𝟗

2. Calculate αdc and βdc for the transistor if IC = 1mA and IB = 25µA. Determine the
new base current to give IC = 5mA
Collector current is given by
IC = βdcIB
IC 1m
βdc = =
IB 25μ
𝛃𝐝𝐜 = 𝟒𝟎
Emitter current is given by
IE = IC + IB
IE = 1m + 25μ
𝐈𝐄 = 𝟏. 𝟎𝟐𝟓𝐦𝐀
ratio of the collector current to emitter current is
IC 1m
αdc = =
I E 1.025m
𝛂𝐝𝐜 = 𝟎. 𝟗𝟕𝟔
New base current is
IC = βdcIB
IC 5m
IB = =
βdc 40
𝐈𝐁 = 𝟏𝟐𝟓𝛍𝐀

3. A transistor has measured a currents of IC = 3mA and IE = 3.03mA. Calculate the

new current levels when the transistor is replaced with a device that has βdc = 75.
Assume that IB remains constant.
Emitter current is given by
IE = IC + IB
IB = 3.03m − 3m
𝐈𝐁 = 𝟑𝟎𝛍𝐀
New current levels for βdc = 75 are
IC = βdcIB
IC = 75 ∗ 30μ
𝐈𝐂 = 𝟐. 𝟐𝟓𝐦𝐀

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Emitter current is given by

IE = IC + IB
IE = 2.25m + 30μ
𝐈𝐄 = 𝟐. 𝟐𝟖𝐦𝐀

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Common Emitter Characteristics

Common emitter circuit
 Fig.4.9 shows the npn transistor with common emitter configuration. The input is applied
between base-emitter terminal and output is measured between collector- emitter terminal.
 Since emitter terminal is used for both input and output, the emitter terminal is called as
common terminal and the configuration is called as common emitter configuration.
 Ammeters and voltmeters are used to measure the current and voltage at input and output
terminals in the circuit.

Fig.2.9: npn transistor in Common-Emitter configuration

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Common emitter input characteristics

 For input characteristics the output voltage VCE is kept constant and input voltage VBE
is varied.
 At each input voltage VBE, the input current IB is measured.
 The input voltage VBE and the input current IB is plotted to obtain the input
characteristics as shown in the fig.4.10.

Fig.2.10: Input characteristics

 Since emitter-base junction is forward biased the input characteristics is similar to pn-
junction diode.
 When output voltage VCE is increased the collector-base junction increases and more
charge carries from the emitter flows across the collector-base junction into collector,
and few flow out through the base terminal.
 Hence for the given value of input voltage VBE, the input current IB is reduced when
output voltage VCE is increased.
Common emitter output characteristics
 For output characteristics the input current IB is kept constant and output voltage VCE
is varied.
 At each output voltage VCE, the output current IC is measured.
 The output voltage VCE and the output current IC is plotted to obtain the output
characteristics as shown in the fig.4.11.

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 Since VCE is used for representation, the horizontal axis is shown with negative values.
The common base output characteristics shows that the output current IC is almost equal
to IE and output current IC remains constant when output voltage VCB is increased. This
is because of reverse biased collector-base junction.

Fig.2.11: Output characteristics

 When the output voltage VCB is reduced to zero, output current IC still flows since the
collector-base junction assist the flow of minority charge carriers.
 To stop the flow of flow of minority charge carriers the collector-base junction has to
be forward bias.
 Therefore IC is reduced to zero when output voltage VCB is increased positively.
 The region in which collector-base junction is forward biased is known as saturation
region.
 The region in which collector-base junction is reverse biased is known as active region.
 If a reverse bias voltage is applied to the collector-base junction, then the junction
breakdown occurs and current increases.
JFET (Junction Field-Effect Transistor)

 The JFET (junction field-effect transistor) is a type of FET that operates with a
reverse-biased pn junction to control current in a channel.
 Depending on their structure, JFETs can be classified into two type
i. n-channel JFET

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ii. p-channel JFET

Structure of n-channel JFET
 Fig.2.1 shows the basic structure of an n-channel JFET (junction field-effect transistor).
Wire leads are connected to each end of the n-channel forms the drain and source
terminals; the drain is at the upper end, and the source is at the lower end.
 Two p-type regions are diffused in the n-type material to form a channel, and both p-
type regions are connected to form the gate terminal.
 The source and the drain terminals are of n-type while the gate is of p-type. Due to this,
two pn junctions will be formed within the device.

Fig.2.12: n-channel JFET

Operation of n-channel JFET
 In n-channel JFET, the majority charge carriers will be the electrons as the channel
formed in-between the source and the drain is of n-type. The working of these devices
depends upon the voltages applied at its terminals.
 VDD provides a drain-to-source voltage and supplies current from drain to source. VGG
provides a gate-to-source voltage and creates the reverse-bias voltage between the gate
and the source, as shown in the fig.2.2.
 Positive terminal of dc bias voltage VDD is connected to drain and negative terminal to
source.
 Positive terminal of dc bias voltage VGG is connected to source and negative terminal
to gate.

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Fig.2.13: n-channel JFET with VGS = 0 and VDS = 0

Case I: VGS = 0 and VDS = 0

 When no voltage is applied to the device i.e. VGS = 0 and VDS = 0, the device will be
idle and no current flows through it i.e. IDS = 0 as shown in the fig2.2.
Case II: VGS = 0 and VDS = +ve
 Consider that the drain terminal of the device is connected to the positive terminal of
the battery while its negative is connected to the source i.e. VDS = +ve. However, let
the gate terminal remain at unbiased state, which means VGS = 0.
 The electrons within the n-substrate of the device start moving towards the drain as
electrons are attracted by the positive VDS. At the same time, the electron will also be
repelled from the source as it is connected to the negative terminal of the voltage supply.
 This results in a current flow from drain to source whose value is restricted by the
resistance offered to it by the channel.
 Suppose the point at source terminal is B and the point at drain terminal is A, then the
resistance of the channel will be such that the voltage drop at the terminal A is greater
than the voltage drop at the terminal B i.e.VA > VB
 Hence the voltage drop is being progressive through the length of the channel. So, the
reverse biasing effect is stronger at drain terminal than at the source terminal. Therefore,
the depletion layer tends to penetrate more into the channel at point A than at point B,
when both VGG and VDD are applied as shown in the fig.2.3.

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Fig.2.14: n-channel JFET when VGS = 0V and VDS = +ve

 When this drain voltage is further increased, a stage occurs where both the depletion
layer's touch each other, and prevent the current ID flow as shown in the fig.2.4
 The voltage at which both these depletion layers literally “touch” is called as “Pinch
off voltage”. It is indicated as VP. The drain current ID becomes essentially constant.
Hence the drain current is a function of reverse bias voltage at gate.

Fig.2.15: n-channel JFET when VGS = 0V and VDS = VP

Case III: VGS = -ve and VDS = +ve
 Consider the gate terminal is negative w.r.t source i.e. VGS = -ve while VDS is +ve.
Here the n-channel JFET behaves in a very-similar way to that in Case II, but for a
lower value of VDS. This means that the pinch-off and the saturation occur quite earlier
and are decided by the negative potential applied at the gate terminal
Output characteristics
 When the voltage between gate and source VGS is zero, the current ID from source to

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drain is also zero as there is no VDS applied.

 As the voltage between drain and source VDS is increased, the current flow ID from
source to drain increases. This increase in current is linear up to a certain point A,
known as Knee Voltage.
 The gate terminals will be under reverse biased condition and as ID increases, the
depletion regions tend to constrict. This constriction is unequal in length making these
regions come closer at drain and farther at drain, which leads to pinch off voltage. The
pinch off voltage is defined as the minimum drain to source voltage where the drain
current approaches a constant value saturation value. The point at which this pinch off
voltage occurs is called as Pinch off point, denoted as B.
 As VDS is further increased, the channel resistance also increases in such a way
that ID practically remains constant. The region BC is known as saturation region or
amplifier region. All these along with the points A, B and C are plotted in the graph
below.

 The drain characteristics are plotted for drain current ID against drain source
voltage VDS for different values of gate source voltage VGS. The overall drain
characteristics for various input voltages are shown in the fig.2.5.

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Fig.2.16: Drain characteristics of n-channel JFET

Structure of p-channel JFET

 Fig.2.6 shows the basic structure of an p-channel JFET (junction field-effect transistor).
Wire leads are connected to each end of the p-channel forms the drain and source
terminals; the drain is at the upper end, and the source is at the lower end.

Fig.2.17: p-channel JFET

 Two n-type regions are diffused in the p-type material to form a channel, and both n-
type regions are connected to form the gate terminal.
 The source and the drain terminals are of p-type while the gate is of n-type. Due to this,

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two pn junctions will be formed within the device.

Operation of p-channel JFET
 In p-channel JFET, the majority charge carriers will be the holes as the channel formed
in-between the source and the drain is of p-type. The working of these devices depends
upon the voltages applied at its terminals.
 VDD provides a drain-to-source voltage and supplies current from source to drain. VGG
provides a gate-to-source voltage and creates the reverse-bias voltage between the gate
and the source, as shown in the fig.2.7.
 Positive terminal of dc bias voltage VDD is connected to source and negative terminal
to drain.
 Positive terminal of dc bias voltage VGG is connected to gate and negative terminal to
source.
Case I: VGS = 0 and VDS = 0
 When no voltage is applied to the device i.e. VGS = 0 and VDS = 0, the device will be
idle and no current flows through it i.e. IDS = 0 as shown in the fig2.7.

Fig.2.18: n-channel JFET with VGS = 0 and VDS = 0

Case II: VGS = 0 and VDS = -ve
 Consider that the drain terminal of the device is connected to the negative terminal of
the battery while its positive is connected to the source i.e. VDS = -ve. However, let the
gate terminal remain at unbiased state, which means VGS = 0.
 The holes within the p-substrate of the device start moving towards the drain as holes
are attracted by the negative VDS. At the same time, the holes will also be repelled from
the source as it is connected to the positive terminal of the voltage supply.
 The electrons move from drain to source terminal. This results in a current flow from

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source to drain whose value is restricted by the resistance offered to it by the channel.
 Suppose the point at source terminal is B and the point at drain terminal is A, then the
resistance of the channel will be such that the voltage drop at the terminal A is greater
than the voltage drop at the terminal B i.e.VA > VB
 Hence the voltage drop is being progressive through the length of the channel. So, the
reverse biasing effect is stronger at drain terminal than at the source terminal. Therefore,
the depletion layer tends to penetrate more into the channel at point A than at point B,
when both VGG and VDD are applied as shown in the fig.2.8.

Fig.2.19: p-channel JFET when VGS = 0V and VDS = -ve

 When this drain voltage is further decreased, a stage occurs where both the depletion
layers touch each other, and prevent the current ID flow as shown in the fig.2.9.
 The voltage at which both these depletion layers literally “touch” is called as “Pinch
off voltage”. It is indicated as VP. The drain current ID becomes essentially constant.
Hence the drain current is a function of reverse bias voltage at gate.

Fig.2.20: p-channel JFET when VGS = 0V and VDS = VP

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Case III: VGS = +ve and VDS = -ve

 Consider the gate terminal is positive w.r.t source i.e. VGS = +ve while VDS is -ve. Here
the n-channel JFET behaves in a very-similar way to that in Case II, but for a lower
value of VDS. This means that the pinch-off and the saturation occur quite earlier and
are decided by the positive potential applied at the gate terminal.
Output characteristics
 When the voltage between gate and source VGS is zero, the current ID from source to
drain is also zero as there is no VDS applied.
 As the voltage between drain and source VDS is increased, the current flow ID from
source to drain increases. This increase in current is linear up to a certain point A,
known as Knee Voltage.

 The gate terminals will be under reverse biased condition and as ID increases, the
depletion regions tend to constrict. This constriction is unequal in length making these
regions come closer at drain and farther at drain, which leads to pinch off voltage. The
pinch off voltage is defined as the minimum drain to source voltage where the drain
current approaches a constant value saturation value. The point at which this pinch off
voltage occurs is called as Pinch off point, denoted as B.
 As VDS is further increased, the channel resistance also increases in such a way
that ID practically remains constant. The region BC is known as saturation region or
amplifier region. All these along with the points A, B and C are plotted in the graph
below.

 The drain characteristics are plotted for drain current ID against drain source
voltage VDS for different values of gate source voltage VGS. The overall drain

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Characteristics for various input voltages are shown in the fig.2.10.

Fig.2.21: Drain characteristics of p-channel JFET

MOSFET
 The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor is a
semiconductor device which is widely used for switching and amplifying electronic
signals in the electronic devices.
 The MOSFET is a four terminal device with source (S), gate (G), drain (D) and body
(B) terminals. The body of the MOSFET is frequently connected to the source terminal
so making it a three terminal device like field effect transistor.
 The MOSFET is very far the most common transistor and can be used in both analog
and digital circuits.
 The MOSFET can function in two ways
i. Depletion Mode: When there is no voltage on the gate, the channel shows its
maximum conductance.
ii. Enhancement Mode: When there is no voltage on the gate the device does not
conduct

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Structure of nMOS enhancement transistor

 nMOS enhancement transistor as shown in the fig.2.11 consists of lightly doped p-
substrate.
 Two highly doped n-type regions are formed in the p-substrate by diffusing n-
impurities. These regions forms the source and drain terminal of the transistor.

Fig.2.22: Structure of nMOS enhancement transistor

 A thin layer of silicon dioxide (SiO2) is grown on the surface of the substrate which
acts as an excellent insulator.
 A polysilicon gate is deposited above the substrate and is separated from the substrate
by an oxide layer.
 Metal contacts are made for gate (G), source (S), drain (D) and substrate (B) regions.
 Substrate (also known as body) region forms pn junctions with source and drain region
and these pn junctions are reverse biased.

Operation of nMOS enhancement transistor

 For transistor operation a channel should be established between source and drain for
the conduction of the majority carries.
 To form a channel a positive gate voltage should be applied with respect to source (i.e.
gate to source voltage Vgs).
 When a positive gate voltage (Vgs) is applied, an electric field is established between
the gate and the substrate which helps for the inversion of the charges at the gate-
substrate interface.

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 The holes repel from the interface of gate-substrate region and the electrons from the
n+ source and n+ drain region gets attracted towards the interface of gate-substrate
region.

Fig.2.23: Cutoff region of nMOS transistor

 When sufficient number of electrons accumulates in interface of gate-substrate region,
an n-region will be formed between n+ source and n+ drain which acts as a channel for
the current conduction between drain and source.
 The channel is created by inverting the interface of gate-substrate region from p-type
to n-type. Hence this induced channel is also called as an inversion layer.
 The amount of gate voltage which is required to create a conducting channel between
n+ source and n+ drain is called threshold voltage (Vt).
 Hence the region of operation in which the gate to source voltage (Vgs) is less than
threshold voltage (Vt) is known as cutoff region as shown in fig.2.12 where the MOS
transistor is in off state.
 Now keep the gate to source voltage (Vgs) constant and apply a small amount of positive
voltage to drain with respect source (Vds). An electric field is established between the
drain and the source, acting towards source terminal which supplies energy to the
electrons present at the source.
 The electrons move towards drain, which causes a small amount of current Id to flow
in the channel.
 The current Id will flow from drain to source which is opposite to the flow of electrons.
 The magnitude of current Id depends on the density of electrons in the channel which
in turn depends on the magnitude of Vgs.

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 The current Id will increase if magnitude of Vgs is increased above Vt, This voltage is
called as excess gate voltage (Vgs - Vt) also called as overdrive voltage (VOV).
 The voltage Vds appears as a voltage drop across the length of the channel.
 The voltage between the gate and the points along the channel decreases from Vgs at
the source end to Vgs – Vds at the drain end.
 Since the channel depth depends on this voltage, we find that the channel is no longer
of uniform depth; rather, the channel will take the tapered form.
 As Vds is increased further, the channel becomes more tapered and its resistance
increases correspondingly.

Fig.2.24: Linear region of nMOS transistor

Thus the Id - Vds curve does not continue as a straight line but bends eventually as shown
in fig.2.15.

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Fig.2.14: Saturation region of nMOS transistor

Fig.2.25: Id - Vds characteristics of nMOS with regions of operations

 When Vds is increased further it reduces the voltage between gate and channel at the
drain end to Vt, i.e, Vgd = Vt, or Vgs – Vds = Vt or Vds = Vgs - Vt, the channel depth at
the drain end decreases to almost zero, and the channel is now said to be pinched off.
 Increasing Vds further shifts the pinch-off point towards the source region, and the
current through the channel remains constant at the value obtained for Vds = Vgs - Vt.
 The drain current thus saturates at this value, and the MOSFET is said to have entered
the saturation region of operation.
 The voltage Vds at which saturation occurs is denoted Vdssat and Vdssat = Vgs - Vt.

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 The device operates in the saturation region if Vds ≥ Vdssat as shown in the fig.2.14
and the device operates in linear region (triode region) if Vds < Vdssat as shown in
the fig.2.13.

Structure of pMOS enhancement transistor

 pMOS enhancement transistor is as shown in the fig.2.16 which consists of lightly
doped n-substrate.
 Two highly doped p-type regions are formed in the n-substrate by diffusing p-
impurities. These regions forms the source and drain terminal of the transistor.
 A thin layer of silicon dioxide (SiO2) is grown on the surface of the substrate which
acts as an excellent insulator.
 A polysilicon gate is deposited above the substrate and is separated from the substrate
by an oxide layer.
 Metal contacts are made for gate (G), source (S), drain (D) and substrate (B) regions.
 Substrate (also known as body) region forms pn junctions with source and drain region
and these pn junctions are reverse biased.

Fig.2.26: Structure of pMOS enhancement transistor

Operation of pMOS enhancement transistor

 For an enhancement mode operation, the majority carries should be enhanced first for
the conduction to take place.
 A channel should be established between source and drain for the conduction to take
place.

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 To form a channel a negative gate voltage should be applied with respect to source (i.e.
gate to source voltage Vgs).
 When a negative gate voltage (Vgs) with source connected to ground is applied, an
electric field is established between the gate and the substrate. The vertical component
of the electric field helps for the inversion of the charges at the gate-substrate interface.
 The electrons repel from the interface of gate-substrate region and the holes from the
p+ source and p+ drain region gets attracted towards the interface of gate-substrate
region.
 When sufficient number of holes accumulates at the interface of gate-substrate region,
a p-region will be formed between p+ source and p+ drain which acts as a channel for
the current conduction from drain to source.
 The channel is created by inverting the interface of gate-substrate region from n-type
to p-type. Hence this induced channel is also called as an inversion layer.
 The amount of gate voltage which is required to create a conducting channel between
p+ source and p+ drain is called threshold voltage (Vt).

Fig.2.27: Cutoff region of pMOS transistor

 Hence the region of operation in which the gate to source voltage (Vgs) is greater
than threshold voltage (Vt) is known as cutoff region as shown in fig2.17 where the
MOS transistor is in off state.
 Now keep the gate to source voltage (Vgs) constant and apply a small amount of
negative voltage to drain with respect source (Vds). An electric field is established
between the drain and the source, acting towards source terminal which supplies energy
to the holes present in the source.

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 The holes move towards drain, which causes a small amount of current Id to flow in the
channel.
 The current Id will flow from source to drain which is opposite to the flow of electrons.
 The magnitude of current Id depends on the density of electrons in the channel which
in turn depends on the magnitude of Vgs.
 The current Id will decrease if magnitude of Vgs is decreased below Vt, This voltage is
called as excess gate voltage (Vgs - Vt), also called as overdrive voltage (Vov).
 When Vgs is decreased below Vt, it enhances the channel, hence it is called as
enhancement mode transistor. The conductance of the channel is proportional to the
excess gate voltage (Vgs - Vt).
 The voltage Vds appears as a voltage drop across the length of the channel. The voltage
between the gate and the points along the channel increases from Vgs at the source end
to Vgs - Vds at the drain end.
 Since the channel depth depends on this voltage, we find that the channel is no longer
of uniform depth; rather, the channel will take the tapered form.
 As Vds is decreased further, the channel becomes more tapered and its resistance
increases correspondingly.
 Thus the Id - Vds curve does not continue as a straight line but bends eventually as shown
in fig.2.20, when Vds is decreased to the value which reduces the voltage between gate
and channel at the drain end to Vt, i.e, Vgd = Vt, or Vgs - Vds = Vt or Vds = Vgs - Vt
 The channel depth at the drain end decreases to almost zero, and the channel is said to
be pinched off.
 Decreasing Vds further shifts the pinch-off point towards the source region, and the
current through the channel remains constant at the value obtained for Vds = Vgs - Vt.

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Fig.2.28: Linear region of pMOS transistor

 The drain current thus saturates at this value, and the MOSFET is said to have entered
the saturation region of operation.
 The voltage Vds at which saturation occurs is denoted Vdssat and Vdssat = Vgs - Vt.
 The device operates in the saturation region if Vds ≤ Vdssat as shown in the fig.2.19
and it operates in linear region (triode region) if Vds > Vdssat as shown in the
fig.2.18.

Fig.2.29: Saturation region of pMOS transistor

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Fig.2.30: Id – Vds characteristics of pMOS with regions of operations

Depletion-mode MOSFET
 The Depletion-mode MOSFET, which is less common than the enhancement mode
types are normally switched “ON” (conducting) without the application of a gate bias
voltage. That is the channel conducts when VGS = 0 making it a “normally-closed”
device.
Depletion nMOS transistor
 For the n-channel depletion MOS transistor, a negative gate-source voltage, -VGS will
deplete (hence its name) the conductive channel of its free electrons switching the
transistor “OFF”.
 For an n-channel depletion mode MOSFET: +VGS means more electrons and more
current. While a -VGS means less electrons and less current.

Fig.2.31: Structure of depletion nMOS

 When a positive voltage is applied to the gate terminal more electrons is attracted into
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the channel and on applying positive VDS more current to flow from the drain to source.
 When a negative voltage is applied to the gate terminal the electrons gets repelled
towards the substrate and combines with the holes resulting in the depletion of the
majority charge carriers in the channel and so there will be a reduction in the drain
current.
 At a particular negative voltage, the drain current becomes zero. This voltage is called
as pinch off voltage.

Fig.2.32: Id – Vds characteristics of depletion nMOS with regions of operations

Depletion pMOS transistor

 For p-channel depletion MOS transistor a positive gate-source voltage, +VGS will
deplete the channel of its free holes turning it “OFF”.

Fig.2.33: Structure of depletion pMOS

 For an p-channel depletion mode MOSFET: +VGS means less electrons and less
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current. While a -VGS means more electrons and more current.

Fig.2.35: Id – Vds characteristics of depletion pMOS with regions of operations

 When a negative voltage is applied to the gate terminal more holes is attracted into the
channel and on applying negative VDS more current to flow from the drain to source.
 When a positive voltage is applied to the gate terminal the holes gets repelled towards
the substrate and combines with the electrons resulting in the depletion of the majority
charge carriers in the channel and so there will be a reduction in the drain current.
 At a particular negative voltage, the drain current becomes zero. This voltage is called
as pinch off voltage.
MOSFET Symbol

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Problems:

1. For Enhancement type MOSFET (E-MOSFET), determine value of ID, if ID(ON) =

4mA, VGS(ON) = 6V, VT = 4V and VGS = 8V.
The current in EMOSFET is given by
ID = k(VGS − VT)2
where constant k is given by
ID(ON)
k= 2
(VGS(ON) − VT)
On substituting the values
4 ∗ 10−3
k= = 1 ∗ 10−3A/V2
(6 − 4)2
ID = 1 ∗ 10−3(8 − 4)2
ID = 16mA

2. For Depletion type MOSFET (D-MOSFET), ID = 10mA at VGS = -1V. Determine

VP if IDSS = 15mA
The current in DMOSFET is given by
VGS 2
ID = IDSS (1 − )
VP
On substituting the values
1 2
10m = 15m (1 + )
VP
VP = −5.5V

3. An n-channel JFET has an IDSS = 8mA, VP = -4V. Determine ID for VGS = -1V and
VGS = -2V
The current in JFET is given by
VGS 2
ID = IDSS (1 − )
VP
On substituting the values
At VGS = -1V

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−1 2
ID = 8 (1 − ) = 4.5mA
−4
At VGS = -2V
−2 2
ID = 8 (1 − ) = 2mA
−4

4. For a JFET IDSS = 9mA and VGS(off) = -8V Determine ID for VGS = -4V
The current in JFET is given by
VGS 2
ID = IDSS (1 − )
VP
On substituting the values
At VGS = -4V
−4 2
ID = 8 (1 − ) = 2mA
−8

5. An n-channel JFET has an IDSS = 8mA, VP = -5V. Determine ID for VGS = -3V and
VGS at ID = 3mA
The current in JFET is given by
VGS 2
ID = IDSS (1 − )
VP
On substituting the values
At VGS = -3V
−3 2
ID = 8 (1 − ) = 1.28mA
−5
At ID = 3mA
𝑉𝐺𝑆 2
3 = 8 (1 − )
−4

VGS = -1.55mA

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Question bank

1. Explain the characteristics of N-channel JFET.

2. Explain the construction and operation of P-channel JFET with necessary diagram.
3. With neat diagram, explain the characteristics of an enhancement type MOSFET.
4. Explain the construction and working of P-channel enhancement type MOSFET.
5. What is MOSFET? Explain D- MOSFET and E- MOSFET transfer characteristics.

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