Introduction to VLSI

Instructor: Yu-Te Liao

National Chiao Tung University

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 Introduction
• Instructor: Yu-Te Liao (廖育德)
• Office: 工程五館 769
• Email: yudoliao@g2.nctu.edu.tw
• Lecture time: 15:30-16:20 Monday and 15:30-
17:20 Thursday
• Office hours: 11a-noon Thursday
• TAs: 蔡瑞翔、郭鎮億 (工程五館615A)

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 Textbooks
Textbook:

1. Digital Integrated Circuits: A Design Perspective.

Jan M. Rabaey, Anantha Chandrakasan, Borivoje
Nikolic, Prentice Hall 2003.
Reference textbooks:

1. CMOS VLSI Design: A Circuits and Systems Perspective

Neil H.E. Weste and David Harris, Addison Wesley, 2005

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 Course goals
• Learn to design and analyze state-of-the-art
VLSI designs using CMOS technology
• Understand design issues from the device,
transistor, logic and system levels
• Learn complete digital IC design flow
– Full custom design
– Cell based design
• Ability of digital integrated circuit design,
simulation, layout, and verification
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 Requirements
• Obey the classroom rules
• No late report and homework are accepted
• Active participation in TA sessions and office
hours
• No makeup exam
• Cheating in the exam immediately disqualifies
you from the class
• Team work

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 Lecture schedule
Week 1 Introduction to VLSI design (9/12)
Week 2 Fundamentals of MOS devices (9/19)
IC fabrication, layout, tooling (9/22)
Week 3 IC design flow (9/26) (9/29)
HSPICE
Week 4 Inverter design (10/3) (10/6)
Week 5 Wire interconnection (10/13)
Week 6 Digital design performance estimation (10/17, 10/20)
Week 7 Combinational Logics (10/24, 10/27)
Week 8 Dynamic logics (10/31, 11/3)
Week 9 Midterm (11/10)
Week 10 Sequential logic design (11/14,11/17)
Week 11 Timing analysis (11/21, 11/24)
Week 12 Arithmetic circuits (11/28, 12/1)
Week 13 Arithmetic circuits (12/5, 12/8)
Week 14 Storage elements (12/12,12/15)
Week 15 Memory design (12/19,12/22)
Week 16 Memory design (12/26, 12/29)
Week 17 Advanced layout techniques (1/5)
Week 18 Final Exam (1/12) 6
 Lecture
• PPT will be uploaded to the website every
Sunday
• IEEE VLSI-related papers
• Office hours: Thurs. 11a-noon
– Solve questions
– Project discussion
– Teaching enhancement

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 Grading
• Homework: 30%, midterm exam: 30%, final
exam: 40%
• Exam Contents: concepts + simple calculation
• Homework will be assigned every Thursday
• Homework should be turned in before lecture
on the following Thursday (no late homework)
• Homework includes basic knowledge of
circuits, simple calculation, and paper reading
assignments.

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 When and Who?
• 什麼時候會需要電路設計?
– 任何有用到電的部分都需要電路!!
– 未來DNA運算、量子科學、神經系統也都需要
電路

• 什麼人適合學電路設計?
– 不夠聰明但夠努力的人!!
– 喜歡創新的人

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 Before the class
• much of what I stumbled into by following my
curiosity and intuition turned out to be
priceless later on.
• you can’t connect the dots looking forward;
you can only connect them looking backwards
• 努力過必留痕跡 !!

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Questions?

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 Outline
• What is VLSI?
• IC development in the industry and academy
• History of VLSI design
• Design flow
• Digital IC design metrics

(Chapter 1)

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 What is VLSI?
• Very Large Scale Integration (VLSI)
– The process of combining thousands of transistors
in a single chip

Layout

Wafer
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Core computing will need to increase

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Revenue of IC industries

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Main players in IC design industry

聯發科

聯詠
晨星
瑞昱
奇景

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2013 Top Fabless IC Suppliers

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 2015 top Taiwan IC Company
排名 公司 英文名稱 營業額（億元新台幣）
1 聯發科技 MediaTek 2132
2 聯詠科技 Novatek 508
3 瑞昱半導體 Realtek 317
4 奇景光電 Himax 228
5 立錡科技 Richtek 126
6 榮慧科技 Silicon Motion 119
7 敦泰電子 FocalTech 114
8 晶豪科技 Elite 92
9 矽創電子 Sitronix 92
10 凌陽科技 Sunplus 84
11 創意電子 Global Unichip 77
12 鈺創科技 Etron 74
13 瑞鼎科技 Rad 72
14 義隆電子 Elan 66
15 智原科技 Faraday 65
16 威盛電子 VIA 47
17 原相科技 PixArt 43
18 盛群電子 Holtek 39
19 揚智科技 Alitech 36
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20 致新科技 GMT 34
 Major IC design conference
• IEEE society: Solid state society, circuit and
system society, microwave theory and technique
society, etc.
• International Solid-state circuits conference
(ISSCC)
• VLSI symposia conference
• Custom integrated circuits conference (CICC)
• Radio frequency integrated circuit conference
(RFIC)
• Asian solid state circuits conference (ASSCC)
• Europe solid state circuits conference (ESCIRC)

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 Overview of VLSI history
• 1926--- Lilienfeld invented Field Effect
Transistor (FET) (patent)
• 1947--- First transistor (Bipolar junction
transistor (BJT)) invented at Bell Lab (1956
Nobel prize: Bratain, Bardeen, Schockley)
• 1957--- First IC developed by Jack Kilby at TI
(Nobel prize 2000)
• 1959--- Robert Noyce (Intel cofounder)
developed a IC fabrication technology
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 First computer
• The first computer(mechanics)

The Babbage
Difference Engine
(1832)
25,000 parts
cost: ? 7,470

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 The ENIAC computer (1946)
• Contained 17,468 vacuum tubes, along with 70,000 resistors,
10,000 capacitors, 1,500 relays, 6,000 manual switches and 5
million soldered joints.
• It covered 1800 square feet (167 square meters) of floor space,
weighed 30 tons, consumed 160 kilowatts of electrical power.

Vacuum tube
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 “Modern” Computer
• The first DRAM available in 1970 (Intel)
• The first microprocessor in a single chip (1971)
(Intel)

Process: 10µm
Transistor counts: 2300
Speed: 740 kHz
Cost (last time): $1425 (USD)
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 Trends in IC design
• Small size, complex function, and low power

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 Moore’s law
• Moore’s Law (Gordon Moore, Intel Cofounder):
The number of transistors on an IC doubles
approximately every two years.

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 Moore’s law in action

Source: Intel
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Cost reduction due to transistor scaling

Source: WSTS/Dataquest/Intel 27
Potential energy savings by Moore’s law

Courtesy Dr. Mark Stettler, Intel 28

 Challenges of VLSI design
• Advanced device model: models in textbooks
may not be correct
• Complexity: now >1 million transistors in a
mm2 and multiply functions of a chip
• Low power: leakage, device and architecture
choice, etc.
• High integration: noise coupling, layout
placement

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Custom IC design flow

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Design abstraction levels in digital circuits
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

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 Design Metrics
• How to evaluate performance of a digital circuit
(gate, block, …)?
– Cost
– Reliability
– Scalability
– Speed (delay, operating frequency)
– Power dissipation
– Energy to perform a function
• Design Issues:
– Signal integrity /noise
– Timing
– Energy/power consumption

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 Noise in electrical circuits
• Noise is a random fluctuation in electric
signals

Analog design:
noise determines the minimum useful
signal level.
Digital design:
noise can cause the logic level errors
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Reliability-noise in digital circuit design
• Noise Coupling from wires, substrate, power
supply, etc.

v ( t) V DD
i ( t)

Inductive coupling Capacitive coupling Power and ground

noise

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Voltage transfer characteristic (VTC)
Inverter symbol

Noise margin: A measure of the

sensitivity of a gate to noise

NML,H represent the noise margin

“low” and “high”, respectively
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 Timing issues in digital circuits
• Propagation delay (tp): the delay experienced
by a signal passing through a gate
V in

TpLH : response time of

50% a gate from low to high
t
TpHL : response time of
tpHL tpLH
V out a gate from high to low
90%
TpLH + TpHL
50% Tp =
2
10% t
tf tr
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 What can affect Tp?
• Circuit topology and process technology
• Load factors
• Fan-out and fan-in

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 Power and energy consumption
• Static power consumption
• Dynamic power consumption
• Instantaneous power: P(t)=V(t)*I(t)
• Peak power: Ppeak=Vpeak *Ipeak
• Average power:
1 t +T Vsupply t +T
Pave = ∫ p (t )dt = ∫ isupply (t )dt
T t T t

• Energy-delay product: Pav * Tp

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Example: First-order RC network

− t/τ
Vout (t) = (1 − e )Vin (t)
Vout (50%) = ln(2) ⋅τ = 0.69τ
Vout (90%) = ln(9) ⋅τ = 2.2τ
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Example: First-order RC network

∞ ∞ dv in v
E in = ∫ i in (t)vin (t)dt = V ∫ C dt = CV ∫ dv in = CV 2
0 0 dt 0

∞ ∞ dv out v 1
E C = ∫ i out (t)v out (t)dt = ∫ vout dt = C ∫ v out dv out = CVout
2
C
0 0 dt 0 2

Only half power is delivered to the capacitor!!

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 Conclusion
• This week we have reviewed the history and
trend of digital circuit design
• Digital design metrics
– Noise
– Speed
– Power consumption
• we will start the devices (MOS) and fabrication
in the next class (read Chapter 3)

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