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Electronic Principles and Circuits

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(BEC303)

3rd SEMESTER, 2024

Prepared by

Dr. M V Sreenivas Rao, Dr. Shyamala C & Amrutha R,

Associate Professors and Assistant Professor
Dept of ECE
GSSSIETW, Mysuru
VISION

"To foster professional level competence in all areas of Electronics and Communication
Engineering and to benchmark the Department as a centre for nurturing Women
Engineers in the Country"

MISSION
M1: To impart value based Technical education and training.

M2: To impart Theoretical Knowledge, Practical Knowledge and Entrepreneurship Skills.

M3: Fostering culture of innovation and research for development of society.

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M4: To sensitize the Students regarding Social, Moral and Professional ethics.

M5: To provide industry standard certifications on skills to enhance students knowledge

make them prepared for placements
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Program Educational Objective’s
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PEO 1: To inculcate students to excel in professional career and/or higher education by

acquiring knowledge in the field of Electronics and Communication.
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PEO 2: To make the students capable of managing their profession based on existing as
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well as new emerging technologies in the area of Electronics and Communication

Engineering.

PEO 3: To Produce Technically competent graduates with Ability to analyse, design,

develop, optimise and implement Electronics and Communication systems.

PEO 4: To prepare the students to be able to exhibit professionalism, ethical attitude,

communication skills, team work in their profession and to adapt to current trends by
engaging in life-long learning.
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Electronic Principles and Circuits Semester 3

Course Code BEC303 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours
Examination nature (SEE) Theory/Practical
Course objectives:
This course will enable students to
 Design and analyse the BJT circuits as an amplifier and voltage regulation.
 Design of MOSFET Amplifiers and analyse the basic amplifier configurations using small
signal equivalent circuit models
 Design of operational amplifiers circuits as Comparators, DAC and filters.
 Understand the concept of positive and negative feedback.

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 Analyze Power amplifier circuits in different modes of operation.
 Construct Feedback and Oscillator circuits using FET.
 Understand the thyristor operation and the different types of thyristors.
Teaching-Learning Process (General Instructions)
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These are sample Strategies, which teacher can use to accelerate the attainment of the various course
outcomes.
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1. Lecture method (L) does not mean only traditional lecture method, but different type of teaching
methods may be adopted to develop the outcomes.
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2. Show Video/animation films to explain evolution of communication technologies.

3. Encourage collaborative (Group) Learning in the class
4.Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes critical
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thinking
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking
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skills such as the ability to evaluate, generalize, and analyze information rather than simply recall it.
6. Show the different ways to solve the same problem and encourage the students to come up with
their own creative ways to solve them.
7. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
MODULE-1
BJT AC models: Base Biased Amplifier, Emitter Biased Amplifier, Small Signal Operation, AC
Beta, AC Resistance of the emitter diode, Two transistor models, Analyzing an amplifier.
Voltage Amplifiers: Voltage gain, Multistage Amplifiers.
CC and CB Amplifiers: CC Amplifier, Output Impedance, Cascading CE and CC, Darlington
Connections, Voltage regulation, The Common base Amplifier.
[Text1]
MODULE-2

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MOSFET
Biasing in MOS amplifier circuits: Fixing VGS, Fixing VG, Drain to Gate feedback resistor.
Small signal operation and modelling: The DC bias point, signal current in drain, voltage gain,
small signal equivalent circuit models, transconductance, The T equivalent circuit model.
MOSFET Amplifier configuration: Basic configurations, characterizing amplifiers, CS amplifier
with and without source resistance, The Common Gate Amplifier, Source follower.
MODULE-3
Linear Opamp Circuits: Summing Amplifier and D/A Converter, Nonlinear Op-amp Circuits:
Comparator with zero reference, Comparator with non-zero references. Comparator with Hysteresis.
Oscillator: Theory of Sinusoidal Oscillation, The Wein-Bridge Oscillator, RC Phase Shift
Oscillator, The Colpitts Oscillator, Hartley Oscillator, Crystal Oscillator.
The 555 timer: Monostable Operation, Astable Operation.
[Text1]
MODULE-4
Negative Feedback: Four Types of Negative Feedback, VCVS Voltage gain, Other VCVS

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Equations, ICVS Amplifier, VCIS Amplifier, ICIS Amplifier (No Mathematical Derivation).
Active Filters: Ideal Responses, First Order Stages, VCVS Unity Gain Second Order Low pass
Filters, VCVS Equal Component Low Pass Filters, VCVS High Pass Filters, MFB Bandpass
Filters, Bandstop Filters.
[Text1]
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MODULE-5
Power Amplifiers: Amplifier terms, Two load lines, Class A Operation, Class B operation, Class
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B push pull emitter follower, Class C Operation.

Thyristors: The four layer Diode, SCR, SCR Phase control, Bidirectional Thyristors, IGBTs,
Other Thyristors.
[Text1]
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PRACTICAL COMPONENT OF IPCC (Experiments can be conducted either using any circuit simulation
software or discrete components)
Sl.NO Experiments
1 Design and Test
(i) Bridge Rectifier with Capacitor Input Filter
(ii) Zener voltage regulator

2 Design and Test

Biased Clippers – a)Positive, b) Negative , c) Positive-Negative
Positive and Negative Clampers with and without Reference.
3 Plot the transfer and drain characteristics of a JFET and calculate its drain resistance, mutual conductance
and amplification factor.

4 Plot the transfer and drain characteristics of n-channel MOSFET and calculate its parameters, namely;
drain resistance, mutual conductance and amplification factor.

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Design and test (i) Emitter Follower , (ii) Darlington Connection

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Design and plot the frequency response of Common Source JFET/MOSFET amplifier

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Test the Opamp Comparator with zero and non zero reference and obtain the Hysteresis curve.
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Design and test Full wave Controlled rectifier using RC triggering circuit.
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9 Design and test Precision Half wave and full wave rectifiers using Opamp

10 Design and test RC phase shift oscillator

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Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:
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5. Understand the characteristics of BJTs and FETs for switching and amplifier circuits.
6. Design and analyze amplifiers and oscillators with different circuit configurations and biasing conditions.
7. Understand the feedback topologies and approximations in the design of amplifiers and oscillators.
8. Design of circuits using linear ICs for wide range applications such as ADC, DAC, filters and timers.
9. Understand the power electronic device components and its functions for basic power electronic circuits.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a pass in the course if
he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal
Evaluation) and SEE (Semester End Examination) taken together.

The IPCC means the practical portion integrated with the theory of the course. CIE marks for the theory component
are 25 marks and that for the practical component is 25 marks.
CIE for the theory component of the IPCC
 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests (Two Tests,
each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other assessment methods

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 15.09.2023

mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the syllabus and the second test after
covering 85-90% of the syllabus.
 Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for the theory
component of IPCC (that is for 25 marks).
 The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of IPCC.
CIE for the practical component of the IPCC

 15 marks for the conduction of the experiment and preparation of laboratory record, and 10 marks for the
test to be conducted after the completion of all the laboratory sessions.
 On completion of every experiment/program in the laboratory, the students shall be evaluated including viva-
voce and marks shall be awarded on the same day.
 The CIE marks awarded in the case of the Practical component shall be based on the continuous evaluation of
the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of all experiments’ write-
ups are added and scaled down to 15 marks.

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 The laboratory test (duration 02/03 hours) after completion of all the experiments shall be conducted for 50
marks and scaled down to 10 marks.
 Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory component of


IPCC for 25 marks.
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The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the IPCC.
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SEE for IPCC
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for the
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course (duration 03 hours)

5. The question paper will have ten questions. Each question is set for 20 marks.
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6. There will be 2 questions from each module. Each of the two questions under a module (with a maximum of 3
sub-questions), should have a mix of topics under that module.
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7. The students have to answer 5 full questions, selecting one full question from each module.
8. Marks scored by the student shall be proportionally scaled down to 50 Marks
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will have a CIE
component only. Questions mentioned in the SEE paper may include questions from the practical
component.
 The minimum marks to be secured in CIE to appear for SEE shall be 10 (40% of maximum marks-25) in the
theory component and 10 (40% of maximum marks -25) in the practical component. The laboratory
component of the IPCC shall be for CIE only. However, in SEE, the questions from the laboratory
component shall be included. The maximum of 04/05 sub-questions are to be set from the practical
component of IPCC, the total marks of all questions should not be more than 20 marks.
 SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to qualify for
the SEE. Marks secured will be scaled down to 50.

 The student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100)
in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken
together.

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Suggested Learning Resources:

Books
1. Albert Malvino, David J Bates, Electronic Principles, 7th Edition, Mc Graw Hill Education, 2017, ISBN:978-0-
07-063424-4.
2. Microelectronic Circuits, Theory and Applications, Adel S Sedra, Kenneth C Smith, 6thEdition, Oxford,
2015.ISBN:978-0-19-808913-1

Web links and Video Lectures (e-Resources):

1. Integrated Electronics: Analog and Digital Circuits and Systems, Jacob Millman, Christos C. Halkias,
McGraw-Hill, 2015.
2. Electronic Devices and Circuit, Boylestad & Nashelsky, Eleventh Edition, Pearson, January 2015.

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

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 Course Outcome

After the completion of the Course, the students will be able to

Design BJT Amplifier circuits with different circuit configurations and

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biasing conditions.

Design MOSFET Amplifier circuits with different circuit configurations and

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biasing conditions.

CO3 Design Oscillator, Opamp and 555 Timer circuits for various applications.

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Apply the design of filter circuits and feedback topologies in amplifier and
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oscillator circuits.
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Understand the characteristics and functions of power electronic devices and

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thyristors for basic power electronic circuits.
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Thyristor
 The Four-Layer Diode

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• Thyristor operation :

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• The upper transistor Q1 is a pnp

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device, and the lower transistor Q2 is
an npn device.

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Q2. Similarly, the collector of Q2 drives
the base of Q1.

• Positive Feedback: This uses a positive feedback.

• If the base current of Q2 increases, the collector current of Q2
increases. This increases the base current of Q1 and the collector
current of Q1. This amplify-and-feedback action continues until
both transistors are driven into saturation and circuit acts like a
closed switch (Fig. 13-1b).
 The Four-Layer Diode

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• On the other hand, if something causes the base current of Q2 to

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decrease, the collector current of Q2 decreases, the base current

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of Q1 decreases, the collector current of Q1 decreases, and the
base current of Q2 decreases further. This action continues until
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both transistors are driven into cutoff. Then, the circuit acts like
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an open switch (Fig. 13-1c).

• Therefore the circuit of Fig. 13-1a is stable in either of two states:

open or closed. It will remain in either state indefinitely until acted
on by an outside force.
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The Four-Layer Diode

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• Figure 13-2a shows a latch connected to a load resistor with a supply

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voltage of VCC.
• Let the latch be open, as shown in Fig. 13-2b. As there is no current

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through the load resistor, the voltage across the latch equals the

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supply voltage.

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• So, the operating point is at the lower end of the dc load line (Fig. 13-
2d ).
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• The only way to close the latch of Fig. 13-2b is by breakover. This
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means using a large enough supply voltage VCC to break down the
Q1 collector diode.
• Since the collector current of Q1 increases the base current of Q2,
the positive feedback will start. This drives both transistors into
saturation.
• When saturated, both transistors ideally look like short-circuits, and
the latch is closed (Fig. 13-2c).
• Now the latch has zero voltage across it when it is closed and the
operating point is at the upper end of the load line (Fig. 13-2d ).
• Again to open the latch reduce the VCC supply to zero. This forces the
transistors to switch from saturation to cutoff.
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The Schockley Diode

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• Schockley diode, also known as four-layer diode,

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pnpn diode, and silicon unilateral switch (SUS).

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• This device lets current flow in only one direction.

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• The only way to close a four-layer diode is by
breakover. The only way to open it is by low-current
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drop-out, which means reducing the current to less
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than the holding current (given on data sheets).
• The holding current is the low value of current
where the transistors switch from saturation to
cutoff
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• Figure 13-4 shows the graph of current versus
voltage of a four-layer diode.

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• The device has two operating regions: cutoff

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and saturation.
• The dashed line is the transition path

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between cutoff and saturation.
• It is dashed to indicate that the device

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states

• When the device is at cutoff, it has zero current.

• If the voltage across diode tries to exceed VB, the device breaks
over and moves rapidly along the dashed line to the saturation
region.
• When the diode is in saturation, it is operating on the upper line.
• As long as the current through it is greater than the holding
current IH, the diode remains latched in the on state.
• If the current becomes less than IH, the device switches into cutoff.
• The value of knee voltage VK, approximately 0.7 V
 .IN
The Silicon Controlled Rectifier

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• The SCR is the most widely used thyristor. It

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can switch very large currents on and off.
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Because of this, it is used to control motors,
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ovens, air conditioners, and induction heaters.
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C
.IN
VT
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N
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.IN
VT
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N
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.IN
 RC Circuit Controls Phase Angle

.IN
• Figure 13-22a shows ac line voltage being applied to

C
an SCR circuit that controls the current through a

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SY
heavy load. In this circuit, variable resistor R1 and
capacitor C shift the phase angle of the gate signal.
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• When R1 is zero, the gate voltage is in phase with
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the line voltage, and the SCR acts like a half-wave
rectifier. R2 limits the gate current to a safe level.
• When R1 increases, however, the ac gate voltage
lags the line voltage by an angle between 0° and
90°, as shown in Figs. 13-22b and c.
 RC Circuit Controls Phase Angle

.IN
• Before the trigger point shown in Fig. 13-22c, the

C
SCR is off and the load current is zero.

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• At the trigger point, the capacitor voltage is large
enough to trigger the SCR.
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• When this happens, almost all of the line voltage
appears across the load and the load current
becomes high.
• Ideally, the SCR remains latched until the line
voltage reverses polarity. This is shown in Figs. 13-
22c and d
 RC Circuit Controls Phase Angle

.IN
• The angle at which the SCR fi res is called the fi ring

C
angle, shown as fi re in Fig. 13-22a. The angle

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SY
between the start and end of conduction is called
the conduction angle, shown as conduction. The RC
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phase controller of Fig. 13-22a can change the fi
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ring angle between 0° and 90°, which means that
the conduction angle changes from 180° to 90°
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.IN
 .IN
Bidirectional Thyristors

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N
SY
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VT
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N
C
.IN
VT
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N
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.IN
VT
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N
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.IN
VT
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.IN
 .IN
IGBTs-Insulated-Gate Bipolar

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Transistors

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• Power MOSFETs and BJTs can both be used in

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high-power switching applications. The
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MOSFET has the advantage of greater
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switching speed, and the BJT has lower
conduction losses. By combining the low
conduction loss of a BJT with the switching
speed of a power MOSFET, we can begin to
approach an ideal switch.
• This hybrid device exists and is called an insulated-

.IN
gate bipolar transistor (IGBT).

C
• Its structure and operation closely resembles a

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power MOSFET.
• The basic structure of an n-channel IGBT is shown.
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Its structure resembles an n-channel power
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MOSFET constructed on a p-type substrate. As
shown, it has gate, emitter, and collector leads.
• Two versions of of IGBTs:

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– Punch-through (PT) and

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– Nonpunch-through (NPT) IGBTs.

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• Figure shows the structure of a PT IGBT.
• The PT IGBT has an n+ buffer layer between its p+
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and n- regions, and the NPT device has no n+ buffer
layer.
 .IN
• NPT versions have higher conduction VCE(on)

C
values than PT versions and a positive

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temperature coefficient.
• The positive temperature coefficient makes
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the NPT suited for paralleling.
• PT versions, with the extra n+ layer, have the
advantage of higher switching speeds. They
also have a negative temperature coefficient.
VT
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N
C
.IN
• Figures 13-31a and b show two common schematic symbols

.IN
for an n-channel IGBT.
• In Fig.b there is intrinsic body-diode.

C
• This built-in diode is similar to the body-diodes found in

N
power FETs.

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• Also, Fig. 13-31c shows a simplified equivalent circuit for this
device.
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• The IGBT is essentially a power MOSFET on the input side and
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a BJT on the output side.
• The input control is a voltage between the gate and emitter
leads.
• Just as in a power FET, the gate drive circuits for an IGBT must
be able to quickly charge up and discharge the IGBT’s input
capacitance for fast switching speeds.
• The output is a current between the collector and emitter
leads. Because the output of the IGBT relies on BJT
construction, this results in a slower device turn-off speed
than a power FET.
• The IGBT is a normally off high-input impedance

.IN
device.

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• When the input voltage VGE is large enough,

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collector current will begin to flow.

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• This minimum voltage value is the gate threshold
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voltage VGE(th).
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• The typical VGE(th) is 5.0 V when IC 5 60 mA.
• The maximum continuous collector current is
shown to be 60 A.
• Another important characteristic is its collector to
emitter saturation voltage VCE(sat).
• The typical VCE(sat) value, shown on the data sheet,
is 1.5 V at a collector current of 10 A and 2.5 V at a
collector current of 60 A
 IGBT Advantages

.IN
1. Conduction losses of IGBTs are related to the

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forward voltage drop of the device, and the

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MOSFET conduction loss is based on its RDS(on)

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values. For low-voltage applications, power
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MOSFETs can have extremely low RD(on)
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resistances.
2. IGBTs also have a much higher collector-emitter
breakdown voltage as compared to the VDSS
maximum value of MOSFETs.
This is important in applications using higher-
voltage inductive loads, such as inductive heating (IH)
applications. This makes the IGBT ideal for high-
voltage full H-bridge and half-bridge circuits
 IGBT Advantages

.IN
4. As compared to BJTs, IGBTs have a much higher

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input impedance and have much simpler gate drive

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requirements. Although the IGBT cannot match the
switching speed of the MOSFET, new IGBT families,
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such as FS IGBTs, are being developed for high-
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frequency applications. IGBTs are, therefore, effective
solutions for high-voltage and current applications at
moderate frequencies.
 .IN
Other Thyristors

C
• Photo-SCR(light-activated SCR):

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• The arrows represent incoming light that passes through a

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window and hits the depletion layers.
• When the light is strong enough, valence electrons are
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dislodged from their orbits and become free electrons.
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• The flow of free electrons starts the positive feedback, and
the photo-SCR closes.
• After a light trigger has closed the photo-SCR, it remains
closed, even though the light disappears. For maximum
sensitivity to light, the gate is left open, as shown in Fig. 13-
34a.
• To get an adjustable trip point, we can include the trigger
adjust shown in Fig. 13-34b. The resistance between the gate
and ground diverts some of the light-produced electrons and
reduces the sensitivity of the circuit to the incoming light.
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N
C
.IN
• Gate-Controlled Switch:

.IN
• low-current drop-out is the normal way to open an

C
SCR. But the gate-controlled switch is designed for

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SY
easy opening with a reversebiased trigger.
• A gate-controlled switch is closed by a positive
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trigger and opened by a negative trigger. Figure 13-
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35 shows a gate-controlled circuit.
• Each positive trigger closes the gate-controlled
switch, and each negative trigger opens it. Because
of this, we get the square-wave output shown. The
gate-controlled switch has been used in counters,
digital circuits, and other applications in which a
negative trigger is available
VT
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N
C
.IN
 Silicon Controlled Switch

.IN
• Figure 13-36a shows the doped regions of a silicon controlled

C
switch. Now an external lead is connected to each doped region.

N
• Visualize the device separated into two halves (Fig. 13-36b).

SY
Therefore, it’s equivalent to a latch with access to both bases (Fig.
13-36c).
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• A forward-bias trigger on either base will close the silicon
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controlled switch.
• Likewise, a reverse-bias trigger on either base will open the
device.
• Figure 13-36d shows the schematic symbol for a silicon controlled
switch
• . The lower gate is called the cathode gate, and the upper gate is
the anode gate.
• The silicon controlled switch is a low-power device compared to
the SCR. It handles currents in milliamperes rather than amperes.
VT
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N
C
.IN
 .IN
Unijunction Transistor and PUT

C
N
SY
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VT
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N
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.IN
VT
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N
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.IN
 Institute Vision and Mission
Vision
"To become a recognized world class Women Educational Institution, by imparting professional
education to the students, creating technical opportunities through academic excellence and technical
achievements, with ethical values"

Mission
 To support value based education with state of art infrastructure.

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 To empower women with the additional skill for professional future career
 To enrich students with research blends in order to fulfill the International challenges

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To create multidisciplinary center of excellence
To achieve Accreditation standards towards International education recognition.
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 To establish more Post Graduate & Research course.

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To increase Doctorates numbers towards the Research quality of academics.

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