Lecture 1: Overview & Introduction of MOS Transistors

Digital Systems, EE-208

Dr. S.K.Vishvakarma, IIT Indore

Introduction

°Integrated circuits: many transistors on one chip.

°Digital Systems
°Very Large Scale Integration (VLSI): bucketloads!
°Complementary Metal Oxide Semiconductor
• Fast, cheap, low power transistors

°Today: How to build your own simple CMOS chip

• CMOS transistors
• Building logic gates from transistors
• Transistor layout and fabrication
Silicon Lattice

°Transistors are built on a silicon substrate

°Silicon is a Group IV material
°Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si
Dopants

°Silicon is a semiconductor
°Pure silicon has no free carriers and conducts
poorly
°Adding dopants increases the conductivity
°Group V: extra electron (n-type)
°Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si
p-n Junctions

°A junction between p-type and n-type

semiconductor forms a diode.
°Current flows only in one direction

p-type n-type

anode cathode
 nMOS Transistor

°Four terminals: gate, source, drain, body

°Gate – oxide – body stack looks like a capacitor
• Gate and body are conductors
• SiO2 (oxide) is a very good insulator
• Called metal – oxide – semiconductor (MOS) capacitor
• Even though gate is
no longer made of metal*
Source Gate Drain
Polysilicon
SiO2
* Metal gates are returning today!

n+ n+
Body
p bulk Si
nMOS Operation

°Body is usually tied to ground (0 V)

°When the gate is at a low voltage:
• P-type body is at low voltage
• Source-body and drain-body diodes are OFF
• No current flows, transistor is OFF

Source Gate Drain

Polysilicon
SiO2

0
n+ n+
S D
p bulk Si
nMOS Operation Cont.

°When the gate is at a high voltage:

• Positive charge on gate of MOS capacitor
• Negative charge attracted to body
• Inverts a channel under gate to n-type
• Now current can flow through n-type silicon from source
through channel to drain, transistor is ON

Source Gate Drain

Polysilicon
SiO2

1
n+ n+
S D
p bulk Si
pMOS Transistor

°Similar, but doping and voltages reversed

• Body tied to high voltage (VDD)
• Gate low: transistor ON
• Gate high: transistor OFF
• Bubble indicates inverted behavior

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si
Power Supply Voltage

°GND = 0 V
°In 1980’s, VDD = 5V
°VDD has decreased in modern processes
• High VDD would damage modern tiny transistors
• Lower VDD saves power

°VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

Transistors as Switches

°We can view MOS transistors as electrically

controlled switches
°Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
CMOS Transistor Theory
°So far, we have treated transistors as ideal
switches
°An ON transistor passes a finite amount of current
• Depends on terminal voltages
• Derive current-voltage (I-V) relationships

°Transistor gate, source, drain all have capacitance

• I = C (DV/Dt) -> Dt = (C/I) DV
• Capacitance and current determine speed
Inverter Cross-section

°Typically use p-type substrate for nMOS

transistors
°Requires n-well for body of pMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

MOS Capacitor

°Gate and body form MOS

capacitor
°Operating modes
polysilicon gate
Vg < 0
silicon dioxide insulator
+
• Accumulation - p-type body

• Depletion (a)

• Inversion
0 < Vg < Vt
depletion region
+
-

(b)

Vg > Vt
inversion region
+
- depletion region

(c)

Introduction 15
Terminal Voltages

°Mode of operation depends on Vg, Vd, Vs Vg

• Vgs = Vg – Vs +
Vgs
+
Vgd
• Vgd = Vg – Vd - -
Vs Vd
• Vds = Vd – Vs = Vgs - Vgd -
Vds +

°Source and drain are symmetric diffusion terminals

• By convention, source is terminal at lower voltage
• Hence Vds  0
°nMOS body is grounded. First assume source is 0 too.
°Three regions of operation
• Cutoff
• Linear
• Saturation
nMOS Cutoff

°No channel
°Ids ≈ 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b
nMOS Linear

°Channel forms
°Current flows from d to s
• e- from s to d
Vgs > Vt
Vgd = Vgs
+ g +
°Ids increases with Vds - -
s d

°Similar to linear resistor n+ n+ Vds = 0

p-type body
b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
nMOS Saturation

°Channel pinches off

°Ids independent of Vds
°We say current saturates
°Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b
I-V Characteristics

°In Linear region, Ids depends on

• How much charge is in the channel?
• How fast is the charge moving?
CMOS Inverter

A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF

A Y
GND
CMOS NAND Gate

A B Y
ON
OFF
OFF
ON OFF
ON
0 0 1
0 1 1
1
0
Y
1 0 1 ON
A OFF

1 1 0 0
1
1
0
OFF
ON
B ON
OFF
CMOS NOR Gate

A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y
3-input NAND Gate

°Y pulls low if ALL inputs are 1

°Y pulls high if ANY input is 0

Y
A
B
C
Fabrication

°Chips are built in huge factories called fabs

°Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.