Maquina de Mealy

Maquina de Moore
set
set
process(present_state,x)
process(present_state,x)

Registro de estado

Registro de estado
s(t+1)
s(t+1)
C1 Siguiente s(t)
x(t) estado Estado C1 Siguiente s(t)
Entrada actual x(t) estado Estado
presente Entrada actual
process(present_state,x) z(t) presente
C2 process(present_state,x) z(t)
C2

clk
clk
process (clk, init) process (clk, init)
Implementar una maquina de estados que detecte la siguiente secuencia: 1101 cuando ocurra esto la
salida debe ser 1.

din
din : 1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0
clk fsm dout
dout : 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0
clr

0 1
1  𝑆 1
0 1
 𝑆 0 0
0
 𝑆 11
0
CLR 0 1
0 0

𝑆1101
  𝑆110
 
1 1 0
 Maquina de Moore sreg: process(clk, clr)
c1: process(present_state, din)
Begin
begin
din
if clr=‘1’
case then is
present_state
clk seqdata do
whenpresent_state
s0 => <= s0;
clr ut
elsif clk’event
if din = '1'and clk=‘1’ then
then
present_state <= next_state;
next_state <= s1;
library
when s3 ieee;
=> end if;else
use ieee.std_logic_1164.all;
if din = '1' then End process; next_state <= s0;
next_state <= s4; end if;
entity seqdata
else is c2: process(present_state)
when s1 =>
port( next_state <= s0; beginif din = '1' then
clk :end
in std_logic;
if; if present_state
next_state =<=s4s2;
then
clr
when: in
s4std_logic;
=> else dout <= '1';
din :ifindin
std_logic;
= '0' then else next_state <= s0;
dout: out std_logic);
next_state <= s0; dout <= '0';
end if;
end seqdata;
else whenend if;
s2 =>
next_state <= s2; end process;
if din = '0' then
Architecture
endcomportamiento
if; of seqdata is end comportamiento;
next_state <= s3;
Type when
state_type
others is =>
(s0, s1, s2, s3, s4); else
Signal present_state,
null; next_state: state_type; next_state <= s2;
Beginend case; end if;
end process;
 Maquina de Mealy

set
Maquina de Mealy process(present_state,x)

Registro de estado
s(t+1)
din
C1 Siguiente s(t)
clk seqdata dout x(t) estado Estado
clr Entrada actual
presente
process(present_state,x) z(t)
C2

1/1 clk
0/0
process (clk, init)

0/0
 𝑠 0  𝑠 1  𝑠 2  𝑠 3
1/0 0/0
1/0

1/0

0/0
when
library
s3ieee;
=> c1: process(present_state, din)
use ieee.std_logic_1164.all;
if din='1' then begin
next_state <= s1; case present_state is
entity seqdata
else is when s0 =>
port (clk : innext_state
std_logic;<= s0; if din='1' then
clr : in end
std_logic;
if; next_state <= s1;
din : inwhen
std_logic;
others => else
dout: out null;
std_logic); next_state <= s0;
endend
seqdata;
case; end if;
end process; when s1 =>
c2:
architecture
process(clk,Behavioral
clr) of seqdata is if din='1' then
begin
type state_type is (s0, s1, s2, s3); next_state <= s2;
signal
if clr
present_state,
= '1' then next_state: state_type; else
begin dout <= '0'; next_state <= s0;
sregelsif
: process(clk,clr)
clk'event and clk='1' then end if;
begin if present_state = s3 and din='1' then when s2 =>
if clr='1' then
dout <= '1'; if din='0' then
else
present_state <= s0; next_state <= s3;
elsif clk'event
dout <=and'0';
clk='1' then else
end
present_state
if; <= next_state; next_state <= s2;
end
endif;if; end if;
endend
process;
process;
end Behavioral;
 Count<15
SEMAFOROS

Count<3 S0
Count<3
S5 S1

Norte - Sur Este - Oeste

Estado Norte – Sur Este - Oeste Retardo(seg)

0 Verde Rojo 5
Count<3 S4 Count<3
S2
1 Amarillo Rojo 1

2 Rojo Rojo 1 S3
3 Rojo Verde 5

4 Rojo Amarillo 1
Count<15

5 Rojo Rojo 1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Case state is
entity trafico is when s0 =>
port (clk : in std_logic; if count < sec5 then
clr : in std_logic; state <= s0;
lights: out std_logic_vector(5 downto 0)); count <= count +1;
end trafico; else
state <= s1;
architecture Behavioral of trafico is count <= x"0";
Type state_type is (s0,s1,s2,s3,s4,s5); end if;
Signal count :std_logic_vector(3 downto 0); when s1 =>
Signal state : state_type; if count < sec1 then
Constant sec5 : std_logic_vector(3 downto 0) := "1111"; state <= s1;
Constant sec1 : std_logic_vector(3 downto 0) := "0011"; count <= count +1;
begin else
state <= s2;
process(clk,clr) count <= x"0";
Begin end if;
if clr='1' then
state <= s0;
count <= x"0";
elsif clk'event and clk='1' then
 when s4 =>
if count < sec1 then
when s2 => state <= s4;
if count < sec1 then count <= count +1;
state <= s2; else
count <= count +1; state <= s5;
else count <= x"0";
state <= s3; end if;
count <= x"0"; when s5 =>
end if; if count < sec1 then
when s3 => state <= s5;
if count < sec5 then count <= count +1;
state <= s3; else
count <= count +1; state <= s0;
else count <= x"0";
state <= s4; end if;
count <= x"0"; when others =>
end if; state <= s0;
end case;
End if;
End process;
 Rojo
C2: process(state) Verde
Begin
Case state is
when s0 => lights <= "100001";
when s1 => lights <= "100010";
when s2 => lights <= "100100";
when s3 => lights <= "001100";
when s4 => lights <= "010100";
when s5 => lights <= "100100";
when others => lights <= "100001";
End case;
End process;
End Behavioral;
 q3 q2 q1 q0
data_in D Q D Q D Q D Q

CLK CLK CLK CLK

 ´
𝑄  ´
𝑄  ´
𝑄  ´
𝑄
CLR CLR CLR CLR

clk

clr
library ieee; architecture Behavioral of ShiftReg is
use ieee.std_logic_1164.all; signal qs : std_logic_vector(3 downto 0);
begin
entity ShiftReg is process(clk, clr)
port( begin
clk : in std_logic; if clr = '1' then
clr : in std_logic; qs <= "0000";
data_in : in std_logic; elsif clk'event and clk ='1' then
q : out std_logic_vectro(3 downto 0)); qs(3) <= data_in;
end ShiftReg; qs(2 downto 0) <= qs(3 downto 1);
end if;
end process;
q <= qs;
end ShiftReg;
 q3 q2 q1 q0
D Q D Q D Q D Q

CLK CLK CLK CLK

 ´
𝑄  ´
𝑄  ´
𝑄  ´
𝑄
CLR CLR CLR SET

clk

clr
CONTADOR ANILLO architecture Behavioral of ContAn is
signal qs : std_logic_vector(3 downto 0);
library ieee; begin
use ieee.std_logic_1164.all; process(clk, clr)
begin
entity ContAn is if clr = '1' then
port( qs <= "0001";
clk : in std_logic; elsif clk'event and clk ='1' then
clr : in std_logic; qs(3) <= qs(0);
q : out std_logic_vectro(3 downto 0)); qs(2 downto 0) <= qs(3 downto 1);
end ContAn; end if;
end process;
q <= qs;
end ShiftReg;