Chapter Five

Sequential
logic circuits

Under graduate (2017)

Girma Adam (M.Tech)

5.1
 Cont’d..
Topics discussed in this section:
Introduction
Latch and Flip-flops
- R-s flip-flop
- D-flip-flop
-J-K flip-flop
- T-flip-flop
Registers
- Serial-in/serial-out
- serial in/parallel-out
- parallel in/serial-out
- parallel-in/parallel-out
Counter
- asynchronous
- synchronous

5.2
 Introduction
 Sequential circuits:- are constructed using combinational logic
and a number of memory elements with some or all of the
memory outputs fed back into the combinational logic forming
a feedback path or loop.

Block diagram of sequential circuit

5.3
 Cont’d..
 Sequential circuit = Combinational logic + Memory Elements

 Current State of A sequential Circuit: Value stored in memory

elements (value of state variables).

 State transition: A change in the stored values in memory

elements thus changing the sequential circuit from one state to
another state.

 A Memory Element: A logic device that can remember a

single-bit value indefinitely, or change its value on command
from its inputs.

5.4
 Cont’d..

 The output Q of the memory element represents the value stored

in the memory element. This is also called the state variable of the
memory elements.
 A memory element can be in one of two possible states:
– Q = 0 (the memory element has 0 stored), also said be in state 0.
– Q =1 (the memory element has 1 stored), also said to be in state 1.

5.5
 Cont’d..

 The commands to the memory element formed by its input(s)

may include:
– Set: Store 1 (Q=1) in the memory element.
– Reset: Store 0 (Q=0) in the memory element.
– Flip: Change stored value from 0 to 1 or from 1 to 0.
– Hold value: Memory value does not change.
 Memory Element state transition: A change in the stored value
from 0 to 1, or from 1 to 0 such as that caused by a flip command.

5.6
 Synchronous and asynchronous
 Synchronous sequential
- the time at which transitions between circuit states occurs is
controlled by common clock signals.
- Changes in all variables occur simultaneously
- Sequential circuits that have a clock signal as one of its inputs:
- All state transitions in such circuits occur only when the clock value is
either 0 or 1 or happen at the rising or falling edges of the clock depending on
the type of memory elements used in the circuit.

 Asynchronous sequential logic

- state transitions occur independently of any clock . And
normally depend on the time at which input variables changes.
- outputs do not necessarily changes simultaneously
5.7
 Clock Signals

 A clock signal is a periodic square wave that indefinitely switches

values from 0 to 1 and 1 to 0 at fixed intervals.

 Clock cycle time or clock period: The time interval between

two consecutive rising or falling edges of the clock.

 Clock Frequency = 1 / clock cycle time

5.8
 Latch and Flip-flop
 Latches and flip-flops are the basic single-bit memory elements
used to build sequential circuit with one or two inputs/outputs,
designed using individual logic gates and feedback loops.
1. Latches:
- The output of a latch depends on its current inputs and on its
previous inputs and its change of state can happen at any time when its
inputs change.
2. Flip-Flop:
- The output of a flip-flop also depends on current and previous input
but the change in output (change of state or state transition) occurs at
specific times determined by a clock input.
5.9
 S-R Flip-flop

 An S-R (set-reset) latch has two input terminals labelled as

S(for set) and R (for reset) and two output terminals labelled as
Q and Q.
 The output of the S-R latch depends on current as well as
previous state, and its state (value stored) can change as soon as
its inputs change.

5.10
 Cont’d..

 The truth table for S-R latch is given by

 Qn represents the existing state and Qn+1 represents the state of the flip-flop
after it has been triggered by an appropriate pulse at the R or S input

5.11
 Cont’d..

 The transition table for S-R latch is given by

5.12
 Cont’d..

 Timing Diagram (for S-R Flip-flop)

5.13
 Cont’d..

 The K-map for S-R latch is given by

 From the K-map the Boolean equations for S-R Circuit can be :-

 This equation can be implement using NOR or NAND gate

5.14
 Cont’d..

 Example.1. Design an S-R latch using two input NAND gates with
Active High input ?

Solution

5.15
 Cont’d..

 Example.2. If the S and R waveforms in figure below are

applied to the inputs of the active High S-R latch. Determine
the waveform that will be observed on the Q output ? Assume
that Q is initially Low.

5.16
 Cont’d..

 Solution

5.17
 Cont’d..

 Exercise 1. Design an S-R latch using two 2-inputs NOR gate ?

Solution
Using De-morgans law we can write

 The logic diagram For active-High input S-R using NOR gate
implementation

5.18
 Clocked R-S Flip-Flop
 Any clocked flip-flop, the outputs change states as per the
inputs only on the occurrence of a clock pulse.
 The clocked flip-flop could be a
1. level-triggered or
2. edge-triggered.
1. level-triggered one
- In a level-triggered flip-flop, the output responds to the data
present at the inputs during the time the clock pulse level is
HIGH (or LOW).
- That is, any changes at the input during the time the clock is active
(HIGH or LOW) are reflected at the output as per its function table.

5.19
 Cont,d..

 The truth table for Clocked R-S flip-flop with active HIGH
inputs.

5.20
 Cont,d..

 The logic diagram

5.21
 Cont’d..

2. Edge-triggered flip-flop
- In an edge-triggered flip-flop, the output responds to the
data at the inputs only on LOW-to-HIGH or HIGH-to-LOW
transition of the clock signal.
- The flip-flop in the two cases is referred to as positive edge
triggered and negative edge triggered respectively.
- Any changes in the input during the time the clock pulse is
HIGH (or LOW) do not have any effect on the output.
- The edge detector circuit transforms the clock input into a
very narrow pulse that is a few nanoseconds wide.

5.22
 Cont’d...

 The edge-detector circuit diagram

5.23
 Cont’d...

 The logic diagram

5.24
 Cont’d..

 Example.1. Determine Q and Q output waveforms of the flip-

flop in figure below for RS and Clk inputs for S-R flip-flop?
Assume that positive edge-triggered flip-flop is initially reset

 Solution

5.25
 Cont’d..

5.26
 Flip-flop operating characteristics

 The performance , operating requirements, and limitations of

flip-flops are specified by several operating characteristics or
parameter.
1. Propagation Delay Times
- A propagation delay time is the time interval of time required
after an input signal has been applied for the resulting output
change to occur.
a. Propagation delay tpLH as measured from the triggering edge of the clock
pulse to the LOW –to-HIGH transition of the output.

b. Propagation delay tpHL as measured from the triggering edge of the clock
pulse to the HIGH –to-LOW transition of the output.
5.27
 Cont’d..

2. Set-up time

- The set-up time (ts) is the minimum interval required for the
logic levels to be maintained constantly on the inputs prior to
the triggering edge of the clock pulse in order for the levels to
be reliably clocked in to the flip-flop.

5.28
 Cont’d..

3. Hold Time

- The hold time (th) is the minimum interval required for the logic
levels to remain on inputs after the triggering edge of the clock
pulse in order for the levels to be reliably clocked into the flip-
flop.

5.29
 Cont’d..

4. Maximum clock frequency(fmax):-is the highest rate at which a

flip-flop can be reliably triggered.

5. Pulse widths (tw):- is the minimum pulse width for reliable

operation are usually specified by the manufacturer for the
clock.
5.30
 Cont’d..

6. Power dissipation:-The power dissipation of any digital circuit is

the total power consumption of the device.

5.31
 D-flip-flop

 A D flip-flop, also called a delay flip-flop, can be used to provide

temporary storage of one bit of information. the data bit (0 or 1)
present at the D input is transferred to the output.
 The function table of D flip-flop shown below.

5.32
 Cont’d..

 The K-map and Boolean expression is given by

 The Logic diagram and logic symbol of D-Latch with enable input is
given by

5.33
 Cont’d..

 Example 1. Determine the Q output waveform if the input shown in

figure below are applied a D-Latch , which is initially
reset.

5.34
 Cont’d..

 The circuit symbol and function table of a negative edge-triggered

D flip-flop shown below.
 When the clock is active, the data bit (0 or 1) present at the D
input is transferred to the output.

5.35
 Cont’d..

 The D flip-flop can provide a maximum delay of one clock period

5.36
 J-K Flip-flop

 A J-K flip-flop behaves in the same fashion as an R-S flip-flop

except for one of the entries of the indeterminate state of the
RS type.

 Inputs J and K behave like inputs S and R to set and clear the
flip-flop, respectively.

 The input marked J is set and the input marked K is for reset.

 The output toggles for indeterminate case of RS ,Thus, a J-K

flip-flop overcomes the problem of a forbidden input
combination of the R-S flip-flop.

5.37
 Cont’d..

 The Block diagram and truth table for level-triggered J-K flip-
flops with active HIGH

5.38
 Cont’d..

 The K-map for J-K Flip-flop is given by

5.39
 Cont’d..
 From the K-map the Boolean equations for J-K Circuit can be :-

 Realization of J-K flip-flop using R-s flip-flop

5.40
 Cont’d..
 Realization of J-K flip-flop using R-s flip-flop with active High
input

5.41
 The Edge-triggered J-K flip-flop

1. The basic internal logic for a positive edge-triggered J-K flip-

flop.

5.42
 Cont’d..

 Example.1. The waveforms in figure below are applied to the

J,K and clock inputs as indicated. Determine the Q output,
assuming that the flip-flop is initially reset.

5.43
 Cont’d..

5.44
 Master–Slave Flip-Flops

 Whenever the width of the pulse clocking the flip-flop is

greater than the propagation delay of the flip-flop, the change in
state at the output is not reliable.
 The propagation delays are normally very small, One way to get
over come this problem by using a master–slave configuration.

5.45
 Toggle Flip-Flop (T Flip-Flop)

 The output of a toggle flip-flop, also called a T flip-flop, changes

state every time it is triggered at its T input, called the toggle
input.
 That is, the output becomes ‘1’ if it was ‘0’ and ‘0’ if it was ‘1’.
 If we consider the T input as active when HIGH the
characteristic table of such a flip-flop is shown below.

5.46
 Cont’d..

 The K-map of T-flip-flop is:-

 The Boolean equation is given by:-

5.47
 Cont’d..

 The circuit symbols of positive edge-triggered and negative

edge-triggered T flip-flops, along with their function tables.

5.48
 J-K Flip-Flop as a Toggle Flip-Flop

 The logic diagram is given by:-

5.49
 J-K Flip-Flop as D Flip-Flop

5.50
 Registers
 A Register:-is a group of binary cells suitable for holding binary
information.
 A group of flip-flops constitutes a register, since each flip-flop is a
binary cell capable of storing one bit of information.
 An n-bit register has a group of n flip-flops and is capable of storing any
binary information containing n bits.
 In addition to the flip-flops, a register may have combinational gates
that perform certain data-processing tasks.
 The flip-flops hold binary information and the gates control when and
how new information is transferred into the register.
 Various types of register are available , the simplest possible register is
one that consists of only flip-flops without any external gates.

5.51
 Shift Register
 A shift register is a digital device used for storage and transfer
of data.
 The basic building block in all shift registers is the flip-flop,
mainly a D-type flip-flop.
 The storage capacity of the shift register equals the number of
flip-flops used to construct the shift register. Since each flip-flop
can store one bit of data.
 The shift capability of a register permits the movement of data
from stage to stage within the register or into or out of the
register upon application of clock pulses.

5.52
 Cont’d..
 Based on the method used to load data onto and read data from
shift registers, they are classified as
1. serial-in serial-out (SISO)

2. Serial-in Parallel-out (SIPO)

3. Parallel-in Serial-out (PISO)
4. Parallel-in Parallel-out (PIPO)

5.53
 Serial-In Serial-Out Shift Register
 Serial-in serial-out shift register:- accepts data serially,that is ,
one bit at a time on a single line. it produces the stored
information on its output also in serial form.

5.54
 Cont’d..
 A 4-bit serial-in serial-out shift register implemented using D-
flip-flops. The circuit functions as follows.
- A reset applied to the CLEAR input of all the flip-flops resets
their Q outputs to 0’s.
- The waveform representing the data to be loaded onto the shift register
and the Q outputs of different flip-flops including clock pulse

5.55
 Cont’d..

5.56
 Cont’d..
 Example.1. Show the entry of four bits 1010 in to the register,
Assume that the register is initially cleared (all 0’s)

Solution

5.57
 Cont’d..

5.58
 Cont’d..
 Example.2. Show the states of the 5-register in figure below for
the specified data input and clock waveforms. Assume that the
register is initially cleared (all 0’s)

5.59
 Cont’d..
 Solution

5.60
 Serial-In Parallel-Out Shift Register
 Data bits are entered serially (right-most bit first) into ,this type
of register in the same manner as SISO. The difference is the way in which
the data bits are taken out of the register.
 Once the data are stored, each bit appears on its respective output line, and
all bits are available simultaneously.
 A 4-bit serial-in/parallel out shift register and its logic block diagram.

5.61
 Cont’d..
 Example.1. Show the states of the 4-register in figure below for the
specified data input and clock waveforms. Assume that the register is initially
set (all 1’s)

5.62
 Parallel in/serial out shift register
 For a register with parallel data inputs, bits are entered simultaneously in to
their respective stages on parallel lines. The serial output is the same as
before ,Once the data are completely stored in the register .
 A 4-bit parallel in/serial out shift register

5.63
 Cont’d..
 The logic diagram has a four data-input lines , Do,D1,D2 and D3.
 SHIFT/LOAD input , which allows four bits of data to Load in parallel into
register.
 When SHIFT/LOAD is LOW , gates G1-G4 are enabled, allowing each data bit
to be applied to the D input of its respective flip-flop.
 When a clock pulse is applied, the flip-flops with D=1 will set and those with
D=0 will reset, there by storing all four bits simultaneously.
 When SHIFT/LOAD is HIGH, gates G1 –G4 are disabled and gates G5-G7 are
enabled, allowing the data bits to shift right from one stage to the next.
 The OR gates allow either the normal shifting operation or parallel data-entry
operation, depending on which AND gates are enabled by the level on the
SHIFT/LOAD input.

5.64
 Cont’d..
 Notice that FFo has a single AND to disable the parallel input, Do. It doesn’t
required an AND/OR arrangement because there is no serial data in.
 Example.1. Show the data-output waveform for a 4-bit register with the
parallel input data(DoD1D2D3=1010) and the clock and
SHIFT/LOAD waveforms given below.
Solution

5.65
 Parallel in /parallel out shift register

5.66
 Counter
 A sequential circuits that goes through a prescribed sequence of
states upon the application of input pulses is called counter.
 The input pulses, called count pulses, may be clock pulses or they
may originate from an external source and may occur at
prescribed interval of time or at random.
 A counter that follows the binary sequence is called a binary
counter.
 An n-bit binary counter consists of n-flip-flops and can count in
binary from 0 to 2n -1.
 The number of flip-flops used and the way in which they are
connected determine the number of states is called modulus.
5.67
 Cont’d..
 Counter are classified into two broad categories according to the
way they are clocked.
1. Asynchronous counter
2. Synchronous counter
 In Asynchronous counters, commonly called ripple counters, the
first flip-flop is clocked by the external clock pulse and then each
successive flip-flop is clocked by the output of the preceding
flip-flop.

5.68
 Cont’d..
 A 2-bit asynchronous binary counter.

 Timing diagram

5.69
 Cont’d..
 Binary state sequence for the counter.

 A 3-bit asynchronous binary counter

5.70
 Cont’d..
 Timing diagram.

5.71
 Cont’d..
 State sequence for a 3-bit binary counter.

5.72
 Cont’d..
 Asynchronous counters are commonly referred to as ripple
counters because of the effect of an input clock pulse through the
counter, taking some time , due to propagation delays, to reach the
last flip-flop.
 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary
counter.

5.73
 Cont’d..
 Example.1. A 4-bit asynchronous binary counter is shown below.
Each flip-flop is negative edge-triggered and has a
propagation delay for 10 ns. Develop a timing diagram
showing the Q output of each flip-flop, and determine
the total propagation delay time from the triggering
edge of a clock pulse until a corresponding change can
occur in the state of Q3. Also determine the maximum
clock frequency at which the counter can be operated.

5.74
 Cont’d..

 Solution

5.75
 Cont’d..

 Asynchronous Decode counters

- The modulus of a counter is the number of unique states through
which the counter will sequence.
- The maximum possible number of states (maximum modulus) of a
counter is 2n where n is the number of flip-flops in the counter.

5.76
 Cont’d..
- Counter can be designed to have a number of states in their
sequence that is less than the maximum of 2n. This type of
sequence is called truncated sequence.
 One common module for counter with truncated sequences is a BCD
decode counter(MoD10)

5.77
 Cont’d..
 Timing diagram

 Exercise.1. Design an asynchronous counter which can be implemented

having a modulus of twelve with a straight binary sequence from 0000
through 1011.
5.78
 Cont’d..
2. Synchronous Counter :-is one in which all the flip-flops in the
counter are clocked at the same time by a
common clock pulse.

 A 2-bit synchronous binary counter

5.79
 Cont’d..
 Timing detail for the 2-bit synchronous counter operation (the
propagation delays of both flip-flops are assumed to be equal).

5.80
 Cont’d..
 The complete timing diagram of the counter

 A 3-bit synchronous binary counter

5.81
 Cont’d..
 The timing diagram of the 3-bit synchronous binary counter

5.82
 Cont’d..
 Binary state sequence for 3-bit synchronous binary counter

5.83
 Cont’d..
 A 4-bit asynchronous binary down counter

5.84
 Cont’d..
 Up/Down asynchronous counter :- is one that is capable of
progressing in either direction
through a certain sequence.
 An up/down counter, sometimes called a bi directional counter, can
have any specified sequence of states.
 A three-bit binary UP/DOWN counter.
- the counter counts upwards when UP control is logic ‘1’ and DOWN
control is logic ‘0’.

5.85
 Cont’d..

5.86