Synchronization in Digital Circuits

18 April 2025 11:00

Hey all!!!
In my previous post about Metastability, we dug deep into the fundamental cause of Metastability. (If you haven’t
seen that post yet, you can check it out in the Featured section of my profile.)

To summarize, we saw that whenever a Flip-Flop samples a value that is neither a logic '1' nor a logic '0', its output
will also be undefined—neither a logic '1' nor a logic '0' (at least for a short period of time). In this case, the Flip-
Flop is said to be in a Metastable state, and it may eventually come out of this state after some time. This duration
is called the Resolution time, which I’ll explain in detail today!

Capture window

Data changing in the capture window of the Flip-Flop

Here Flip-Flop entering into Metastable state and coming

Fig 1 : Shows Metastability in a Flip-Flop out of it after some time.

What might be the reason for a Flip-Flop to sample neither logic '0' nor logic '1'?
The reason is when a signal violates the Setup and Hold Time requirement of the Flip-Flop. Thus, that’s the crux of
my previous post!

Metastability is a very serious issue in Digital VLSI Design. It is no less than a Nightmare!!! To better understand
the severity of Metastability, let's consider the below sequential circuit:

DFF0

Data changing in the capture window of the Flip-Flop

Here Flip-Flop enters into Metastable state. The value

here is neither logic '0' nor logic '1'.

Here, since the Flip-Flop entered into Metastable state, it will cause the AND gate to go
into Metastable state that eventually causes the XOR gate to go into Metastable state.
Fig 2 : Shows the worst effect of Metastability

As we can see from the sequential circuit and the timing diagrams above, if the input signal (a) to a Flip-Flop does not satisfy the setup and hold time
requirements, it can cause the Flip-Flop to enter a metastable state. This, in turn, can affect all subsequent gates and parts of the circuit.
In the given circuit, for example, this could cause the System on Chip (SoC) to produce incorrect results, since the input to the SoC may become
indeterminate—neither a logic '1' nor logic '0'—which poses a serious issue. This situation becomes even more critical if the output of the Flip-Flop is
connected to the inputs of multiple gates, as it can lead all those gates into a metastable state as well, compounding the problem.

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What is the Real Problem here?
In the above circuit, can you guess where the main problem starts? The issue actually begins at the input (a) of the Flip-Flop (FF0), which violates the
Setup and Hold Time requirements. But why does this input have a high likelihood of violating these timing constraints?
The reason is that this Flip-Flop has no knowledge of when the signal will arrive at its input—in other words, the input is asynchronous to the clock of
the Flip-Flop. When we lack information about the timing of the signal's arrival relative to the Flip-Flop’s clock, it becomes nearly impossible to
ensure that the signal meets the Setup and Hold Time requirements. This uncertainty significantly increases the chances of timing violations and
potential Metastability.

From where does this Asynchronous signal come from?

1. This asynchronous signal can originate from a Flip-Flop that operates on a different clock frequency. This situation is known as Clock Domain
Crossing (CDC).
2. It can also result from any activity that is not synchronized to the receiving domain's clock. For example, consider a scenario where a push
button is used to reset a system. The user can press the button at any arbitrary time, without any knowledge of when the active clock edge of
the receiving Flip-Flop will occur. (The receiving Flip-Flop is the one into which this push button signal is fed in a sequential circuit.)

What is the possible solution here?

So, can you guess the solution to the above problem? Let me give you a clue! Think about what the real issue is—the actual problem lies in the fact
that the input (a) is asynchronous to the clock.
Now, many of you might already have figured out the answer. It’s simple: since the input (a) is asynchronous to the clock, and that’s causing the issue,
then why not make it synchronous?
So, how do we make the input signal synchronous to the clock of the Flip-Flop (DFF0) in the above circuit? The simplest way is to insert another Flip-
Flop before the existing Flip-Flop (DFF0) in the circuit and provide the same clock to both Flip-Flops, as shown below:

DFF1 DFF0

Fig 3 : Shows circuit with single stage synchronizer to mitigate Metastability

Here, the signal s is synchronous with the clock of DFF0, even though the input (a) to DFF1 is asynchronous. In this setup, DFF1 is
called a synchronizer. Synchronizing a signal using only one Flip-Flop in this manner is referred to as a Single-Stage Synchronizer.
Now, let us understand this concept with the help of the timing diagram below:

Fig 4 : Shows the timing diagram for the circuit

In this setup, DFF0 receives s as its input, which becomes available after tcq (the Clock-to-Q propagation delay of DFF1). The data (a) is launched by DFF1 at the
active clock edge and is then captured by DFF0 at the next clock edge (as shown above).
If we choose the clock period appropriately, we can ensure that the input s meets the Setup Time requirement at DFF0. As a result, DFF0 will not enter a
Metastable state, and all the previously mentioned issues will be resolved!
However, note that there is a latency of one clock cycle for DFF0 to sample the synchronized input s.

For the signal s to meet the Setup Time constraint:

Here, tcq and ts are the Clock-to-Q propagation delay of DFF1 (the launch Flip-Flop) and Setup Time of
DFF0 (the capture Flip-Flop) respectively.

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 For the signal s to meet the Hold Time constraint:

Here, tcq and th are the Clock-to-Q propagation delay of DFF1 (the launch Flip-Flop) and Hold Time of DFF0 (the capture FF) respectively.

If we are able to satisfy the above two equations for the above circuit with single stage synchronizer, then we can avoid the Metastability issue
and our problem is solved!!!

The Reality!!!
Now, some of you might have noticed a loophole here—have we really solved the problem?
If you look closely at the circuit with the single-stage synchronizer, DFF0 now receives a synchronized input s relative to the clock. However, the
asynchronous input (a) is now connected to DFF1. Doesn’t that mean the asynchronous input could still cause DFF1 to enter a metastable state?
Yes, indeed.
So, in reality, we haven't eliminated the problem—we’ve simply shifted it from DFF0 to DFF1!

Not Very Bad!!!

Although we haven't completely solved the problem—but rather shifted it from DFF0 to DFF1—the situation is now actually in our favor. But
how? Let’s see.

As you can observe from the timing diagram (Fig. 4) of the circuit with the single-stage synchronizer, DFF0 now captures the input (a), one clock
cycle later compared to the circuit without the synchronizer (Fig. 2). This delay occurs because the asynchronous input (a) is first captured by the
synchronizing Flip-Flop (DFF1), and only after one clock cycle does it become available as the synchronous input s at the input of DFF0.
So, even if the asynchronous input (a) causes DFF1 to enter a Metastable state, there is still one full clock cycle (with some margin) for it to
resolve and produce a valid output. This ensures that DFF0 receives a clean, stable input and does not go into Metastable state, effectively
shielding the subsequent circuit—which is critical in our design—from Metastability issues!

Note: Also, isolating the Metastability problem to a single synchronizing Flip-Flop (DFF1) has an additional benefit. Even if a Metastability issue
occurs, it will only affect DFF1, causing it to enter a Metastable state first. On the other hand, if DFF0—whose output might connect to
multiple inputs of logic gates and Flip-Flops—goes directly into Metastability due to the asynchronous input (a), it could cause more serious
issues across the entire circuit.

The good news that supports the idea of avoiding Metastability using a single-stage synchronizer is the following theorem, which I will state
without proof:

The probability of a Flip-Flop remaining in Metastable state decreases exponentially with time.

Probability of Flip-Flop remaining

in Metastable state

Time available for the synchronizing Flip-Flop to come out of Metastability (tr)

Fig 5 : Shows the exponential decrease of probability of a Flip-Flop remaining in Metastable state with
Metastability resolution time

Interested readers can refer to this IEEE paper: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4070065, which provides a detailed mathematical
analysis of the Metastability behavior of Flip-Flops.

The theorem mentioned above states that if DFF1 enters a Metastable state due to the asynchronous input (a), the chances of it remaining in the Metastable
state decreases exponentially with time. As we just discussed, since the synchronizing Flip-Flop (DFF1) is given approximately one full clock cycle to resolve the
Metastability, there is a very high probability that it will come out of the Metastable state—assuming the clock period is not too short.
However, as a word of caution, it’s important to understand that this is still a matter of probability. While providing sufficient time significantly increases the
likelihood that DFF1 will resolve Metastability, we can never guarantee that it will. In fact, we can never be certain when, or even if, a Flip-Flop will come out of a
Metastable state once it has entered one.
When dealing with Metastability, we always talk in terms of probability, not certainty.

The Metastability Resolution time (tr) for single stage synchronizer

I am defining it as follows :

It is the maximum time available for the output of the synchronizing Flip-Flop (Q1 = s = D0) to resolve to a valid state
without causing the subsequent Flip-Flop (DFF0) to enter a Metastable state (see the timing diagram below).

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 Fig 6 : Timing diagram to calculate Metastability resolution time

From the above timing diagram it can be observed that:

If the synchronizing Flip-Flop (DFF1) comes out of the Metastable state before this time, it ensures that the subsequent Flip-Flop (DFF0)
will not enter a Metastable state.

We want the resolution time (tr) to be as high as possible, because doing so gives the synchronizing Flip-Flop more time—and therefore a
better chance—to resolve Metastability.

From Equation 3, it's clear that to increase the resolution time, we can either increase the clock period (or equivalently, reduce the clock
frequency). However, this comes at the cost of reduced system throughput.

There is, however, another way to increase the Metastability resolution time without reducing system throughput: by adding one more
Flip-Flop in front of the synchronizing Flip-Flop in Figure 3. This configuration is known as a Double-Stage Synchronizer.

DFF1 DFF DFF0

Fig 7 : Shows circuit with double stage synchronizer to mitigate Metastability

Note: The downside of using a Double-Stage Synchronizer is that there is now a latency of two clock cycles for
DFF0 to sample the synchronized input s.

In fact, we can add any number of Flip-Flops to create a higher-stage synchronizer. However, the trade-off is that
latency increases proportionally with each added stage. Therefore, in most practical applications, we generally
use a maximum of two stages for synchronization.

Lastly, there is one more important concept related to synchronization in digital circuits, and that is the Mean Time Between Failures (MTBF).

MTBF (Mean Time Between Failures):

The MTBF is defined as :

Failure : The Flip-Flop remains in Metastability even after tr

or,
Here,
tr : Metastability resolution time
f : Frequency of the clock
era e fre ue c of the as chro ous put
T, o sta ts a epe s upo the character st cs of the Fl p Flop

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