UNIT-5

Introduction to Data transfer techniques

Bus Interface – UART
Interfacing UART to Microprocessor Unit
Programmed IO, Interrupt driven IO
Direct Memory Access
I/O Interrupt
I/O channel/Processor
Interconnection Standards – PCI Bus, SCSI, USB
Interconnection Standards -Firewire, SATA, SAS, PCI
Express
INPUT-OUTPUT ORGANIZATION

- INTRODUCTION
 Input/Output Interfaces

INPUT/OUTPUT INTERFACES
* Provides a method for transferring information between internal storage
(such as memory and CPU registers) and external I/O devices

* Resolves the differences between the computer and peripheral devices

- Peripherals - Electromechanical Devices

CPU or Memory - Electronic Device

- Data Transfer Rate

Peripherals - Usually slower
CPU or Memory - Usually faster than peripherals
Some kinds of Synchronization mechanism may be needed

- Unit of Information
Peripherals - Byte
CPU or Memory - Word

- Operating Modes
Peripherals - Autonomous, Asynchronous
CPU or Memory - Synchronous
 Input/Output Interfaces

I/O BUS AND INTERFACE MODULES

I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic
disk
Magnetic
tape
display
terminal
Each peripheral has an interface module associated with it

Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
Typical I/O instruction
Op. code Device address Function code
(Command)
 Introduction to Data Transfer Techniques

• Data transfer may take place between two devices.

For e.g.
– Microprocessor and memory
– Microprocessor and I/O device
– Memory and I/O device
• Classification of data transfer techniques
– Programmed data transfer
– Direct Memory Access (DMA)
 Asynchronous Data Transfer

ASYNCHRONOUS DATA TRANSFER

Synchronous and Asynchronous Operations

Synchronous - All devices derive the timing
information from common clock line
Asynchronous - No common clock

Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted
Two Asynchronous Data Transfer Methods
Strobe pulse
- A strobe pulse is supplied by one unit to indicate
the other unit when the transfer has to occur

Handshaking
- A control signal is accompanied with each data
being transmitted to indicate the presence of data
- The receiving unit responds with another control
signal to acknowledge receipt of the data
 Asynchronous Data Transfer

STROBE CONTROL

• The strobe may be activated by either the source or the destination unit

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe
• a strobe is a signal that is sent that validates
data or other signals on adjacent parallel lines.
In memory technology, the CAS (column
address strobe) and RAS ( row
address strobe ) signals are used to tell a
dynamic RAM that an address is a column or
row address.
 Asynchronous Data Transfer

HANDSHAKING

Strobe Methods

Source-Initiated

The source unit that initiates the transfer has

no way of knowing whether the destination unit
has actually received data

Destination-Initiated

The destination unit that initiates the transfer

no way of knowing whether the source has
actually placed the data on the bus

To solve this problem, the HANDSHAKE method

introduces a second control signal to provide a Reply
to the unit that initiates the transfer
 Asynchronous Data Transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE

Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus
Timing Diagram

Data valid

Data accepted

Sequence of Events Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
 Asynchronous Data Transfer

DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Data bus
Block Diagram Source Data valid Destination
unit Ready for data unit

Timing Diagram Ready for data

Data valid

Valid data
Data bus

Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

* Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism
 Buses
Processor, main memory, and I/O devices are
interconnected by means of a bus.
Bus provides a communication path for the
transfer of data.
◦ Bus also includes lines to support interrupts and arbitration.

A bus protocol is the set of rules that govern

the behavior of various devices connected to
the bus, as to when to place information on
the bus, when to assert control signals, etc.
 Buses (contd..)
Bus lines may be grouped into three types:
 Data
 Address
 Control

Control signals specify:

 Whether it is a read or a write operation.
 Required size of the data, when several operand sizes (byte, word, long word) are possible.
 Timing information to indicate when the processor and I/O devices may place data or
receive data from the bus.

Schemes for timing of data transfers over a bus can

be classified into:
 Synchronous,
 Asynchronous.
 Synchronous bus (contd..)
Time
Bus clock

Address and
command

Data

t0 t1 t2

Bus cycle
Master places the
device address and Addressed slave places
command on the bus, data on the data lines Master “strobes” the data
and indicates that on the data lines into its
it is a Read operation. input buffer, for a Read
operation.
• In case of a Write operation, the master places the data on the bus along with the
address and commands at time t0.
• The slave strobes the data into its input buffer at time t2.
 Synchronous bus (contd..)
Once the master places the device address and
command on the bus, it takes time for this
information to propagate to the devices:
◦ This time depends on the physical and electrical characteristics of the bus.

Also, all the devices have to be given enough time

to decode the address and control signals, so that
the addressed slave can place data on the bus.
Width of the pulse t1 - t0 depends on:
◦ Maximum propagation delay between two devices connected to the bus.
◦ Time taken by all the devices to decode the address and control signals, so that the
addressed slave can respond at time t1.
 Synchronous bus (contd..)
At the end of the clock cycle, at time t2, the
master strobes the data on the data lines into its
input buffer if it’s a Read operation.
◦ “Strobe” means to capture the values of the data and store them into a buffer.

When data are to be loaded into a storage

buffer register, the data should be available for a
period longer than the setup time of the device.
Width of the pulse t2 - t1 should be longer than:
◦ Maximum propagation time of the bus plus
◦ Set up time of the input buffer register of the master.
 Synchronous bus (contd..) Time
Address & Bus clock
command Data reaches
Seen by
appear on the master t AM the master.
bus. Address and
command

Data
Address & t DM
command reach
Seen by slave
the slave. tAS
Address and Data appears
command on the bus.

Data
tDS

t0 t1 t
2
• Signals do not appear on the bus as soon as they are placed on the bus, due to the
propagation delay in the interface circuits.
• Signals reach the devices after a propagation delay which depends on the
characteristics of the bus.
• Data must remain on the bus for some time after t2 equal to the hold time of the buffer.
 Synchronous bus (contd..)
• Data transfer has to be completed within one
clock cycle.
– Clock period t2 - t0 must be such that the longest propagation delay on the
bus and the slowest device interface must be accommodated.
– Forces all the devices to operate at the speed of the slowest device.

• Processor just assumes that the data are

available at t2 in case of a Read operation, or
are read by the device in case of a Write
operation.
– What if the device is actually failed, and never really responded?
 Synchronous bus (contd..)
• Most buses have control signals to represent a
response from the slave.
• Control signals serve two purposes:
– Inform the master that the slave has recognized the address, and is ready to
participate in a data transfer operation.
– Enable to adjust the duration of the data transfer operation based on the
speed of the participating slaves.

• High-frequency bus clock is used:

– Data transfer spans several clock cycles instead of just one clock cycle as in the
earlier case.
 Synchronous bus (contd..)
Address & command Time
requesting a Read
operation appear on 1 2 3 4
the bus.
Clock

Address

Command
Master strobes data
into the input buffer.
Data

Slave-ready

Slave places the data on the bus, Clock changes are seen by all the devices
and asserts Slave-ready signal. at the same time.
 Asynchronous bus
Data transfers on the bus is controlled by a handshake
between the master and the slave.
Common clock in the synchronous bus case is replaced by
two timing control lines:
 Master-ready,
 Slave-ready.

Master-ready signal is asserted by the master to indicate to

the slave that it is ready to participate in a data transfer.
Slave-ready signal is asserted by the slave in response to the
master-ready from the master, and it indicates to the master
that the slave is ready to participate in a data transfer.
 Asynchronous bus (contd..)
• Data transfer using the handshake protocol:
– Master places the address and command information on the bus.
– Asserts the Master-ready signal to indicate to the slaves that the address and
command information has been placed on the bus.
– All devices on the bus decode the address.
– Address slave performs the required operation, and informs the processor it
has done so by asserting the Slave-ready signal.
– Master removes all the signals from the bus, once Slave-ready is asserted.
– If the operation is a Read operation, Master also strobes the data into its input
buffer.
 Asynchronous bus (contd..)
Time
Address
and command

Master-ready

Slave-ready

Data

t0 t1 t2 t3 t4 t5

Bus cycle
t0 - Master places the address and command information on the bus.
t1 - Master asserts the Master-ready signal. Master-ready signal is asserted at t 1 instead of t0
t2 - Addressed slave places the data on the bus and asserts the Slave-ready signal.
t3 - Slave-ready signal arrives at the master.
t4 - Master removes the address and command information.
t5 - Slave receives the transition of the Master-ready signal from 1 to 0. It removes the data
and the Slave-ready signal from the bus.
Asynchronous vs. Synchronous bus
• Advantages of asynchronous bus:
– Eliminates the need for synchronization between the sender and the receiver.
– Can accommodate varying delays automatically, using the Slave-ready signal.

• Disadvantages of asynchronous bus:

– Data transfer rate with full handshake is limited by two-round trip delays.
– Data transfers using a synchronous bus involves only one round trip delay, and
hence a synchronous bus can achieve faster rates.
 UART – Universal
Asynchronous Receiver
Transmitter

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 Introduction of uart & usart

• UART – Stands for Universal Asynchronous Receiver Transmitter

• USART – Stands for Universal Synchronous Asynchronous Receiver Transmitter
• In RS-232 we implement serial port with UART
• Actually UART receives/sends data to microprocessor/microcontroller through data
bus. The remaining part of signal handling of RS-232 is done by UART i.e. start
bit, stop bit, parity etc.

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 WHY USE A UART?
A UART may be used when:
High speed is not required
An inexpensive communication link between two devices is required

UART communication is very cheap

Single wire for each direction (plus ground wire)
Asynchronous because no clock signal is transmitted
Relatively simple hardware

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 BASICS OF SERIAL COMMUNICATION
Bit rate:

-Number of bits sent every second (BPS)

Baud rate:

-Number of symbols sent every second, where every symbol can represent more than
one bit.

Ex. high-speed modems which use phase shifts to make every data transition period
represent more than one bit.

-For the PIC 16f877A’s USART, with every clock tick one bit is sent, each symbol
represents one bit.

-So, we can consider bit rate and baud rate the same thing.

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 TRANSMISSION REQUIREMENT

 Before transmission begins, transmitter and receiver must agree

on :

- Baud rate (75, 150, 300, 600, etc)

- 1, 1.5 or 2 stop bits

- 5, 6, 7 or 8 data bits

- even, odd or no parity

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BASIC BLOCK DIAGRAM OF UART

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BASIC BLOCK DIAGRAM OF UART
 UART/USART TRANSMITTER

1. The module is enabled by setting the TXEN bit.

2. Data to be sent should be written into the TXREG register. When using 9-bit,
TX9D must be written before writing TXREG.
3. Byte will be immediately transferred to the shift register TSR after the STOP
bit from the pervious load is sent.
4. From there, data will be clocked out onto the TX pin preceded by a START
bit and followed by a STOP bit. 32
 Transmitter Contd.

TXIF bit : in the PIR1 register

 Indicates when data can be written to TXREG(when data is moved from
TXREG into the Transmit Shift Register,
 It cannot be cleared in software. It will reset only when new data is loaded
into the TXREG register.
 It doesn’t indicate that the transmission has completed.

TRMT bit:
 Once the data in the TSR register has been clocked out on the TX pin(at
the beginning of the STOP bit), the TRMT bit in the TXSTA register will be
set,
 Indicating that the transmission has been completed.

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 UART/USART RECIEVER

1. The clock of the receiver is a multiple of the bit rate, in PIC 16f877A,it’s x16
or x64. So, each bit is transmitted/received in 16 clock cycle.
2. If the receiver detects a start bit for a period= bit period (16 clock cycles),
then it waits for the period of half bit, and then sample the value on the RX
pin and shift it in the receiving shift register.

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 RECEIVER CONTD.
3. Every received bit is sampled at the middle of the bit’s time period.

4. The USART can be configured to receive eight or nine bits by the RX9 bit in the
RCSTA register.

5. After the detection of a START bit, eight or nine bits of serial data are shifted
from the RX pin into the Receive Shift Register, one bit at a time.

6. After the last bit has been shifted in, the STOP bit is checked and the data is
moved into the FIFO buffer.

7. RCREG is the output of the two element FIFO buffer. A next start bit can be sent
immediately after the stop bit.

8. RCIF: indicates when data is available in the RCREG.

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 UART CHARACTER TRANSMISSION

Below is a timing diagram for the transmission of a single byte

Uses a single wire for transmission
Each block represents a bit that can be a mark (logic ‘1) or space (logic
‘0’) 1 bit time

mark

space
Time

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 UART REGISTERS
 To use and control the UART, special internal registers are assigned to them. Usually
there will be at least four registers: control, status, receive and transmit registers. All
these vary in size depending on the MCU.

1) Control Register - Contains settings for the UART. Some common settings/features
include: Number of data bits, number of stop bits, parity control, UART TX/RX
enable/disable, baud rate setting, RX/TX interrupt enable, etc.

2) Status Register - From its name, this contains information about the UART's condition
or state. During run-time, this register may be helpful in guiding the processor on the
next instruction to execute like when to retrieve data. Information that can be retrieved
include: data send/receive ready, etc.

3) Receive Register - This is the where received data is temporarily stored.

4) Transmit Register - A buffer register/s for temporarily storing data to be sent.

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UART Interfacing

38
MC6850 UART
 MC6850 UART
4 UART registers accessible by CPU selected
by R/~W and RS (register select):
– 00: control register
– 01: transmit data register
– 10: status register
– 11: receive data register
 MC6850 UART
UART control register: initialized by
program;
bits to divide tx/rec clocks by factor of 1, 16, or
64, select # of data bytes, type of parity, # of
stop bits, and interrupt control
• UART status register: status/error bits that
may either generate interrupts or be polled
by s/w:

– Received data reg. full (set when data transferred from serial input reg. to rec’d
data reg., reset when CPU reads data) to see if new data has arrived since last data
read
– Transmit data reg. empty (set when data transferred from transmit data reg. to
serial output reg.)
– RS-232 modem handshaking bits (DCD, CTS)
 UART Status Register
Interrupt request output bit (shows state of h/w IRQ)
• Error bits
– Framing error? UART detects an invalid stop bit
– Receiver overrun error? when data transferred from
serial input
reg. to rec’d data reg. before CPU has read last data; s/w
not
reading data fast enough, and data possibly lost
– Parity error? received character does not match
scheme ⇒ error in code word
 Flow Control
Refers to higher level of handshaking to control s/w
transferring data
Computer perhaps unable to deal with incoming
data quickly enough, data may be lost
Destination sends message to source to stop
sending data until ready to receive more
H/W flow control: RTS and CTS handshaking signals
used as h/w flow control; computer must control
these bits in the communication s/w
– Requires full DTE-DCE cable or full DTE-DTE null-
modem cable (need RTS/CTS)
Accessing I/O Devices
 Accessing I/O devices

Processor Memory

Bus

I/O device 1 I/O device n

• Multiple I/O devices may be connected to the processor and the memory via a bus.
• Bus consists of three sets of lines to carry address, data and control signals.
• Each I/O device is assigned an unique address.
• To access an I/O device, the processor places the address on the address lines.
• The device recognizes the address, and responds to the control signals.
 Accessing I/O devices (contd..)
I/O devices and the memory may share the same
address space:
 Memory-mapped I/O.
 Any machine instruction that can access memory can be used to transfer data to or
from an I/O device.
 Simpler software.

I/O devices and the memory may have different

address spaces:
 Special instructions to transfer data to and from I/O devices.
 I/O devices may have to deal with fewer address lines.
 I/O address lines need not be physically separate from memory address lines.
 In fact, address lines may be shared between I/O devices and memory, with a control
signal to indicate whether it is a memory address or an I/O address.

47
 Accessing I/O devices (contd..)
Address lines
Bus Data lines
Control lines

Address Control Data and I/O

decoder circuits status registers interface

Input device

• I/O device is connected to the bus using an I/O interface circuit which has:
- Address decoder, control circuit, and data and status registers.
• Address decoder decodes the address placed on the address lines thus enabling the
device to recognize its address.
• Data register holds the data being transferred to or from the processor.
• Status register holds information necessary for the operation of the I/O device.
• Data and status registers are connected to the data lines, and have unique addresses.
• I/O interface circuit coordinates I/O transfers.
 Accessing I/O devices (contd..)
Recall that the rate of transfer to and from I/O
devices is slower than the speed of the processor.
This creates the need for mechanisms to
synchronize data transfers between them.
Program-controlled I/O:
 Processor repeatedly monitors a status flag to achieve the necessary synchronization.
 Processor polls the I/O device.

Two other mechanisms used for synchronizing data

transfers between the processor and memory:
 Interrupts.
 Direct Memory Access.
 Programmed I/O
• Programmed I/O (PIO) refers to data transfers initiated by a CPU under driver
software control to access registers or memory on a device.
• The CPU issues a command then waits for I/O operations to be complete. As the
CPU is faster than the I/O module, the problem with programmed I/O is that the
CPU has to wait a long time for the I/O module of concern to be ready for either
reception or transmission of data. The CPU, while waiting, must repeatedly check
the status of the I/O module, and this process is known as Polling. As a result, the
level of the performance of the entire system is severely degraded.
• Programmed I/O basically works in these ways:
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
 INTERRUPT DRIVEN I/O
 The CPU issues commands to the I/O module then proceeds with its normal work
until interrupted by I/O device on completion of its work.
 For input, the device interrupts the CPU when new data has arrived and is ready to
be retrieved by the system processor. The actual actions to perform depend on
whether the device uses I/O ports, memory mapping.
 For output, the device delivers an interrupt either when it is ready to accept new
data or to acknowledge a successful data transfer. Memory-mapped and DMA-
capable devices usually generate interrupts to tell the system they are done with
the buffer.
 Although Interrupt relieves the CPU of having to wait for the devices, but it is still
inefficient in data transfer of large amount because the CPU has to transfer the
data word by word between I/O module and memory.
 Below are the basic operations of Interrupt:
 CPU issues read command
 I/O module gets data from peripheral whilst CPU does other work
 I/O module interrupts CPU
 CPU requests data
 I/O module transfers data
 Direct Memory Access (DMA)
• Direct Memory Access (DMA) means CPU grants I/O module authority to read
from or write to memory without involvement. DMA module controls exchange of
data between main memory and the I/O device. Because of DMA device can
transfer data directly to and from memory, rather than using the CPU as an
intermediary, and can thus relieve congestion on the bus. CPU is only involved at
the beginning and end of the transfer and interrupted only after entire block has
been transferred.
• Direct Memory Access needs a special hardware called DMA controller (DMAC)
that manages the data transfers and arbitrates access to the system bus. The
controllers are programmed with source and destination pointers (where to
read/write the data), counters to track the number of transferred bytes, and
settings, which includes I/O and memory types, interrupts and states for the CPU
cycles.
• DMA increases system concurrency by allowing the CPU to perform tasks while the
DMA system transfers data via the system and memory busses. Hardware design is
complicated because the DMA controller must be integrated into the system, and
the system must allow the DMA controller to be a bus master. Cycle stealing may
also be necessary to allow the CPU and DMA controller to share use of the
memory bus.
Interrupts
 Interrupts
In program-controlled I/O, when the processor
continuously monitors the status of the device, it
does not perform any useful tasks.
An alternate approach would be for the I/O device
to alert the processor when it becomes ready.
◦ Do so by sending a hardware signal called an interrupt to the processor.
◦ At least one of the bus control lines, called an interrupt-request line is dedicated for this
purpose.

Processor can perform other useful tasks while it

is waiting for the device to be ready.
 Interrupts (contd..)
Program 1 Interrupt Service routine

1
2

Interrupt
occurs i
here
i +1

• Processor is executing the instruction located at address i when an interrupt occurs.

• Routine executed in response to an interrupt request is called the interrupt-service routine.
• When an interrupt occurs, control must be transferred to the interrupt service routine.
• But before transferring control, the current contents of the PC (i+1), must be saved in a known
location.
• This will enable the return-from-interrupt instruction to resume execution at i+1.
• Return address, or the contents of the PC are usually stored on the processor stack.
 Interrupts (contd..)
Treatment of an interrupt-service routine is
very similar to that of a subroutine.
However there are significant differences:
 A subroutine performs a task that is required by the calling program.
 Interrupt-service routine may not have anything in common with the program it
interrupts.
 Interrupt-service routine and the program that it interrupts may belong to
different users.
 As a result, before branching to the interrupt-service routine, not only the PC, but
other information such as condition code flags, and processor registers used by
both the interrupted program and the interrupt service routine must be stored.
 This will enable the interrupted program to resume execution upon return from
interrupt service routine.
 Interrupts (contd..)
Saving and restoring information can be done automatically
by the processor or explicitly by program instructions.
Saving and restoring registers involves memory transfers:
 Increases the total execution time.
 Increases the delay between the time an interrupt request is received, and the start of execution of the
interrupt-service routine. This delay is called interrupt latency.

In order to reduce the interrupt latency, most processors

save only the minimal amount of information:
 This minimal amount of information includes Program Counter and processor status registers.

Any additional information that must be saved, must be

saved explicitly by the program instructions at the
beginning of the interrupt service routine.
 Interrupts (contd..)
• When a processor receives an interrupt-
request, it must branch to the interrupt
service routine.
• It must also inform the device that it has
recognized the interrupt request.
• This can be accomplished in two ways:
– Some processors have an explicit interrupt-acknowledge control signal for this
purpose.
– In other cases, the data transfer that takes place between the device and the
processor can be used to inform the device.
 Interrupts (contd..)
Interrupt-requests interrupt the execution of a program,
and may alter the intended sequence of events:
 Sometimes such alterations may be undesirable, and must not be allowed.
 For example, the processor may not want to be interrupted by the same device while executing
its interrupt-service routine.

Processors generally provide the ability to enable and

disable such interruptions as desired.
One simple way is to provide machine instructions such
as Interrupt-enable and Interrupt-disable for this
purpose.
To avoid interruption by the same device during the
execution of an interrupt service routine:
 First instruction of an interrupt service routine can be Interrupt-disable.
 Last instruction of an interrupt service routine can be Interrupt-enable.
 Interrupts (contd..)
Multiple I/O devices may be connected to the processor
and the memory via a bus. Some or all of these devices
may be capable of generating interrupt requests.
 Each device operates independently, and hence no definite order can be imposed on how the
devices generate interrupt requests?

How does the processor know which device has

generated an interrupt?
How does the processor know which interrupt service
routine needs to be executed?
When the processor is executing an interrupt service
routine for one device, can other device interrupt the
processor?
If two interrupt-requests are received simultaneously,
then how to break the tie?
 Interrupts (contd..)
Consider a simple arrangement where all devices send their
interrupt-requests over a single control line in the bus.
When the processor receives an interrupt request over this
control line, how does it know which device is requesting an
interrupt?
This information is available in the status register of the
device requesting an interrupt:
 The status register of each device has an IRQ bit which it sets to 1 when it requests an interrupt.

Interrupt service routine can poll the I/O devices connected

to the bus. The first device with IRQ equal to 1 is the one
that is serviced.
Polling mechanism is easy, but time consuming to query
the status bits of all the I/O devices connected to the bus.
 Interrupts (contd..)
The device requesting an interrupt may
identify itself directly to the processor.
◦ Device can do so by sending a special code (4 to 8 bits) the processor over the bus.
◦ Code supplied by the device may represent a part of the starting address of the
interrupt-service routine.
◦ The remainder of the starting address is obtained by the processor based on other
information such as the range of memory addresses where interrupt service
routines are located.

Usually the location pointed to by the

interrupting device is used to store the starting
address of the interrupt-service routine.
 Interrupts (contd..)
Multiple I/O devices may be connected to the processor
and the memory via a bus. Some or all of these devices may
be capable of generating interrupt requests.
 Each device operates independently, and hence no definite order can be imposed on how the devices
generate interrupt requests?

How does the processor know which device has generated

an interrupt?
How does the processor know which interrupt service
routine needs to be executed?
When the processor is executing an interrupt service
routine for one device, can other device interrupt the
processor?
If two interrupt-requests are received simultaneously, then
how to break the tie?
 Interrupts (contd..)
Consider a simple arrangement where all devices send their
interrupt-requests over a single control line in the bus.
When the processor receives an interrupt request over this
control line, how does it know which device is requesting an
interrupt?
This information is available in the status register of the
device requesting an interrupt:
 The status register of each device has an IRQ bit which it sets to 1 when it requests an interrupt.

Interrupt service routine can poll the I/O devices connected

to the bus. The first device with IRQ equal to 1 is the one
that is serviced.
Polling mechanism is easy, but time consuming to query
the status bits of all the I/O devices connected to the bus.
 Interrupts (contd..)
• The device requesting an interrupt may
identify itself directly to the processor.
– Device can do so by sending a special code (4 to 8 bits) the processor over the
bus.
– Code supplied by the device may represent a part of the starting address of
the interrupt-service routine.
– The remainder of the starting address is obtained by the processor based on
other information such as the range of memory addresses where interrupt
service routines are located.

• Usually the location pointed to by the

interrupting device is used to store the
starting address of the interrupt-service
routine.
 Interrupts (contd..)
Previously, before the processor started executing
the interrupt service routine for a device, it
disabled the interrupts from the device.
In general, same arrangement is used when
multiple devices can send interrupt requests to the
processor.
 During the execution of an interrupt service routine of device, the processor does not
accept interrupt requests from any other device.
 Since the interrupt service routines are usually short, the delay that this causes is
generally acceptable.

However, for certain devices this delay may not be

acceptable.
 Which devices can be allowed to interrupt a processor when it is executing an interrupt
service routine of another device?
Interrupts (contd..)
• I/O devices are organized in a priority
structure:
– An interrupt request from a high-priority device is accepted while the
processor is executing the interrupt service routine of a low priority device.

• A priority level is assigned to a processor that

can be changed under program control.
– Priority level of a processor is the priority of the program that is currently
being executed.
– When the processor starts executing the interrupt service routine of a device,
its priority is raised to that of the device.
– If the device sending an interrupt request has a higher priority than the
processor, the processor accepts the interrupt request.
Interrupts (contd..)
Processor’s priority is encoded in a few bits of
the processor status register.
◦ Priority can be changed by instructions that write into the processor status
register.
◦ Usually, these are privileged instructions, or instructions that can be executed
only in the supervisor mode.
◦ Privileged instructions cannot be executed in the user mode.
◦ Prevents a user program from accidentally or intentionally changing the priority
of the processor.

If there is an attempt to execute a privileged

instruction in the user mode, it causes a special
type of interrupt called as privilege exception.
 Interrupts (contd..)
INTR 1 I NTR p
Processor

Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration

• Each device has a separate interrupt-request and interrupt-acknowledge line.

• Each interrupt-request line is assigned a different priority level.
• Interrupt requests received over these lines are sent to a priority arbitration circuit
in the processor.
• If the interrupt request has a higher priority level than the priority of the processor,
then the request is accepted.
Interrupts (contd..)
Which interrupt request does the processor
accept if it receives interrupt requests from
two or more devices simultaneously?.
If the I/O devices are organized in a priority
structure, the processor accepts the interrupt
request from a device with higher priority.
 Each device has its own interrupt request and interrupt acknowledge line.
 A different priority level is assigned to the interrupt request line of each device.

However, if the devices share an interrupt

request line, then how does the processor
decide which interrupt request to accept?
 Interrupts (contd..)
Polling scheme:
• If the processor uses a polling mechanism to poll the status registers of I/O devices
to determine which device is requesting an interrupt.
• In this case the priority is determined by the order in which the devices are polled.
• The first device with status bit set to 1 is the device whose interrupt request is
accepted.
Daisy chain scheme:
I NTR
Processor

Device 1 Device 2 Device n

INTA

• Devices are connected to form a daisy chain.

• Devices share the interrupt-request line, and interrupt-acknowledge line is connected
to form a daisy chain.
• When devices raise an interrupt request, the interrupt-request line is activated.
• The processor in response activates interrupt-acknowledge.
• Received by device 1, if device 1 does not need service, it passes the signal to device 2.
• Device that is electrically closest to the processor has the highest priority.
 Interrupts (contd..)
• When I/O devices were organized into a priority structure, each device had its own
interrupt-request and interrupt-acknowledge line.
• When I/O devices were organized in a daisy chain fashion, the devices shared an
interrupt-request line, and the interrupt-acknowledge propagated through the devices.
• A combination of priority structure and daisy chain scheme can also used.
I NTR1

Device Device
INTA1
Processor

INTR p

Device Device
INTAp
Priority arbitration
circuit
• Devices are organized into groups.
• Each group is assigned a different priority level.
• All the devices within a single group share an interrupt-request line, and are
connected to form a daisy chain.
Interrupts (contd..)
Only those devices that are being used in a program
should be allowed to generate interrupt requests.
To control which devices are allowed to generate interrupt
requests, the interface circuit of each I/O device has an
interrupt-enable bit.
 If the interrupt-enable bit in the device interface is set to 1, then the device is allowed to generate
an interrupt-request.

Interrupt-enable bit in the device’s interface circuit

determines whether the device is allowed to generate an
interrupt request.
Interrupt-enable bit in the processor status register or the
priority structure of the interrupts determines whether a
given interrupt will be accepted.
 Exceptions
Interrupts caused by interrupt-requests sent by I/O
devices.
Interrupts could be used in many other situations
where the execution of one program needs to be
suspended and execution of another program needs
to be started.
In general, the term exception is used to refer to any
event that causes an interruption.
 Interrupt-requests from I/O devices is one type of an exception .

Other types of exceptions are:

 Recovery from errors
 Debugging
 Privilege exception
 Exceptions (contd..)
Many sources of errors in a processor. For
example:
 Error in the data stored.
 Error during the execution of an instruction.

When such errors are detected, exception

processing is initiated.
 Processor takes the same steps as in the case of I/O interrupt-request.
 It suspends the execution of the current program, and starts executing an exception-
service routine.

Difference between handling I/O interrupt-

request and handling exceptions due to errors:
 In case of I/O interrupt-request, the processor usually completes the execution of an
instruction in progress before branching to the interrupt-service routine.
 In case of exception processing however, the execution of an instruction in progress
usually cannot be completed.
 Exceptions (contd..)
• Debugger uses exceptions to provide
important features:
– Trace,
– Breakpoints.

• Trace mode:
– Exception occurs after the execution of every instruction.
– Debugging program is used as the exception-service routine.

• Breakpoints:
– Exception occurs only at specific points selected by the user.
– Debugging program is used as the exception-service routine.
 Exceptions (contd..)
Certain instructions can be executed only
when the processor is in the supervisor mode.
These are called privileged instructions.
If an attempt is made to execute a privileged
instruction in the user mode, a privilege
exception occurs.
Privilege exception causes:
◦ Processor to switch to the supervisor mode,
◦ Execution of an appropriate exception-servicing routine.
Direct Memory Access
 Direct Memory Access (contd..)
Direct Memory Access (DMA):
 A special control unit may be provided to transfer a block of data directly between an
I/O device and the main memory, without continuous intervention by the processor.

Control unit which performs these transfers is a

part of the I/O device’s interface circuit. This
control unit is called as a DMA controller.
DMA controller performs functions that would be
normally carried out by the processor:
 For each word, it provides the memory address and all the control signals.
 To transfer a block of data, it increments the memory addresses and keeps track of
the number of transfers.
 Direct Memory Access (contd..)

DMA controller can transfer a block of data from an

external device to the processor, without any intervention
from the processor.
 However, the operation of the DMA controller must be under the control of a program executed by
the processor. That is, the processor must initiate the DMA transfer.

To initiate the DMA transfer, the processor informs the

DMA controller of:
 Starting address,
 Number of words in the block.
 Direction of transfer (I/O device to the memory, or memory to the I/O device).

Once the DMA controller completes the DMA transfer, it

informs the processor by raising an interrupt signal.
 Direct Memory Access
Main
Processor
memory

System bus

Disk/DMA DMA Keyboard

controller controller Printer

Disk Disk Network

Interface

• DMA controller connects a high-speed network to the computer bus.

• Disk controller, which controls two disks also has DMA capability. It provides two
DMA channels.
• It can perform two independent DMA operations, as if each disk has its own DMA
controller. The registers to store the memory address, word count and status and
control information are duplicated.
 Direct Memory Access (contd..)
Processor and DMA controllers have to use the bus in
an interwoven fashion to access the memory.
 DMA devices are given higher priority than the processor to access the bus.
 Among different DMA devices, high priority is given to high-speed peripherals such as a disk
or a graphics display device.

Processor originates most memory access cycles on

the bus.
 DMA controller can be said to “steal” memory access cycles from the bus. This interweaving
technique is called as “cycle stealing”.

An alternate approach is the provide a DMA controller

an exclusive capability to initiate transfers on the bus,
and hence exclusive access to the main memory. This
is known as the block or burst mode.
 Bus arbitration
Processor and DMA controllers both need to initiate
data transfers on the bus and access main memory.
The device that is allowed to initiate transfers on
the bus at any given time is called the bus master.
When the current bus master relinquishes its status
as the bus master, another device can acquire this
status.
 The process by which the next device to become the bus master is selected and bus
mastership is transferred to it is called bus arbitration.

Centralized arbitration:
 A single bus arbiter performs the arbitration.

Distributed arbitration:
 All devices participate in the selection of the next bus master.
 Centralized Bus Arbitration

B BS Y

BR

Processor

DMA DMA
controller controller
BG1 1 BG2 2
 Centralized Bus Arbitration(cont.,)
• Bus arbiter may be the processor or a separate unit connected to the
bus.
• Normally, the processor is the bus master, unless it grants bus
membership to one of the DMA controllers.
• DMA controller requests the control of the bus by asserting the Bus
Request (BR) line.
• In response, the processor activates the Bus-Grant1 (BG1) line,
indicating that the controller may use the bus when it is free.
• BG1 signal is connected to all DMA controllers in a daisy chain fashion.
• BBSY signal is 0, it indicates that the bus is busy. When BBSY becomes
1, the DMA controller which asserted BR can acquire control of the
bus.
Centralized arbitration (contd..)
DMA controller 2
asserts the BR signal. Time
Processor asserts
BR
the BG1 signal

BG1 BG1 signal propagates

to DMA#2.
BG2

BBSY

Bus
master
Processor DMA controller 2 Processor

Processor relinquishes control

of the bus by setting BBSY to 1.
 Distributed arbitration
All devices waiting to use the bus share the
responsibility of carrying out the arbitration process.
 Arbitration process does not depend on a central arbiter and hence distributed arbitration
has higher reliability.

Each device is assigned a 4-bit ID number.

All the devices are connected using 5 lines, 4
arbitration lines to transmit the ID, and one line for
the Start-Arbitration signal.
To request the bus a device:
 Asserts the Start-Arbitration signal.
 Places its 4-bit ID number on the arbitration lines.

The pattern that appears on the arbitration lines is

the logical-OR of all the 4-bit device IDs placed on the
arbitration lines.
Distributed arbitration
 Distributed arbitration(Contd.,)
• Arbitration process:
– Each device compares the pattern that appears on
the arbitration lines to its own ID, starting with
MSB.
– If it detects a difference, it transmits 0s on the
arbitration lines for that and all lower bit positions.
– The pattern that appears on the arbitration lines is
the logical-OR of all the 4-bit device IDs placed on
the arbitration lines.
 Distributed arbitration (contd..)
• Device A has the ID 5 and wants to request the bus:
- Transmits the pattern 0101 on the arbitration lines.
• Device B has the ID 6 and wants to request the bus:
- Transmits the pattern 0110 on the arbitration lines.
• Pattern that appears on the arbitration lines is the logical OR of the patterns:
- Pattern 0111 appears on the arbitration lines.

Arbitration process:
• Each device compares the pattern that appears on the arbitration lines to its own
ID, starting with MSB.
• If it detects a difference, it transmits 0s on the arbitration lines for that and all lower
bit positions.
• Device A compares its ID 5 with a pattern 0101 to pattern 0111.
• It detects a difference at bit position 0, as a result, it transmits a pattern 0100 on the
arbitration lines.
• The pattern that appears on the arbitration lines is the logical-OR of 0100 and 0110,
which is 0110.
• This pattern is the same as the device ID of B, and hence B has won the arbitration.
Interface Circuits
 Interface circuits
I/O interface consists of the circuitry required to
connect an I/O device to a computer bus.
Side of the interface which connects to the
computer has bus signals for:
 Address,
 Data
 Control

Side of the interface which connects to the I/O

device has:
 Datapath and associated controls to transfer data between the interface and the I/O
device.
 This side is called as a “port”.

Ports can be classified into two:

 Parallel port,
 Serial port.
 Interface circuits (contd..)
• Parallel port transfers data in the form of a
number of bits, normally 8 or 16 to or from the
device.
• Serial port transfers and receives data one bit at
a time.
• Processor communicates with the bus in the
same way, whether it is a parallel port or a serial
port.
– Conversion from the parallel to serial and vice versa takes place inside the interface
circuit.
 Parallel port
Data

Address
DATAIN Data
Encoder
R /W and Keyboard
Processor SIN
debouncing switches
Master-ready circuit
Valid
Input
Slave-ready
interface

• Keyboard is connected to a processor using a parallel port.

• Processor is 32-bits and uses memory-mapped I/O and the asynchronous bus
protocol.
• On the processor side of the interface we have:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
 Parallel port (contd..)
Data

Address
DATAIN Data
Encoder
R/W and Keyboard
Processor SIN
debouncing switches
Master-ready circuit
Valid
Input
Slave-ready
interface

• On the keyboard side of the interface:

- Encoder circuit which generates a code for the key pressed.
- Debouncing circuit which eliminates the effect of a key bounce (a single key
stroke may appear as multiple events to a processor).
- Data lines contain the code for the key.
- Valid line changes from 0 to 1 when the key is pressed. This causes the code to
be loaded into DATAIN and SIN to be set to 1.
Input Interface Circuit
• Output lines of DATAIN are
are connected to the data lines of
the bus by means of 3 state drivers
• Drivers are turned on when the
processor issues a read signal and
the address selects this register.

• SIN signal is generated using a status flag circuit.

• It is connected to line D0 of the processor bus
using a three-state driver.
• Address decoder selects the input interface based
on bits A1 through A31.
• Bit A0 determines whether the status or data
register is to be read, when Master-ready is
active.
• In response, the processor activates the Slave-ready
signal, when either the Read-status or Read-data
is equal to 1, which depends on line A0.
 Parallel port (contd..)
Data

Address DATAOUT Data

Processor
CPU R /W SOUT Printer
Valid
Master-ready
Output Idle
Slave-ready interface

• Printer is connected to a processor using a parallel port.

• Processor is 32 bits, uses memory-mapped I/O and asynchronous bus protocol.
• On the processor side:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
 Parallel port (contd..)
Data

Address DATAOUT Data

Processor
CPU R /W SOUT Printer
Valid
Master-ready
Output Idle
Slave-ready interface

• On the printer side:

- Idle signal line which the printer asserts when it is ready to accept a character.
This causes the SOUT flag to be set to 1.
- Processor places a new character into a DATAOUT register.
- Valid signal, asserted by the interface circuit when it places a new character
on the data lines.
Output Interface Circuit
• Data lines of the processor bus
are connected to the DATAOUT
register of the interface.
• The status flag SOUT is connected
to the data line D1 using a three-state
driver.
• The three-state driver is turned on,
when the control Read-status line is
1.
• Address decoder selects the output
interface using address lines A1
through A31.
• Address line A0 determines whether
the data is to be loaded into the
DATAOUT register or status flag is
to be read.
• If the Load-data line is 1, then the
Valid line is set to 1.
• If the Idle line is 1, then the status
flag SOUT is set to 1.
 Bus
D7 PA7

DATAIN
D1
D0 PA0

SIN
• Combined I/O interface circuit.
Input
CA
• Address bits A2 through A31, that is
status
30 bits are used to select the overall
PB7
interface.
DATAOUT • Address bits A1 through A0, that is, 2
bits select one of the three registers,
PB0
SOUT
namely, DATAIN, DATAOUT, and
CB1
Handshake
control
the status register.
CB2
Slave-
Ready 1 • Status register contains the flags SIN and
SOUT in bits 0 and 1.
• Data lines PA0 through PA7 connect the
Master- input device to the DATAIN register.
Ready
R/ W
• DATAOUT register connects the data
A31 lines on the processor bus to lines PB0
My-address
Address
decoder through PB7 which connect to the output
A2 device.
A1
RS1 • Separate input and output data lines for
connection to an I/O device.
RS0
A0
 D7 P7
• Data lines to I/O device are bidirectional.
DATAIN • Data lines P7 through P0 can be used for
D0
both input, and output.
P0
• In fact, some lines can be used for input &
some for output depending on the pattern
in the Data Direction Register (DDR).
DATAOUT • Processor places an 8-bit pattern into a DDR
• If a given bit position in the DDR is 1, the
corresponding data line acts as an output
line, otherwise it acts as an input line.
• C1 and C2 control the interaction between
Data
Direction the interface circuit and the I/O devices.
Register
• Ready and Accept lines are the handshake
control lines on the processor bus side, and
My-address
are connected to Master-ready & Slave-ready.
RS2
• Input signal My-address is connected to the
C1
RS1 Status output of an address decoder.
Register
RS0 and
R/W
select control • Three register select lines that allow up to 8
Ready C2 registers to be selected.
Accept

INTR
 Serial port
• Serial port is used to connect the processor to
I/O devices that require transmission of data
one bit at a time.
• Serial port communicates in a bit-serial
fashion on the device side and bit parallel
fashion on the bus side.
– Transformation between the parallel and serial formats is achieved with shift
registers that have parallel access capability.
 Input shift register Serial
input
• Input shift register accepts input one bit
at a time from the I/O device.
DATAIN • Once all the 8 bits are received, the
contents of the input shift register are
loaded in parallel into DATAIN register.
• Output data in the DATAOUT register
are loaded into the output shift register.
D7 • Bits are shifted out of the output shift
register and sent out to the I/O device one
D0 bit at a time.
• As soon as data from the input shift reg.
My-address DATAOUT
are loaded into DATAIN, it can start
accepting another 8 bits of data.
RS1
• Input shift register and DATAIN registers
RS0
Chip and are both used at input so that the input
Serial
R /W register Output shift re gister
Ready select shift register can start receiving another
Accept set of 8 bits from the input device after
loading the contents to DATAIN, before
Receiving clock
the processor reads the contents of
I NTR Status
and
ransmission clock
DATAIN. This is called as double-
control
T buffering.
erial port (contd..)
Serial interfaces require fewer wires, and hence
serial transmission is convenient for connecting
devices that are physically distant from the computer.
Speed of transmission of the data over a serial
interface is known as the “bit rate”.
 Bit rate depends on the nature of the devices connected.

In order to accommodate devices with a range of

speeds, a serial interface must be able to use a range
of clock speeds.
Several standard serial interfaces have been
developed:
 Universal Asynchronous Receiver Transmitter (UART) for low-speed serial devices.
 RS-232-C for connection to communication links.
Standard I/O interfaces
I/O device is connected to a computer using an
interface circuit.
Do we have to design a different interface for every
combination of an I/O device and a computer?
A practical approach is to develop standard
interfaces and protocols.
A personal computer has:
 A motherboard which houses the processor chip, main memory and some I/O interfaces.
 A few connectors into which additional interfaces can be plugged.

Processor bus is defined by the signals on the

processor chip.
 Devices which require high-speed connection to the processor are connected directly to
this bus.
tandard I/O interfaces
(contd..)
Because of electrical reasons only a few devices
can be connected directly to the processor bus.
Motherboard usually provides another bus that
can support more devices.
 Processor bus and the other bus (called as expansion bus) are interconnected by a
circuit called “bridge”.
 Devices connected to the expansion bus experience a small delay in data transfers.

Design of a processor bus is closely tied to the

architecture of the processor.
 No uniform standard can be defined.

Expansion bus however can have uniform

standard defined.
 Standard I/O interfaces (contd..)
• A number of standards have been developed
for the expansion bus.
– Some have evolved by default.
– For example, IBM’s Industry Standard Architecture.

• Three widely used bus standards:

– PCI (Peripheral Component Interconnect)
– SCSI (Small Computer System Interface)
– USB (Universal Serial Bus)

108
Standard I/O interfaces (contd..)
Main
Processor
memory
Bridge circuit translates
signals and protocols from
Processor bus
processor bus to PCI bus.

Bridge

PCI bus
Expansion bus on
the motherboard
Additional SCSI Ethernet USB ISA
memory controller Interface controller Interface

SCSI bus
IDE
disk
Video
Disk CD-ROM
controller controller

CD-
Disk 1 Disk 2 ROM K eyboard Game
 PCI Bus
Peripheral Component Interconnect
Introduced in 1992
Low-cost bus
Processor independent
Plug-and-play capability
In today’s computers, most memory transfers involve a burst of data rather than just
one word. The PCI is designed primarily to support this mode of operation.
The bus supports three independent address spaces: memory, I/O, and configuration.
we assumed that the master maintains the address information on the bus until data
transfer is completed. But, the address is needed only long enough for the slave to be
selected. Thus, the address is needed on the bus for one clock cycle only, freeing the
address lines to be used for sending data in subsequent clock cycles. The result is a
significant cost reduction.
A master is called an initiator in PCI terminology. The addressed device that responds
to read and write commands is called a target.
Data transfer signals on the PCI bus.

Name Function

CLK A 33-MHz or 66-MHz clock.

FRAME# Sent b y the initiator to indicate the duration of a

transaction.

AD 32 address/data lines, which may be optionally

increased to 64.

C/BE# 4 command/byte-enable lines (8 for a 64-bit bus).

IRD Y#, TRD Y# Initiator-ready and Target-ready signals.

DEVSEL# A response from the device indicating that it has

recognized its address and is ready for a data
transfer transaction.

IDSEL# Initialization Device Select.

 1 2 3 4 5 6 7

CLK

Frame#

AD Adress #1 #2 #3 #4

C/BE# Cmnd Byte enable

IRDY#

TRD Y#

DEVSEL#

A read operation on the PCI bus

 Device Configuration
When an I/O device is connected to a computer, several actions are needed
to configure both the device and the software that communicates with it.
PCI incorporates in each I/O device interface a small configuration ROM
memory that stores information about that device.
The configuration ROMs of all devices are accessible in the configuration
address space. The PCI initialization software reads these ROMs and
determines whether the device is a printer, a keyboard, an Ethernet
interface, or a disk controller. It can further learn bout various device
options and characteristics.
Devices are assigned addresses during the initialization process.
This means that during the bus configuration operation, devices cannot be
accessed based on their address, as they have not yet been assigned one.
Hence, the configuration address space uses a different mechanism. Each
device has an input signal called Initialization Device Select, IDSEL#
Electrical characteristics:
PCI bus has been defined for operation with either a 5 or 3.3 V power supply
 SCSI Bus
The acronym SCSI stands for Small Computer System Interface.
It refers to a standard bus defined by the American National
Standards Institute (ANSI) under the designation X3.131 .
In the original specifications of the standard, devices such as disks are
connected to a computer via a 50-wire cable, which can be up to 25
meters in length and can transfer data at rates up to 5 megabytes/s.
The SCSI bus standard has undergone many revisions, and its data
transfer capability has increased very rapidly, almost doubling every
two years.
SCSI-2 and SCSI-3 have been defined, and each has several options.
Because of various options SCSI connector may have 50, 68 or 80 pins.
 SCSI Bus (Contd.,)
Devices connected to the SCSI bus are not part of the address space of the processor
The SCSI bus is connected to the processor bus through a SCSI controller. This controller uses
DMA to transfer data packets from the main memory to the device, or vice versa.
A packet may contain a block of data, commands from the processor to the device, or status
information about the device.
A controller connected to a SCSI bus is one of two types – an initiator or a target.
An initiator has the ability to select a particular target and to send commands specifying the
operations to be performed. The disk controller operates as a target. It carries out the
commands it receives from the initiator.
The initiator establishes a logical connection with the intended target.
Once this connection has been established, it can be suspended and restored as needed to
transfer commands and bursts of data.
While a particular connection is suspended, other device can use the bus to transfer
information.
This ability to overlap data transfer requests is one of the key features of the SCSI bus that leads
to its high performance.
 SCSI Bus (Contd.,)
Data transfers on the SCSI bus are always
controlled by the target controller.
To send a command to a target, an initiator
requests control of the bus and, after winning
arbitration, selects the controller it wants to
communicate with and hands control of the bus
over to it.
Then the controller starts a data transfer operation
to receive a command from the initiator.
 SCSI Bus (Contd.,)
Assume that processor needs to read block of data from a disk drive and that
data are stored in disk sectors that are not contiguous.
The processor sends a command to the SCSI controller, which causes the
following sequence of events to take place:
1. The SCSI controller, acting as an initiator, contends for control of the bus.
2. When the initiator wins the arbitration process, it selects the target controller and
hands over control of the bus to it.
3. The target starts an output operation (from initiator to target); in response to this,
the initiator sends a command specifying the required read operation.
4. The target, realizing that it first needs to perform a disk seek operation, sends a
message to the initiator indicating that it will temporarily suspend the connection
between them. Then it releases the bus.
5. The target controller sends a command to the disk drive to move the read head to the
first sector involved in the requested read operation. Then, it reads the data stored in
that sector and stores them in a data buffer. When it is ready to begin transferring
data to the initiator, the target requests control of the bus. After it wins arbitration, it
reselects the initiator controller, thus restoring the suspended connection.
 SCSI Bus (Contd.,)
6. The target transfers the contents of the data buffer to the
initiator and then suspends the connection again
7. The target controller sends a command to the disk drive to
perform another seek operation. Then, it transfers the
contents of the second disk sector to the initiator as before.
At the end of this transfers, the logical connection between
the two controllers is terminated.
8. As the initiator controller receives the data, it stores them
into the main memory using the DMA approach.
9. The SCSI controller sends as interrupt to the processor to
inform it that the requested operation has been completed
Operation of SCSI bus from H/W point of
view
Category Name Function

Data – DB(0) to Data lines: Carry one byte of information

– DB(7) during the information transfer phase and
iden tify device during arbitration, selection and
reselection phases
– DB(P) Parit y bit for the data bus
Phase – BSY Busy: Asserted when the bus is not free

– SEL Selection: Asserted during selection and

reselection

Information – C/D Control/Data: Asserted during transfer of

type con trol information (command, status or
message)

– MSG Message: indicates that the information being

transferred is a message

Table 4. The SCSI bus signals.

 Table 4. The SCSI bus signals.(cont.)

Category Name Function

Handshake – REQ Request: Asserted by a target to request a data

transfer cycle

– ACK Acknowledge: Asserted by the initiator when it

has completed a data transfer op eration

Direction of – I/O Input/Output: Asserted to indicate an input

transfer operation (relative to the initiator)

Other – ATN Attention: Asserted by an initiator when it

wishes to send a message to a target

– RST Reset: Causes all device controls to disconnect

from the bus and assume their start-up state
 Main Phases involved
Arbitration
A controller requests the bus by asserting BSY and by asserting it’s associated data
line
When BSY becomes active, all controllers that are requesting bus examine data lines
Selection
Controller that won arbitration selects target by asserting SEL and data line of
target. After that initiator releases BSY line.
Target responds by asserting BSY line
Target controller will have control on the bus from then
Information Transfer
Handshaking signals are used between initiator and target
At the end target releases BSY line
Reselection
 Targets examine ID

DB 2

DB 5

DB 6

BS Y

S EL

Free Arbitration Selection

Figure 42. Arbitration and selection on the SCSI bus.

Device 6 wins arbitration and selects device 2.
 USB
Universal Serial Bus (USB) is an industry standard
developed through a collaborative effort of several
computer and communication companies, including
Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, Nortel
Networks, and Philips.
Speed
Low-speed(1.5 Mb/s)
Full-speed(12 Mb/s)
High-speed(480 Mb/s)
Port Limitation
Device Characteristics
Plug-and-play
Universal Serial Bus tree structure

Host computer

Root
hub

Hub Hub

Hub I/O I/O I/O I/O

de vice de vice de vice de vice

I/O I/O
de vice de vice
 Universal Serial Bus tree structure
To accommodate a large number of devices that can be added or removed at
any time, the USB has the tree structure as shown in the figure.
Each node of the tree has a device called a hub, which acts as an intermediate
control point between the host and the I/O devices. At the root of the tree, a
root hub connects the entire tree to the host computer. The leaves of the tree
are the I/O devices being served (for example, keyboard, Internet connection,
speaker, or digital TV)
In normal operation, a hub copies a message that it receives from its upstream
connection to all its downstream ports. As a result, a message sent by the host
computer is broadcast to all I/O devices, but only the addressed device will
respond to that message. However, a message from an I/O device is sent only
upstream towards the root of the tree and is not seen by other devices. Hence,
the USB enables the host to communicate with the I/O devices, but it does not
enable these devices to communicate with each other.
 Addressing
When a USB is connected to a host computer, its root hub is attached to the processor bus,
where it appears as a single device. The host software communicates with individual
devices attached to the USB by sending packets of information, which the root hub
forwards to the appropriate device in the USB tree.
Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit address.
This address is local to the USB tree and is not related in any way to the addresses used on
the processor bus.
A hub may have any number of devices or other hubs connected to it, and addresses are
assigned arbitrarily. When a device is first connected to a hub, or when it is powered on, it
has the address 0. The hardware of the hub to which this device is connected is capable of
detecting that the device has been connected, and it records this fact as part of its own
status information. Periodically, the host polls each hub to collect status information and
learn about new devices that may have been added or disconnected.
When the host is informed that a new device has been connected, it uses a sequence of
commands to send a reset signal on the corresponding hub port, read information from
the device about its capabilities, send configuration information to the device, and assign
the device a unique USB address. Once this sequence is completed the device begins
normal operation and responds only to the new address.
 USB Protocols
All information transferred over the USB is organized in packets, where a packet
consists of one or more bytes of information. There are many types of packets
that perform a variety of control functions.
The information transferred on the USB can be divided into two broad
categories: control and data.
Control packets perform such tasks as addressing a device to initiate data transfer,
acknowledging that data have been received correctly, or indicating an error.
Data packets carry information that is delivered to a device.
A packet consists of one or more fields containing different kinds of information.
The first field of any packet is called the packet identifier, PID, which identifies the
type of that packet.
They are transmitted twice. The first time they are sent with their true values,
and the second time with each bit complemented
The four PID bits identify one of 16 different packet types. Some control packets,
such as ACK (Acknowledge), consist only of the PID byte.
 PID0 PID1 PID2 PID3 PID0 PID1 PID2 PID3

(a) Packet identifier field

Bits 8 7 4 5
Control packets used for
PID ADDR ENDP CRC16 controlling data transfer
operations are called token
packets.
(b) Token packet, IN or OUT

Bits 8 0 to 8192 16

PID DATA CRC16

(c) Data packet

Figure 45. USB packet format.

 Host Hub I/O Device

Token
Data0

ACK
Time
Token
Data0

ACK

Token
Data1
Figure: An output
transfer
ACK

Token
Data1

ACK
 Isochronous Traffic on USB
One of the key objectives of the USB is to support the transfer of isochronous data.
Devices that generates or receives isochronous data require a time reference to control the
sampling process.
To provide this reference. Transmission over the USB is divided into frames of equal length.
A frame is 1ms long for low-and full-speed data.
The root hub generates a Start of Frame control packet (SOF) precisely once every 1 ms to
mark the beginning of a new frame.
The arrival of an SOF packet at any device constitutes a regular clock signal that the device
can use for its own purposes.
To assist devices that may need longer periods of time, the SOF packet carries an 11-bit
frame number.
Following each SOF packet, the host carries out input and output transfers for isochronous
devices.
This means that each device will have an opportunity for an input or output transfer once
every 1 ms.
 Electrical Characteristics
The cables used for USB connections consist of four wires.
Two are used to carry power, +5V and Ground.
Thus, a hub or an I/O device may be powered directly from the
bus, or it may have its own external power connection.
The other two wires are used to carry data.
Different signaling schemes are used for different speeds
of transmission.
At low speed, 1s and 0s are transmitted by sending a high
voltage state (5V) on one or the other o the two signal wires.
For high-speed links, differential transmission is used.
 Firewire
IEEE 1394 is an interface standard for a serial bus for high-speed
communications and isochronous real-time data transfer. It was
developed in the late 1980s and early 1990s by Apple, which
called it FireWire. The 1394 interface is also known by the
brands i.LINK(Sony), and Lynx (Texas Instruments).
The copper cable it uses in its most common implementation can
be up to 4.5 metres (15 ft) long. Power is also carried over this
cable, allowing devices with moderate power requirements to
operate without a separate power supply. FireWire is also
available in Cat 5 and optical fiber versions.
The 1394 interface is comparable to USB, though USB requires a
master controller and has greater market share
Serial Advanced Technology
Attachment (SATA)
 SATA Uses in the Enterprise

• Scalability and Cost

• Cabling and
Connections
• Performance and SA
/ SAS Compatibility
 Scalability and Cost
• SATA is highly viable for servers and storage networks
• One SATA controller can aggregate multiple ports
• Multiple SATA drives can be linked using backplanes and
external enclosures
• SATA was designed to provide excellent speed and storage
at a low cost
• Cost and scalability provides potential for greater storage
capacity at a lower cost than networked or server storage
 Cabling and Connections
• Point-to-point connectivity
• Thin and relatively small (compared to PATA) cables allow for
simple routing and better airflow within systems
• SATA was designed to eliminate master and slave setups as well
as drive jumpers
• Hot swapping is supported
• Connectors allow for simple External RAID through backpanes
 Performance and SATA/SAS
Compatibility

• First Generation SATA (1.5 Gbit/s)

• Second Generation SATA (3.0 Gbit/s)
• Third Generation SATA (6.0 Gbit/s)
• Native Command Queuing (NCQ)
• Interoperability with SAS Initiators and
Expanders
 First Generation SATA (1.5 Gbit/s)

• Communication rate of 1.5 Gbit/s for data transfer

• At the application level, only one transaction can be
handled
at a given time
• Throughput capabilities similar to PATA/133 specification
• All optical drives operate at 1.5 Gbit/s transfer rate as well
as many hard disk drives and hosts
 Second Generation SATA (3.0 Gbit/s)
• Designed to compensate for first generation shortcomings
• Native Command Queuing (NCQ) support added for both
1.5 and 3.0 Gbit/s devices
• Backwards compatibility with 1.5 controllers and 3.0 Gbit/s
devices
• Second Generation SATA devices can drop to
1.5 Gbit/s transfer rate when communicating with
First Generation devices
• 3.0 Gbit/s transfer rate supported by many hosts and hard
disk drives
 Third Generation SATA (6.0 Gbit/s)

• With introduction of Solid State Disk (SSD) drives, which

operate at the 250 MB/s limit net read speed, enhancements
were required
• Isochronous data transfers in the NCQ streaming command
were added
• All DRAM cache reads operate at faster rates with Third
Generation
• New NCQ host processing and management
• Power management improved
• Former SATA cables and connectors still meet specification
 SAS
• SAS, the successor technology to the parallel SCSI interface, leverages
proven SCSI functionality and promises to greatly build on the existing
capabilities of the enterprise storage connection.
• SAS offers many features not found in today's mainstream storagesolutions.
These include drive addressability of up to 16,256 devices per port and
reliable point-to-point serial connections at speeds of up to 3G bps (375
MB/s).
• Due to its small connector, SAS offers full dual-ported connections on 3.5-in.
and smaller 2.5-in. hard disk drives, a feature
previously found only on larger 3.5-in. Fibre Channel disk drives. This is an
essential feature in applications requiring redundant drive spindles in a dense
server form factor such as blade servers.
 SAS

• SAS improves drive addressability and connectivity using an expander that enables one or
more SAS host controllers to connect to a large number of drives. Each expander allows
connectivity to 128 physical links, which may include other host connections, other SAS
expanders or hard disks. This highly scalable connection scheme enables enterprise-level
topologies that easily support multi-node clustering for automatic failover availability or
load balancing.
• SAS improves drive addressability and connectivity using an expander that enables one or
more SAS host controllers to connect to a large number of drives. Each expander allows
connectivity to 128 physical links, which may include other host connections, other SAS
expanders or hard disks. This highly scalable connection scheme enables enterprise-level
topologies that easily support multi-node clustering for automatic failover availability or
load balancing
PCI Express Solution
 Advanced Switching with PCI Express

• Signals take place at link level

• Allows for QoS and fan out capabilities
• Utilizes system bandwidth

• Due to the need for growing data transfer rates among

IO devices, the original PCI Architecture has become
0

outdated
• A new model of PCI, called PCI Express will replace
the dated architecture giving it life for another decade
IO Channel
Input/output channel. Alternatively referred to as the
input channel and I/O channel, the input/output channel is a line
of communication between the input/output bus or memory to the
CPU or computer peripherals
The input/output processor or I/O processor is a processor that is
separate from the main processor or CPU and is designed to
handle only input/output processes for a device or the computer. ... A
more advanced I/O processor may also have memory built into it,
allowing it to perform actions and activities more quickly.
Input/Output Processor
An input-output processor (IOP) is a processor with direct memory access
capability. In this, the computer system is divided into a memory unit and number
of processors.

Each IOP controls and manage the input-output tasks. The IOP is similar to CPU
except that it handles only the details of I/O processing. The IOP can fetch and
execute its own instructions. These IOP instructions are designed to manage I/O
transfers only.
Block Diagram Of I/O Processor
Below is a block diagram of a computer along with various I/O Processors. The
memory unit occupies the central position and can communicate with each
processor.
The CPU processes the data required for solving the computational tasks. The
IOP provides a path for transfer of data between peripherals and memory. The
CPU assigns the task of initiating the I/O program.
The IOP operates independent from CPU and transfer data between peripherals
and memory.
The communication between the IOP and the devices is similar to the program
control method of transfer. And the communication with the memory is similar to
the direct memory access method.

In large scale computers, each processor is independent of other processors and

any processor can initiate the operation.

The CPU can act as master and the IOP act as slave processor. The CPU assigns
the task of initiating operations but it is the IOP, who executes the instructions, and
not the CPU. CPU instructions provide operations to start an I/O transfer. The IOP
asks for CPU through interrupt.

Instructions that are read from memory by an IOP are also called commands to
distinguish them from instructions that are read by CPU. Commands are prepared
by programmers and are stored in memory. Command words make the program
for IOP. CPU informs the IOP where to find the commands in memory.