3130704

Digital Fundamentals

Module 3:
Sequential Circuits and
Systems
 Topics to be covered
 Flip-flops
 Applications of Flip-flops
 Shift registers
 Asynchronous counters
 Synchronous counters
 Sequential counters

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 Sequential Switching Circuits
 Sequential switching circuits are circuits whose output levels at
any instant of time are dependent on the levels present at the
inputs at that time and on the state of the circuit, i.e., on the prior
input level conditions (i.e. on its past inputs)
 The past history is provided by feedback from the output back to
the input.
 Made up of combinational circuits and memory elements.
 Eg. Counters, shift registers, serial adder, etc.

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 Sequential Switching Circuits

Inputs Outputs
Combinational Circuit

Memory
elements

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 Sequential Circuits v/s
Combinational Circuits
Sequential Circuits Combinational Circuits
• In sequential circuits, the • In combinational circuits,
output variables at any instant the output variables at any
of time are dependent on the instant of time are
present input variables and on dependent only on the
the present state, i.e., on the present input variables.
past history of the system.

• Memory unit is required to • Memory unit is not required

store the past history of the in combinational circuits.
input variables in sequential
circuits.
 Sequential Circuits v/s
Combinational Circuits
Sequential Circuits Combinational Circuits
• Sequential circuits are • Combinational circuits are
slower than combinational faster because the delay
circuits. between the input and the
output is due to propagation
• Sequential delay of gates only.
circuits are
comparatively harder to
design. • Combinational circuits are
easy to design.
 Flip-flop
 A flip-flop, known formally as bistable multivibrator, has two
stable states.
 It can remain in either of the states indefinitely.
 Its state can be changed by applying the proper triggering signal.

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 Latch
 Latch is used for certain flip-flop which are non-clocked.
 These flip-flops ‘latch on’ to a 1 or a 0 immediately upon receiving
the input pulse called SET or RESET.

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 S-R Flip-Flop (Latch)
 The simplest type of flip-flop is called an S-R latch.
 It has two outputs labelled Q and Q’ and two inputs labelled S and
R. The state of the latch corresponds to the level of Q (HIGH or
LOW, 1 or 0) and Q’ is the complement of that state.
 It can be constructed using either two cross-coupled NAND gates
or two-cross coupled NOR gates.
 Using two NOR gates, an active-HIGH S-R latch can be constructed
and using two NAND gates an active-LOW S-R latch can be
constructed.
 The name of the latch, S-R or SET-RESET, is derived from the
names of its inputs.

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 NOR Gate S-R latch (Active High)
S Q

Outputs
Inputs

R Q’
Logic Symbol S R Qn Qn+1 State
0 0 0 0 No Change
R 0 0 1 1
Q
0 1 0 0
Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
Q’ 1 1 0 x Indeterminate
S
1 1 1 x (invalid)
Logic diagram

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 NAND Gate S-R latch (Active Low)

S R Qn Qn+1 State
S 0 0 0 x Indeterminate
Q 0 0 1 x (invalid)
0 1 0 1 Set
0 1 1 1
1 0 0 0
Reset
Q’ 1 0 1 0
R
1 1 0 0 No Change
Logic diagram 1 1 1 1

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 Gated S-R Latch (S-R Flip flop)
S Q
EN
R Q’ EN S R Qn Qn+1 State
Logic Symbol 1 0 0 0 0 No Change
1 0 0 1 1

S 1 0 1 0 0
Reset
Q 1 0 1 1 0
1 1 0 0 1 Set
1 1 0 1 1
EN
1 1 1 0 x Indeterminate
1 1 1 1 x (invalid)
Q’
R 0 x x 0 0
0 x x 1 1 No Change
Logic diagram

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 Gated D-Latch
D Q
EN
Q’
Logic Symbol

D EN D Qn Qn+1 State
Q 1 0 0 0
Reset
1 0 1 0
EN 1 1 0 1 Set
1 1 1 1

Q’ 0 x 0 0
0 x 1 1 No Change

Logic diagram

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 J-K Flip-Flop
J Q
EN
K Q’ EN J K Qn Qn+1 State
Logic Symbol 1 0 0 0 0 No Change
1 0 0 1 1
1 0 1 0 0
Reset
J 1 0 1 1 0
Q 1 1 0 0 1 Set
1 1 0 1 1
EN 1 1 1 0 1 Toggle
1 1 1 1 0
Q’ 0 x x 0 0
0 x x 1 1 No Change
K

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 T Flip-Flop
T Q
EN
Q’
Logic Symbol

EN T Qn Qn+1 State
T
Q 1 0 0 0
No change
1 0 1 1
1 1 0 1 Toggle
EN 1 1 1 0
0 x 0 0
Q’ 0 x 1 1 No Change

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 Registers
 As a flip-flop (FF) can store only one bit of data, a 0 or a 1, it is
referred to as a single-bit register.
 A register is a set of FFs used to store binary data.
 The storage capacity of a register is the number of bits (1s and 0s)
of digital data it can retain.

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 Registers
 Loading a register means setting or resetting the individual FFs, i.e.
inputting data into the register so that their states correspond to
the bits of data to be stored.
 Loading may be serial or parallel.
 In serial loading, data is transferred into the register in serial form
i.e. one bit at a time.
 In parallel loading, the data is transferred into the register in
parallel form meaning that all the FFs are triggered into their new
states at the same time.

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 Types of Registers
1. Buffer register
2. Shift register
3. Bidirectional shift register
4. Universal shift register

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 Shift Register
 A number of FFs connected together such that data may be shifted
into and shifted out of them is called a shift register.
 Data may be shifted into or out of the register either in serial form or
in parallel form.
 So, there are four basic types of shift registers:
1. serial-in, serial-out
2. serial-in, parallel out
3. parallel-in, serial-out
4. parallel-in, parallel-out
 Data may be rotated left or right. Data may be shifted from left to right
or right to left at will, i.e. in a bidirectional way.
 Also, data may be shifted in serially (in either way) or in parallel and
shifted out serially (in either way) or in parallel.
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 Data transmission in shift register
Serial Serial
data data
input output

Serial-in, serial-out shift-

right, shift register

Serial Serial
data data
output input

Serial-in, serial-out shift-

left, shift register

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 Data transmission in shift register
Serial
data
input

Parallel data output

Serial-in, parallel-out, shift register

Parallel data input

Parallel data output

Parallel-in, parallel-out, shift register

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 Data transmission in shift register
Parallel data input Serial
data
output

Parallel-in, serial-out, shift register

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 Serial-in, Serial-out, Shift register

Serial Input
Serial
output
D1 Q1 D2 Q2 D3 Q3 D4 Q4

> FF1 > FF2 > FF3 > FF4

CLK

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 Serial-in, Serial-out, Shift register
Using J-K Flip Flop

Serial Serial
input output
J1 Q1 J2 Q2 J3 Q3 J4 Q4

> FF1 > FF2 > FF3 > FF4

K1 Q 1’ K2 Q 2’ K3 Q 3’ K4 Q 4’

CLK

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 Serial-in, Serial-out, Shift-left, Shift register

Serial Serial
Output input
Q4 D4 Q3 D3 Q2 D2 Q1 D1

FF4 < FF3 < FF2 < FF1 <

CLK

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 Serial-in, Parallel-out, Shift register

Serial Input QA QB QC QD

D1 QA D2 QB D3 QC D4 QD

> FF1 > FF2 > FF3 > FF4

CLK

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 Parallel-in, Serial-out, Shift register
A B C D

Shift/

D1 Q1 D2 Q2 D3 Q3 D4 Q4

> FF1 > FF2 > FF3 > FF4

CLK
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 Parallel-in, Parallel-out, Shift register

A B C D

D Q D Q D Q D Q

> FF1 > FF2 > FF3 > FF4

CLK
QA QB QC QD

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 Ring Counter

D1 Q1 D2 Q2 D3 Q3 D4 Q4

> FF1 > FF2 > FF3 > FF4

Q 1’ Q 2’ Q 3’ Q 4’

CLK

J1 Q1 J2 Q2 J3 Q3 J4 Q4

> FF1 > FF2 > FF3 > FF4

K1 Q 1’ K2 Q 2’ K3 Q 3’ K4 Q 4’

CLK
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 Ring Counter
State
After
pulses Q1 Q2 Q3 Q4
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0
5 0 1 0 0
6 0 0 1 0
7 0 0 0 1

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 Asynchronous Counters v/s Synchronous
Counters
Asynchronous Counters Synchronous Counters
• In this type of counters FFs are • In this type of counters there is no
connected in such a way that the connection between the output of first
output of the first FF drives the clock FF and clock input of next FF and so on.
for the second FF, the output of the
second the clock of the third and so on.
• All the FFs are not clocked • All the FFs are clocked simultaneously.
simultaneously.
• Design and implementation is very • Design and implementation becomes
simple even for more number of states. tedious and complex as the number of
states increases.
• Main drawback of these counters is • Since clock is applied to all the FFs
their low speed as the clock is simultaneously the total propagation
propagated through a number of FFs delay is equal to the propagation delay
before it reaches the last FF. of only one FF. Hence they are faster.

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 2-bit Ripple Up-Counter using Negative Edge-
triggered Flip-Flop
1 Q1 1 Q2
Present State Next State
CLK
J1 Q1 J2 Q2 Q2 Q1 Q2 Q1

CLK 0 0 0 1
> FF1 > FF2 0 1 1 0
1 0 1 1
K1 Q 1’ K2 Q 2’
1 1 0 0

CLK

Q1 0 1 0 1 0

Q2 0 1 0

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 2-bit Ripple Down-Counter using Negative Edge-
triggered Flip-Flop
1 Q1 1 Q2
Present State Next State
CLK
Q2 Q1 Q2 Q1
J1 Q1 J2 Q2
0 0 1 1
CLK
> FF1 > FF2 1 1 1 0
1 0 0 1
K1 Q1’ K2 Q2’ 0 1 0 0

CLK

Q1 0 1 0 1 0

Q1’ 1 0 1 0 1

Q2 0 1 0

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 2-bit Ripple Up-Counter using Positive Edge-
triggered Flip-Flop
1 Q1 1 Q2
Present State Next State
CLK
Q2 Q1 Q2 Q1
J1 Q1 J2 Q2
0 0 0 1
CLK 0 1 1 0
> FF1 > FF2
1 0 1 1
K1 Q1’ K2 Q2’ 1 1 0 0

CLK

Q1 1 1 1
0 0 0

Q1’ 0 0 0
1 1 1

Q2 0 1 0

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 2-bit Ripple Down-Counter using Positive Edge-
triggered Flip-Flop
1 Q1 1 Q2
Present State Next State
CLK
J1 Q1 J2 Q2 Q2 Q1 Q2 Q1

CLK 0 0 1 1
> FF1 > FF2
1 1 1 0
1 0 0 1
K1 Q 1’ K2 Q 2’
0 1 0 0

CLK

Q1 1 1 1
0 0 0

Q2 0 1 0

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 Mod-6 Asynchronous Counter
State
After
pulses Q3 Q2 Q1
Reset(R) R = 0 for 000 to 101
0 0 0 0 0
R = 1 for 110
1 0 0 1 0 R = x for 111
2 0 1 0 0
3 0 1 1 0 R = Q3Q2Q1’ + Q3Q2Q1
4 1 0 0 0 R = Q3Q2
5 1 0 1 0
6 1 1 0 1
↓ ↓ ↓
0 0 0 0
0 0 1 0

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 Mod-6 Asynchronous Counter

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 Mod-6 Asynchronous Counter

1 Q1 1 Q2 1
Q3
R’
T1 Q1 T2 Q2 T3 Q3
CLK > FF1 > FF2 > FF3

CLRQ1’ CLRQ2’ CLRQ3’

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 Exercise
 Design Mod-10 ripple counter.
 Draw a frequency divider using JK FFs to divide input clock
frequency by a factor of 8.

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 Design of Synchronous Counters
 Step 1. Number of flip-flops:
Based on the description of the problem, determine the required
number n of the FFs - the smallest value of n is such that the
number of states N ≤ 2n and the desired counting sequence.
 Step 2. State diagram:
Draw the state diagram showing all the possible states.
 Step 3. Choice of flip-flops and excitation table:
Select the type of flip-flops to be used and write the excitation
table.
An excitation table is a table that lists the present state (PS), the
next state (NS) and the required excitations.

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 Design of Synchronous Counters
 Step 4. Minimal expressions for excitations:
Obtain the minimal expressions for the excitations of the FFs using
K-maps for the excitations of the flip-flops in terms of the present
states and inputs.
 Step 5. Logic Diagram:
Draw the logic diagram based on the minimal expressions.

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 Excitation Tables
Required Required
PS NS inputs PS NS inputs
Qn Qn+1 S R Qn Qn+1 J K
0 0 0 x
0 0 0 x
0 1 1 0
0 1 1 x
1 0 0 1
1 0 x 1
1 1 x 0
1 1 x 0
S-R FF J-K FF

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 Excitation Tables
Required Required
PS NS inputs PS NS inputs
Qn Qn+1 D Qn Qn+1 T
0 0 0
0 0 0
0 1 1
0 1 1
1 0 0
1 0 1
1 1 1
1 1 0
D FF T FF

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 Design of Synchronous 3-bit Up Counters
 Step 1. Number of flip-flops:
A 3-bit up-counter requires 3 flip-flops. The counting sequence is
000, 001, 010, 011, 100, 101, 110, 111, 000 …
 Step 2. Draw the state diagram:

000
111 001

110 010

101 011
100

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 Design of Synchronous 3-bit Up Counters
 Step 3. Select the type of flip-flops and draw the excitation table:
JK flip-flops are selected and the excitation table of a 3-bit up-
counter using J-K flip-flops is drawn as shown below.
PS NS Required excitations
Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 0 1 0 x 0 x 1 x
0 0 1 0 1 0 0 x 1 x x 1
0 1 0 0 1 1 0 x x 0 1 x
0 1 1 1 0 0 1 x x 1 x 1
1 0 0 1 0 1 x 0 0 x 1 x
1 0 1 1 1 0 x 0 1 x x 1
1 1 0 1 1 1 x 0 x 0 1 x
1 1 1 0 0 0 x 1 x 1 x 1

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 Design of Synchronous 3-bit Up Counters
 Step 4. Obtain the minimal expressions
From excitation table, J1 = K1 = 1.
K – Maps for excitations J3, K3, J2 and K2 and their minimized form are as follows:

Q 3Q 2 Q 3Q 2
Q1 00 01 11 10 Q1 00 01 11 10

0 x x 0 x x

1 1 x x 1 x x 1

J3 = Q 2Q 1 K3 = Q 2 Q 1

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 Design of Synchronous 3-bit Up Counters
Q 3Q 2 Q 3Q 2
00 01 11 10 00 01 11 10
Q1 Q1
0 x x 0 x x

1 1 x x 1 1 x 1 1 x
J2 = Q 1 K2 = Q 1

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 Design of Synchronous 3-bit Up Counters
 Step 5. Draw the logic diagram
1

J1 Q1 J2 Q2 J3 Q3

> FF1 > FF2 > FF3

K1 Q 1’ K2 Q 2’ K3 Q 3’
CLK

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 Sequence Generator (Pulse Train Generators)
1) Using Direct logic
 Inspect given pulse train
 Decide the number of unique states and minimum number of FFs
required.
 If unique states are not possible with the least number of FFs n,
then increase the number of FFs by one or more to get the unique
states.

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 Sequence Generator (Direct Logic)
Example: Generate the following pulse train using direct logic.

0 1 1 1 0 1 1 1 0

FF States FF States
Decimal 0
LSB equivalent
LSB
0 0
0 0 0 0 5 1
0 1
1 1 0 0 1 1
3
? 1 0 1 1 3
1 0 1 5
State assignment State diagram

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 Sequence Generator (Direct Logic)
PS NS Required excitations

Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 1 0 X 1 X X 0

0 1 1 1 0 1 1 X X 1 X 0

1 0 1 0 0 0 X 1 0 X X 1

J3 = Q 2 J 2 = Q 3 ’Q 1 J1 = 1
K3 = 1 K2 = 1 K1 = Q 3

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 Sequence Generator (Direct Logic)

1 J1 Q1 J2 Q2 J3 Q3

> FF1 > FF2 > FF2

K1 Q1’ 1 K2 Q2’ 1 K3 Q3’

CLK

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 Sequence Generator (Indirect Logic)
Example: Generate the following pulse train using indirect logic.

1 0 1 1 0 1 0 1 1 0 1

Q3 Q2 Q1 Output(f) States
Q 3Q 2
0 0 0 1 0 00 01 11 10
0 0 1 0 1
Q1
0 1 0 1 2 0 1 1 x
0 1 1 1 3
1 0 0 0 4 1 1 x x
1 0 1 X 5
1 1 0 X 6 f = Q2 + Q 3 ’ Q 1 ’
1 1 1 X 7

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 Sequence Generator (Indirect Logic)

1
J1 Q1 1 J2 Q2 1 J3 Q3

> FF1 > FF2 > FF2

CLK

K1 Q1’ K2 Q2’ K3 Q3’

f

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