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Chapter 6 Counter

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54 views15 pages

Chapter 6 Counter

ict

Uploaded by

alukardlibro
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Combinatorial and Sequential

Logic

Chapter 06
Counter Decounter
(Synchronous
Asynchronous)
COUNTER DECOUNTER

Introducti
on A counter is a sequential logic circuit
consisting of a set of interconnected flip-flops using
logical functions. It allows for the enumeration or
counting, according to a binary numbering system,
of the number of pulses applied to its clock input:
it receives the pulses to be counted and
continuously delivers at its output a combination, a
set of logical states, representing the number of
received pulses.
Classification of
counters
In sequential logic, counters can be described
by the following characteristics:
Based on counting mode:

Up Counters (or Incremental Counters): Count in


ascending order with each received pulse.
Down Counters (or Decremental Counters): Count
in descending order, decreasing with each pulse.

Based on internal structure:


Binary Counters: Count using the binary system (base
2), with logical states represented by bits (0 and 1).
Decimal Counters: Count using the decimal system
(base 10), simulating digits from 0 to 9.
Based on synchronized or asynchronous operation:
Synchronous Counters: All bits of the counter
change simultaneously with each clock pulse.
Asynchronous Counters: Counter bits can change
independently, with separate control signals for each
bit.
Counting Modulus:
The capacity of the counter expressing the number of
different logical states that the output value can take
over the entire counting cycle. A modulo-M counter
counts from 0 to (M-1) and 2n  1consists
 M 2n of n flip-flops such
as .
Counting Cycle:
Specifies whether the output values  Mutilize
2n all possible
combinations, counting
 M  2n in a full cycle , or
counting
These in an incomplete cycle
classifications help understand . and design
counters suitable for various applications, considering
specific counting requirements and circuit design
constraints.
Asynchronous counter
An asynchronous counter consists of n JK flip-
flops operating in T (Toggle) mode: J=K=1. These
flip-flops are cascaded, meaning the clock signal only
controls the first flip-flop, while for each of the other
flip-flops, the clock signal is provided by the output
of the immediately preceding flip-flop.
This configuration causes the flip-flops to toggle
their states with each clock pulse, effectively creating
a binary counting sequence as each flip-flop changes
state based on the toggling behavior.
odulo 16 asynchronous counter (full cycle)

one must
use
odulo 10 asynchronous counter (incomplete cycle)

asynchronous counter modulo23 10


 M 24
odulo 10 asynchronous counter (incomplete cycle)

asynchronous counter
modulo 10
23  M 24
Modulo 16 asynchronous Decounter (full cycle)
Thank You
For Your
Attention

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