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37 views20 pages

Thesis Defense Slide

Uploaded by

ridwanahmedruddra
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Hybrid SET-CMOS digital logic

inverter design using macro model


technique
Thesis Presentation

Thesis Supervisor
Nayan Sarker
Assistant Professor
Department of
Electrical and Electronic Engineering
Jatiya Kabi Kazi Nazrul Islam University

Department of Electrical and Electronic Engineering


Jatiya Kabi Kazi Nazrul Islam University
Presented by

S.M Safoun Masruk Md. Sumon Hossen


ID : 18102918 ID : 19102908
SESSION : 2017-18 SESSION : 2018-19

Department of Electrical and Electronic Engineering


Jatiya Kabi Kazi Nazrul Islam University
Table of
Content
1. Introduction

2. Methodology

3. Result & Discussion

4. Conclusion

5. Future Scope
Introduction
The name of our thesis is “Hybrid SET-CMOS digital logic inverter design using macro
model technique.

Here we have used an equivalent circuit of Single Electron Transistor (SET) and a CMOS
inverter to make a hybrid model of the inverter circuit.

Reasons behind the uses of Single Electron Transistor with CMOS :

We know the traditional CMOS inverter offers low power dissipation, good noise
immunity, high gain, high speed and nano-scaling.

But when we make an inverter using the combination of SET and CMOS , it provides
ultralow power dissipation, nanoscale feature size, excellent performance in the low
voltage range, high speed and high gain also.
1
1
What is Single Electron Transistor (SET)?

SET is a quantum device that operates by


controlling the flow of individual electrons
through a quantum dot, which is a tiny island
isolated by tunnel barriers.

The SET utilizes the Coulomb blockade effect,


where the addition of a single electron to the
quantum dot creates a significant electrostatic
energy that blocks further electron flow unless
the energy barrier is overcome. Figure : Schematic of
SET
This phenomenon allows the SET to act as a
switch, where current flows only when specific
conditions are met. 1
2
Because of their incredibly small size—
typically at the nanoscale—SETs are able to
manipulate individual electrons.

SETs hold promise for applications in ultra-low


power electronics, quantum computing, and
single-electron memory. They offer high
sensitivity and potential for extremely dense,
energy-efficient circuits.

Figure : Schematic of
SET 1
3
Methodology

There are some limitations of SET, such as high cost, large processing time, extremely
low operating temperatures, and fabrication challenges.

To overcome those limitations the researchers proposed equivalent circuits called macro-
model.

By studying a lot of papers, we have found mainly two kinds of equivalent circuits of SET.

1
4
To overcome those limitations the
researcher Yu proposed a compact
macro-model for SET.

Figure : Proposed macro-model of Yu et


al

1
5
Wu and Lin proposed another macro-
model of SET.

To make this model more efficient, two


diodes have been used on the place of
R4 of yu’s model.

Figure : Proposed macro-model of Wu and


Lin

1
6
Proposed Hybrid SET-CMOS inverter
circuit :

In our proposed model, we have made an


inverter circuit with the combination of SET and
CMOS.

In this model, the NMOS is replaced by SET


macro-model and PMOS is connected above it as
per conventional CMOS inverter.

In our inverter circuit, we eliminated the resistor


R4 of the macro-model proposed by Yu to make Figure : Proposed inverter
the circuit simpler and the desired inverter circuit circuit
has been successfully implemented.
1
7
Here, the function of two combinations, R2-V1-D1
and R3-V2-D2 are to control current in both
positive and negative direction for different
values of gate voltage.

When the gate input voltage is low, the PMOS is


on and SET is off. As SET is off, it offers high
impedance. Due to this reason high output
voltage is obtained.

Similarly, when high input voltage is applied to


the gate terminal, opposite phenomena happens Figure : Proposed inverter
and low output voltage is obtained at the output circuit
terminal.
1
8
Result &
Discussion
The input voltage signal is given in common
gate of PMOS and SET, the output voltage
from common drain terminal of the circuit.

We have given 0.04 volt as the supply


voltage.

The resultant output of this inverter is high


when input is low and vice versa as per Figure: Input - Output Characteristics of the proposed model
conventional CMOS Inverter.

1
9
In this macro modelled circuit of inverter,
the output power can be changed by
changing the resistor value R1.

With the increase in resistance values of R1,


the drain current as well as power
consumption are changing simultaneously.

Figure : Proposed inverter circuit

1
1
0
V-P characteristics

We have changed the value of R1 three


times in our proposed model and observed
that the output power changes each time by
varying the gate voltage from 0.5 to 5 volts.

By plotting the gate voltage along the X-axis


and the output power along the Y axis, we
get the following graph.
Figure : Output power characteristics for
different values of resistance R1 and different
gate voltages.
1
1
1
V-I characteristics

We have changed the value of R1 three


times in our proposed model and observed
the V-I characteristics by varying the gate
voltage from 0.5 to 5 volts.

By plotting the gate voltage along the X-axis


and output current along the Y axis, we get
the following graph.
Figure : Vds and Ids graph for different values of
resistance R1.

1
1
2
Advantages of hybrid SET-CMOS inverter over today’s advance
CMOS inverter

Voltage Levels : Hybrid SET-CMOS can operate at extremely low voltages (0.1 V or
lower), where advance CMOS operates at higher voltages (0.7 V - 5 V).

Variation of Power Consumption : In the proposed hybrid SET-CMOS circuit we


can change power consumption by varying the resistance R1 without changing gate
voltage. But for CMOS, there is no option to vary power consumption.

Power Consumption : Extremely low power consumption due to SETs' ability to


control individual electrons. But CMOS’s power consumption is higher than hybrid
SET-CMOS. 1
1
3
Advantages of hybrid SET-CMOS inverter over today’s advance
CMOS inverter

Device Density : The device density of hybrid SET-CMOS inverter is higher than
advance CMOS inverter.

Noise immunity : Hybrid SET-CMOS inverter provides higher noise immunity than
advance CMOS inverter.

Scalability : Hybrid SET-CMOS Offers better scalability in theory, but practical


implementation faces fabrication challenges. On the other hand, the scability
challenge is more complicated than hybrid SET-CMOS inverter design.
1
1
4
Conclusion
The macro modeling of Single Electron Transistor (SET) provides a fresh
direction in nanodevice research. One of the main characteristics of
advanced computing in Single Electron Transistor topology that comes with
the post-CMOS era is the suggested inverter model.

The SET macro-model, which replaces NMOS, provides ultralow power


dissipation, nanoscale feature size, and excellent performance in the low
voltage range. Its use in PMOS results in high gain, high current drive, high
response speed, considerably more sophisticated fabrication, and acceptance
within the digital family.

Most importantly, because simulation is carried out using a single piece of


software, it can be easily designed and developed, which is highly favored by 1
researchers. 1
5
Future
Scope
It faces fabrication challenges for practical implementation.

If we can overcome these challenges and make this device


easier to build, then it will be a promising invention for the
electronic industry because of its characteristics like ultralow
power dissipation, nanoscale feature size, excellent
performance in the low voltage range, high speed and high
gain, high noise immunity.

1
1
6
Thanks!
Do you have any question, feel free to ask.

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