F

Chapter 2

Combinational Logic
Circuits
Binary Logic and Gates
Boolean Algebra
A

Based on “Logic and Computer Design

Fundamentals”, 4th ed., by Mano and 1
Overview Chapter 2
• Binary Logic and Gates
• Boolean Algebra
• Standard Forms
• Two-Level Optimization
• Map Manipulation
• Other Gate Types
• Exclusive-OR Operator and Gates
• High-Impedance Outputs

2
2-1 Binary Logic and Gates
 Binary logic deals with binary variables
(i.e. can have two values, “0” and “1”)
 Binary variables can undergo three basic
logical operators AND, OR and NOT:

• AND is denoted by a dot (·)

• OR is denoted by a plus (+).
• NOT is denoted by an overbar ( ¯ ), a
single quote mark (') after the variable.

3
 Operator Definitions and Truth
Tables
 Truth table - a tabular listing of the values of a
function for all possible combinations of values
on its arguments
 Example: Truth tables for the basic logic
operations:
AND OR NOT
X Y Z = X·Y X Y Z = X+Y X Z=X
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1
1 1 1
4
Boolean Operator Precedence
 The order of evaluation in a Boolean
expression is:
1. Parentheses
2. NOT
3. AND
4. OR
 Consequence: Parentheses appear
around OR expressions
 Example: F = A(B + C)(C + D)

5
Logic Gates
 In the earliest computers, switches were opened
and closed by magnetic fields produced by
energizing coils in relays. The switches in turn
opened and closed the current paths.
 Later, vacuum tubes that open and close current
paths electronically replaced relays.
 Today, transistors are used as electronic
switches that open and close current paths.
 Optional: Chapter 6 – Part 1: The Design
Space

6
 Logic Gate Symbols and
Behavior
 Logic gates have special symbols:
X X
Z 5 X ·Y Z5 X1 Y X Z5 X
Y Y
AND gate OR gate

(a) Graphic symbols

 And waveform behavior in time as follows:
X 0 0 1 1

Y 0 1 0 1

(AND) X · Y 0 0 0 1

(OR) X1 Y 0 1 1 1

(NOT) X 1 1 0 0
(b) Timing diagram
7
Gate Delay

 In actual physical gates, if one or more input

changes causes the output to change, the output
change does not occur instantaneously.
 The delay between an input change(s) and the
resulting output change is the gate delay denoted
by tG:

1
Input
0
tG tG tG = 0.3 ns
1
Output
0
0 0.5 1 1.5 Time (ns)
8
Logic Diagrams and Expressions
Example: Alarm system for a dorm room

“The alarm should go off when the door opens OR when

the door is closed AND the motion detector goes off.

Inputs: “A” door A=1 (open door), B=0 (closed)

“B” motion detector, B=1 (motion detected)
Output: F
F = A + A.B

Logic Diagram A

B
9
 2-2 Boolean Algebra

George Boole,
Mathematician (self-taught),
Professor of Mathematics of then
Queen's College, Cork in Ireland)

(Encycl. Brittannica online: http://www.britannica.com/)

10
 2-2 Boolean Algebra
 Boolean algebra deals with binary variables and
a set of three basic logic operations: AND (.), OR
(+) and NOT ( ) that satisfy basic identities

Basic identities
1. X + 0= X 2. X. 1=X Existence 0 and 1 or
3. X+ 1=1 X . 0=0 operations with 0 and 1
4.
5. X + X= X 6. X .X =X Idempotence
7. X + X=1 8. X .X =0 Existence complements
9. X = X Involution

Replace “+” by “.”, “.” by +,

Dual “0” by “1” and “1’’ by”0”
11
 Boolean Algebra
Boolean Theorems of multiple variables
10. X + Y =Y + X Commutative 11. XY =YX
12. (X + Y) + Z = X + (Y+ Z) Associative 13. (XY)Z =X(YZ )
14. X (Y+ Z) = XY+XZ Distributive 15. X+ YZ = (X + Y)(X + Z)

16. X + Y = X . Y DeMorgan’s 17. X . Y = X + Y

Dual

12
Example: Boolean Algebraic Proof
 A + A·B = A (Absorption
Theorem)
Proof Steps Justification
(identity or theorem)
A + A·B
=A·1+A·B (Operation with 1)
= A · ( 1 + B) (Distributive Law)

=A·1 (Operation with 1)

=A
13
 Exercise
 Simplify Y+X’Z+XY’ using Boolean
algebra Justification
Y+X’Z+XY’ (COMMUTATIVE Property)
= Y+XY’+X’Z (Distributive)
=(Y+X)(Y+Y’) + X’Z (Existence compl.)

=(Y+X).1 + X’Z (0peration with 1)

= Y+X+X’Z (Distributive)
=Y+(X+X’)(X+Z) (Existence compl.)
=Y+1.(X+Z) = X+Y+Z (Operation with 1)

14
 Complementing Functions
 Use DeMorgan's Theorem to
complement a function:
1. Interchange AND and OR
operators
2. Complement each constant value and
literal

15
 Example: DeMorgan’s theorem

Exercise: find G
F = AB + C (E+D)
G = UX(Y+VZ)

Find F
F = AB + C (E+D)

F = AB . C (E+D)
Answer:
F = (A+B) .(C + (E+D)) G = U’+X’ + Y’V’+Y’Z’
F = (A+B) .(C + E.D)

16
Exercise

Example: Complement G = (a + bc)d + e

G=

17
Other useful Theorems
Dual
 XY + XY = Y Minimization (X + Y)(X + Y) = Y

 X + XY = X Absorption X(X + Y) = X

 X + XY = X + Y Simplification X(X + Y) = XY

 XY + XZ + YZ = XY + XZ Consensus

(X + Y)( X + Z)(Y + Z) = (X + Y)( X + Z)

18
Proof the Consensus Theorem
 AB + AC + BC = AB + AC (Consensus Theorem)
Proof Steps Justification (identity or theorem)
AB + AC + BC
= AB + AC + 1 · BC operation 1
= AB +AC + (A + A) · BC existence
= AB + AC + ABC + ABC distributive
= AB + ABC + AC + ABC commutative
= AB(1+BC) + AC(1+B) distributive
= AB.1 + AC.1 operation with 1
= AB + AC operation with 1

19
 General Strategies
1. Use idempotency to eliminate terms:
X + X =X X . X=X

2. Complimentarily orX existence

+ X=1 X . X=0
complements:
X + XY = X X(X + Y) = X
3. Absorption: X + XY = X + Y X(X + Y) = XY
4. Adsorption: X + Y =X .Y X . Y =X + Y
5. DeMorgan: XY + XZ + YZ = XY + XZ
6. Consensus: (X + Y)( X + Z)(Y + Z) = (X + Y)( X + Z)
20
2-3 Standard (Canonical) Forms
 It is useful to specify Boolean
functions in a form that:
• Allows comparison for equality.
• Has a correspondence to the truth
tables
 Canonical Forms in common usage:
• Sum of Products (SOP), also called Sum
or Minterms (SOM)
• Product of Sum (POS), also called
Product of Maxterms (POM)

21
Minterms
 Minterms are AND terms with every variable
present in either true or complemented form.
 Example: Two variables (X and Y)produce
2 x 2 = 4 minterms:
XY
XY
XY
XY
 Given that each binary variable may appear normal
(e.g., x) or complemented (e.g., x ), there are 2n
minterms for n variables.

22
Maxterms
 Maxterms are OR terms with every variable in
true or complemented form.
 There are 2n maxterms for n variables.
 Example: Two variables (X and Y) produce
2 x 2 = 4 combinations:

X +Y
X +Y
X +Y
X +Y

23
Maxterms and Minterms
 Examples: Two variable minterms and
maxterms.
Index Minterm Maxterm
0 (00) xy x+y
1 (01) xy x+y
2 (10) xy x+y
3 (11) xy x+y
 The index above is important for describing
which variables in the terms are true and which
are complemented.

24
Purpose of the Index
 For Minterms:
• “1” in the index means the variable is “Not
Complemented” and
• “0” means the variable is “Complemented”.
 For Maxterms:
• “0” means the variable is “Not Complemented”
and
• “1” means the variable is “Complemented”.

25
 Index Examples – Four Variables
Index Binary Minterm Maxterm
i Pattern mi Mi

form
order in a standard
are in alphabetical
Notice: the variables
0 0000 abcd abcd
1 0001 abcd ?
3 0011 ? a+b+c+d
5 0101 abcd a+b+c+d
7 0111 ? a+b+c+d
10 1010 abcd a+b+c+d
13 1101 abcd ?
15 1111 abcd a+b+c+d
Relationship between min and MAX term?
M i = mi mi = M i 26
 Implementation of a function with
minterms
Function F1(x,y,z) defined by its truth table:
x y z index F1
000 0 0
001 1 1 F1 = x’ y’ z + x y’ z’ + x y z
010 2 0
011 3 0 Thus F1 = m1 + m4 + m7
100 4 1
101 5 0
110 6 0 Short hand notation: F1 = (1,4,7)
m
111 7 1
also called, little m notation

27
Minterm Function Example
 F(A, B, C, D, E) = m2 + m9 + m17 + m23
 F(A, B, C, D, E) write in standard form:
A’B’C’DE’ + A’BC’D’E + AB’C’D’E + AB’CDE
m2 m9 m17 m23

 Sum of Product (SOP) expression:

• F = Σm(2, 9, 17, 23)

28
 Converting a function into a
SOP form: F(A,B,C) = A+B’C
 Write the function as a canonical SOP (with minterms)
 There are three variables, A, B, and C which we take to
be the standard order.
 To add the missing variables:
“ANDing” any term that has a missing variable
with a term 1=( X + X’).
 F=A+B’C = A(B+B’)(C+C’) + B’C(A+A’)
= ABC + ABC’ + AB’C + AB’C’ + AB’C + A’B’C
= ABC + ABC’ + AB’C + AB’C’ + A’B’C
= m7 + m6 + m5 + m4 + m1
= m1 + m4 + m5 + m6 + m7

29
Expressing a function with
Maxterms
 Start with the SOP: F1(x,y,z) =m1 + m4 + m7
 Thus its complement F1can be written as
• F1 = m0 +m2 +m3 + m5 + m6 (missing term of F1)
 Apply deMorgan’s theorem on F1:
• (F1 = (m0 +m2 +m3 + m5 + m6)
= m0.m2.m3.m5.m6
= M0.M2.M3.M5.M6
= ΠM(0,2,3,5,6) also called, Big M notation
Thus the Product of Sum terms (POS):
F1 = (x + y + z) ·(x + y + z)·(x+ y + z)
·(x + y + z)·(x + y + z)
30
Canonical Product of Maxterms
 Any Boolean Function can be expressed as a
Product of Sums (POS) or of Maxterms (POM).
• For an expression, apply the second
distributive law , then “ORing” terms
missing variable x with a term equal to
0=(x.x’) and then applying the distributive
law again.
F(A,B,C)= A+A’B’
Apply the distributive law:
F= A+A’B’ = (A+A’)(A+B’)
= 1.(A+B’)
Add missing variable C: F= A+B’+CC’
= (A+B’+C)(A+B’+C’)
= M2.M3 31
Alternatively: use Truth Table
 For the function table, the maxterms used
are the terms corresponding to the 0's.
F(A,B,C)= A+A’B’
ABC F
000 1
001 1
010 0 M2 F = M2.M3
011 0 M3
= (A+B’+C)(A+B’+C’)
100 1
101 1
110 1
111 1
32
Function Complements
 The complement of a function expressed as a
sum of minterms is constructed by selecting the
minterms missing in the sum-of-product
canonical forms.
 Alternatively, the complement of a function
expressed by a Sum of Products form is simply
the Product of Sums with the same indices.
 Example: Given
F ( x , y , z ) = Sm ( 1, 3 , 5 , 7 )
F( x, y , z ) = Sm(0, 2,4,6)
F( x, y , z ) = PM(1, 3,5,7 )

33
A Simplification Example
 Simplify F F( A , B, C) m(1,4,5,6,7 )
 Writing the minterm expression:
F = A’ B’ C + A B’ C’ + A B C’ + AB’C + ABC
 Simplifying using Boolean algebra:
F=

34
2-4 Circuit Optimization
 Goal: To obtain the simplest
implementation for a given function
 Optimization requires a cost criterion to
measure the simplicity of a circuit
 Distinct cost criteria we will use:
• Literal cost (L)
• Gate input cost (G)
• Gate input cost with NOTs (GN)

35
 Literal Cost
 Literal – a variable or its complement
 Literal cost – the number of literal
appearances in a Boolean expression
corresponding to the logic circuit
diagram
 Examples (all the same function):
• F = BD + AB’C + AC’D’ L=8
• F = BD + AB’C + AB’D’ + ABC’ L=
• F = (A + B)(A + D)(B + C + D’)( B’ + C’ + D) L=
• Which solution is best?

36
 Gate Input Cost
 Gate input costs - the number of inputs to the gates in the
implementation corresponding exactly to the given equation
or equations. (G - inverters not counted, GN - inverters counted)
 For SOP and POS equations, it can be found from the
equation(s) by finding the sum of:
• all literal appearances
• the number of terms excluding single literal terms,(G) and
• optionally, the number of distinct complemented single literals (GN).
 Example:
• F = BD + A BC + A C D G = 8, GN = 11
• F = BD + A BC + A B D+ AB C G = , GN =
• F = (A + B)(A + D)(B + C + D)( B + C+ D) G = , GN =
• Which solution is best?
37
 Cost Criteria (continued)
 Example: A
 F = A B C + A’B’C’ B
C
L = 6 G = 8 GN = 11 F
 F = (A +C’)(B’+ C)(A’+B)
L = 6 G = 9 GN = 12
 Same function and same
A
literal cost B
 But first circuit has better C
gate input count and better F
gate input count with NOTs
 Select it!

38
 Karnaugh Maps (K-maps)

Maurice Karnaugh (October 4, 1924)

is an American physicist, who
introduced the Karnaugh map while
working at Bell Labs

Source: http://en.wikipedia.org/wiki/File:Eugeneguth.jpg
39
Karnaugh Maps (K-map)
 A K-map is a collection of squares
• Each square represents a minterm
• The collection of squares is a graphical representation
of a Boolean function
• Adjacent squares differ in the value of one variable
• Alternative algebraic expressions for the same function
are derived by recognizing patterns of squares
 The K-map can be viewed as
• A reorganized version of the truth table
• A topologically-warped Venn diagram as used to
visualize sets in algebra of sets

40
 Two Variable Maps
y=0 y=1
Truth Table of F(x,y)
K-map m0 = m1 =
x y F x=0
0 0 0 m0 xy xy
0 1 1 m1 x = 1 m2 = m3 =
xy xy
1 0 0 m2
1 1 1 m3 y=0 y=1

x=00 1

x=10 1
F= m1 +m3 = x’y + xy = (x+x’)y = y

41
K-Map Function Representation
 Example: G(x,y) = xy’ + x’y + xy

G y=0y=1
x=0 0 1

x=1 1 1

 Simplify using theorems:

G = x (y’+y) + x’y = x.1 +x’y = x + x’y = x + y

 Simplify using K-map: cover adjacent cells

42
 Three Variable Maps
 A three-variable K-map:
yz=00 yz=01 yz=11 yz=10
x=0 m0 m1 m3 m2
x=1 m4 m5 m7 m6
 Where each minterm corresponds to the product
terms:
yz=00 yz=01 yz=11 yz=10
x=0 x y z xyz xyz xyz
x=1 x y z x y z xyz xyz
 Note that if the binary value for an index differs in
one bit position, the minterms are adjacent on the
K-Map
43
Three variable K-map

yz
x y
0 1 3 2

4 5 7 6
x
z

44
 Example Functions
 By convention, we represent the minterms of F by
a "1" in the map and a “0” otherwise
y
 Example:
F
F(x, y, z) m(2,3,4,5) 0 1 3
1 2
1
x 4 5 7 6
1 1
 Example:
z
y
G
G(x,y,z)  m(3,4,6,7) 0 1 3 2

x 4 5 7 6

z

45
Example: Combining Squares
 Example: Let F m(2,3,6,7) y
0 1 3 2
1 1
x 4 5 7 6
1 1
z
 Applying the Minimization Theorem three
times: m2 +m3 +m6 +m7
F(x, y, z) = x y z + x y z + x y z + x y z
= yz + yz
 =y
Thus the four terms that form a 2 × 2 square
correspond to the term "y".
46
 Three Variable Maps
Use the K-Map to simplify the following
Boolean function

F(x, y, z) m(1,2,3,5,7)
y
0 1 3 2

x 4 5 7 6

F(x, y, z) = ?
47
Four-Variable Maps
 Variables A,B,C and D
C
0 1 3 2

4 5 7 6

12 13 15 14 B
A
8 9 11 10

D
Notice: only one variable changes for adjacent boxes
48
Four-Variable Maps
 Example F= =m (0,2,3,5,6,7,8,10,13,15)
C
0 1 3 2
1 1 1

4 1 5 1 7 1 6

12 1 13 1 15 14 B
A
1 8 9 11 1 10

D
F= BD + A’C + B’D’ 49
Four-Variable Map Simplification
F(W, X, Y, Z) = Sm(0,2,4,5,6,7,
8,10,13,15)

0 1 3 2

4 5 7 6

12 13 15 14 B
A
8 9 11 10

D
F=
50
 2-5 Map Manipulation:
Systematic Simplification
 A Prime Implicant is a product term obtained by
combining the maximum possible number of adjacent
squares in the map into a rectangle with the number of
squares a power of 2.
 A prime implicant is called an Essential Prime Implicant
if it is the only prime implicant that covers (includes)
one or more minterms.
 Prime Implicants and Essential Prime Implicants can be
determined by inspection of a K-Map.

51
 Example of Prime Implicants
 Find ALL Prime Implicants
CD ESSENTIAL Prime Implicants
C C
BD BD
1 1 1 1 1 1

BD 1 1 BD 1 1
B B
1 1 1 1
A A
1 1 1 1 1 1 1 1
AB
D D
AD Minterms covered by single prime implicant
BC
52
Optimization Algorithm
 Find all prime implicants.
 Include all essential prime implicants
in the solution
 Select a minimum cost set of non-
essential prime implicants to cover
all minterms not yet covered

53
 Selection Rule Example
 Simplify F(A, B, C, D) given on the K-
map. Selected Essential
C C

1 1 1 1

1 1 1 1 1 1 1 1
B B
1 1
A A
1 1 1 1

D D
Minterms covered by essential prime implicants
Minterm covered by one prime implicant
F=?
55
Exercise
 Find all prime, essential implicants
for: G(A, B, C, D) m(2,3,4,7,12,13,14,15)
• Give the minimized SOP implementation
C

B
A

D
56
Don't Cares in K-Maps
 Sometimes a function table or map contains entries
for which it is known:
• the input values for the minterm will never occur, or
• The output value for the minterm is not used
 In these cases, the output value need not be defined
 Instead, the output value is defined as a “don't care”
 By placing “don't cares” ( an “x” entry) in the function
table or map, the cost of the logic circuit may be
lowered.
 Example 1: A logic function having the binary codes
for the BCD digits as its inputs. Only the codes for 0
through 9 are used. The six codes, 1010 through 1111
never occur, so the output values for these codes are
“x” to represent “don’t cares.”

57
 Don’t care example
WXYZ Digit a b
 BCD code on a 0000 0 1 1
a=Σm(0,2,3,5,6,7,8,9)+ Σ
seven segment 0001 1 0 1 d(10,11,12,13,14,15)
display: 0010 2 1 1 Y
0011 3 1
0100 4 0 1 1 1
0101 5 1
0110
0111
6
7
1
1
1 1 1
X
1000 8 1
1001 9 1 X X X X
outputs
1010 - X W
a b c d… g 1011 X 1 1 X X
? 1100 X
1101 X Z
WXYZ 1110 X
Input (BCD) 1111 X a=?
58
 Find SOP for segment “a”
a=Σm(0,2,3,5,6,7,8,9)+ Σ d(10,11,12,13,14,15)

a=? Y

1 1 1
1 1 1
X
X X X X
W
1 1 X X

59
Product of Sums Example
 Find the optimum POS solution:
F(A, B, C, D) m(3,9,11,12 ,13,14,15) 
d (1,4,6)
• Hint: Use F’ and complement it to get
the result.

60
 Product of Sums Example
 Find the optimum POS solution:
F(A, B, C, D) m(3,9,11,12 ,13,14,15)  d (1,4,6)
C Find prime implicants for F’
0 x 1 0 A’B, B’D’, A’C;

x 0 0 x F’=A’B + B’D’
B
1 1 1 1
Use DeMorgan’s to find F as POS
A
0 1 1 0
Thus F=(A+B’) (B+D)
D

61
 Exercises with don’t cares

 F(A,B,C,D)=Σm(2,5,8,10,13,14) +Σd(0,1,6)

 Write F as minimized SOP:

• F=

 Write F as minimized POS

• F=

62
Exercise: Design a 2-bit comparator
 Design a circuit that has two 2–bit numbers N1
and N2 as inputs, and generates three outputs to
indicate if N1<N2, N1=N2 and N1>N2.

(N1=N2) N1=AB
A F1
B N1 N2=CD
F2 (N1<N2)
N2 F3
C (N1>N2)
D

 Design the circuit as minimized SOP

63
Design a 2-bit comparator - Solution

64
Design a 2-bit comparator - Solution

65
2-8 Other Gate Types
 Why?
• Easier to implement on a chip than the AND, OR
gates
• Convenient conceptual representation

(IBM)
A
B

A
B

(Intel)

66
Other Gate Types: overview

A A A A
A
B B B B
A B BUF NAND NOR XOR XNOR

0 0 0 1 1 0 1
0 1 0 1 0 1 0
1 0 1 1 0 1 0
1 1 1 0 0 0 1

67
 Buffer
 A buffer is a gate with the function F = X:

X F

 In terms of Boolean function, a buffer is the

same as a connection!
 So why use it?
• A buffer is an electronic amplifier used to
improve circuit voltage levels and increase the
speed of circuit operation.

68
 NAND Gates X
Y
Z

 The NAND gate is the natural

implementation for CMOS technology in
terms of chip area and speed.
 Universal gate - a gate type that can
implement any Boolean function.
 The NAND gate is a universal gate:
• NOT implemented with NAND:
• AND implemented with NAND gate:
• OR using NAND:

69
 NOR Gates A
B

 Similary as the NAND gate, the NOR gate is

a Universal gate
 Universal gate - a gate type that can
implement any Boolean function.
 With a NOR gate one can implement
• A NOT
• An AND
• An OR

70
 2-9 Exclusive OR/ Exclusive NOR

 The eXclusive OR (XOR) function is an important

Boolean function used extensively in logic
circuits:
• Adders/subtractors/multipliers
• Counters/incrementers/decrementers
• Parity generators/checkers
 The eXclusive NOR function (XNOR) is the
complement of the XOR function
 XOR and XNOR gates are complex gates (built
from simpler gates, such as AND, Not, etc).

71
 Truth Tables for XOR/XNOR
 XOR XNOR
X Y XÅY X Y (XÅY)
or XºY
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
 The XOR function means:
X OR Y, but NOT BOTH
 The XNOR function also known as the equivalence
function, denoted by the operator 

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XOR Implementations
 The simple SOP implementation uses the
following structure: X

X ÅY = XY +XY X Y

Y
 A NAND only implementation is:
X

X Y

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 Odd and Even Functions
 The odd and even functions on a K-map form
“checkerboard” patterns.
 The 1s of an odd function correspond to minterms having
an index with an odd number of 1s.
 The 1s of an even function correspond to minterms
having an index with an even number of 1s.
 Implementation of odd and even functions for greater than
four variables as a two-level circuit is difficult, so we use
“trees” made up of :
• 2-input XOR or XNORs
• 3- or 4-input odd or even functions

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Example: Odd Function Implementation
 Design a 3-input odd function F = X Y+ Z+
with 2-input XOR gates
 Factoring, F = (X +Y) +Z
 The circuit:

X
Y
F
Z

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Example: 4-Input Function Implementation
 Design a 4-input odd function F = W X+ Y+ +Z
with 2-input XOR and XNOR gates
 Factoring, F = (W +X) +(Y +Z)
 The circuit:

W
X
F
Y
Z

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 Parity Generators and
Checkers
 In Chapter 1, a parity bit added to n-bit code to
produce an n + 1 bit code:
• Add odd parity bit to generate code words with even
parity
• Add even parity bit to generate code words with odd
parity
• Use odd parity circuit to check code words with even
parity
• Use even parity circuit to check code words with odd
parity

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 Parity Generators and
Checkers
 Example: n = 3. Generate even parity code words of length four
with odd parity generator:
0
X 01
Y 01
0 X 1
E
Z Error
0 Y 1
P =1 P
1 Z
 Check even parity code words of length four with odd parity
checker

 Operation: (X,Y,Z) = (0,0,1) gives (X,Y,Z,P) = (0,0,1,1) and E = 0.

If Y changes from 0 to 1 between generator and checker, then E =
1 indicates an error.

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 2-10 Hi-Impedance Outputs
 Logic gates introduced thus far
• have 1 and 0 output values,
• cannot have their outputs connected together, and
• transmit signals on connections in only one direction.
 Three-state (or Tri-state) logic adds a third logic
value, Hi-Impedance (Hi-Z), giving three states:
0, 1, and Hi-Z on the outputs.
 What is a Hi-Z value?
• The Hi-Z value behaves as an open circuit
• This means that, looking back into the circuit, the
output appears to be disconnected.

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 The Tri-State Buffer
Symbol  For the symbol and truth table,
IN IN is the data input, and EN,
OUT the control input.
 For EN = 0, regardless of the
EN
value on IN (denoted by X),
the output value is Hi-Z.
Truth Table  For EN = 1, the output value
EN IN OUT follows the input value.
0 X Hi-Z  Variations:
• Data input, IN, can be inverted
1 0 0 • Control input, EN, can be
1 1 1 inverted
by addition of “bubbles” to signals.
OUT= IN.EN
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 Tri-State Logic Circuit
 Data Selection Function: If s = 0, OL = IN0, else OL = IN1
 Performing data selection with 3-state buffers:

IN0

EN0 OL
S OL= IN0.S’ + IN1.S
IN1
EN1

 Since EN0 = S and EN1 = S, one of the two buffer outputs is always
Hi-Z plus the last row of the table never occurs.

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Exercise
 Implement a gate with two three-state
buffers and two inverters:
• F = XÅY=XY’+X’Y

EN0=Y’ F
Y
X’

EN1=Y

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Other usage of Tristate buffers
 Tristate bus connecting multiple chips:

from bus
Processor
To bus

Shared bus
EN1

from bus
Memory
To bus
EN2

from bus
Video
To bus
EN3

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