VLSI Design and Testing

BEC602
1. Principals of CMOS VLSI Design A System approach
Neil H E Weste and Kamran Eshraghain .
Addition Wisley Publishing company.
2. CMOS Digital Integrated Circuits: Analysis and Design”,
Sung Mo Kang & Yosuf Leblebici,
Third Edition, Tata McGraw-Hill

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Course objectives:
 1.This course deals with analysis and design of digital CMOS
integrated circuits.
 2. The course emphasizes on basic theory of digital circuits, design
principles and techniques for digital design blocks
implemented in CMOS technology.
 3. This course will also cover switching characteristics of digital
circuits along with delay and power estimation.
 4. Understanding the CMOS sequential circuits and memory
design concepts.
 5.Explore the knowledge of VLSI Design flow and Testing

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  MODULE-1
 Introduction to CMOS Circuits: Introduction, MOS Transistors, MOS Transistor
switches, CMOS Logic, Alternate Circuit representation, CMOS-nMOS comparison.
[Text 1: 1.1,1.2,1.3,1.4,1.5.1.6.]
 MODULE-2
 MOS Transistor Theory: n-MOS enhancement transistor, p-MOS transistor,
Threshold Voltage, Threshold voltage adjustment, Body effect, MOS device
design equations, V-I characteristics, CMOS inverter DC characteristics, Influence
of βn / βp ratio on transfer characteristics, Noise margin, Alternate CMOS
inverters. Transmission gate DC characteristics. Latch-up in CMOS. [Text 1:
2.1,2.2,2.3,2.4,2.5.2.6.]
 MODULE-3
 CMOS Process Technology: Silicon Semiconductor Technology, CMOS
Technologies, Layout Design Rules. [Text 1: 3.1,3.2,3.3.]
 Circuit Characterization and Performance Estimation: Introduction, Resistance
Estimation, Capacitance Estimation, Switching Characteristics, CMOS gate
transistor sizing, Determination of conductor size, Power consumption, Charge
sharing, Scaling of MOS transistor sizing, Yield. [Text 1:
4.1,4.2,4.3,4.4,4.5.4.6.4.7,4.8,4.9,4.10]
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  MODULE-4
 CMOS Circuit and Logic Design: Introduction, CMOS Logic
structures, CMOS Complementary logic, Pseudo n-MOS logic,
Dynamic CMOS logic, Clocked CMOS Logic, Cascade Voltage
Switch logic, Pass transistor Logic, Electrical and Physical design
of Logic gates, The inverter, NAND and NOR gates, Body effect,
Physical Layout of Logic gates, Input output Pads.
 [Text 1: 5.1,5.2,5.2.1, , 5.2.2, 5.2.3, 5.2.4, 5.2.6, 5.2.8,
5.3,5.3.1,5.3.2, 5.3.4 ,5.3.8,5.5]
 MODULE-5
 Sequential MOS Logic Circuits: Introduction, Behaviour of
Bistable Elements (Excluding Mathematical analysis) SR Latch
Circuit, Clocked Latch and Flip-Flop Circuits, Clocked SR Latch,
Clocked JK Latch.
 [Text2: 8.1, 8.2, 8.3, 8.4]
 Structured Design and Testing: Introduction, Design Styles,
Testing
 [Text1: 6.1, 6.2. 6.5]
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Course Outcomes: After completing the course,
the students will be able to
 CO1 -Apply the fundamentals of semiconductor physics in
MOS transistors and analyze the geometrical effects of MOS
transistors
 CO2- Design and realize combinational, sequential digital
circuits and memory cells in CMOS logic.
 CO3 -Analyze the synchronous timing metrics for sequential
designs and structured design basics.
 CO4- Understand designing digital blocks with design
constraints such as propagation delay and dynamic power
dissipation.
 C05- Understand the concepts of Sequential circuits design
and VLSI testing

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 A Brief History

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A Brief History

 In 1958, Jack Kilby built the first integrated circuit flip-flop with two transistors
at Texas Instruments.
 In 2008, Intel’s Itanium microprocessor contained more than 2 billion
transistors and a 16 Gb Flash memory contained more than 4 billion
transistors.
 Annual growth rate of 53% over 50 years
 This incredible growth has come from steady miniaturization of transistors
and improvements in manufacturing processes.
 The transistors are smaller, they also become faster, dissipate less power, and
are cheaper to manufacture.
 The processing performance once dedicated to secret government super
computers is now available in disposable cellular telephones.
 The memory once needed for an entire company’s accounting system is now
carried by a teenager in her iPod.
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 A Brief History continued ….

 Improvements in integrated circuits have enabled space exploration,

made automobiles safer and more fuel efficient, revolutionized the
nature of warfare, brought much of mankind’s knowledge to our Web
browsers, and made the world a flatter place.

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 Integrated circuits became a $100 billion/year business in 1994.
 In 2007, the industry manufactured approximately 6 quintillion (6 × 10 18)
transistors, or nearly a billion for every human being on the planet.
 Thousands of engineers have made their fortunes in the field.
 New fortunes lie ahead for those with innovative ideas and the talent to bring
those ideas to reality

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A Brief History
 During the first half of the twentieth century, electronic
circuits used large, expensive, power-hungry, and unreliable
vacuum tubes.
 In 1947, John Bardeen and Walter Brattain built the first
functioning point contact transistor at Bell Laboratories.
 It was nearly classified as a military secret, but Bell Labs
publicly introduced the device the following year.
 We have called it the Transistor, T-R-A-N-S-I-S-T-O-R, because
it is a resistor or semiconductor device which can amplify
electrical signals as they are transferred through it from input
to output terminals. It is, if you will, the electrical equivalent
of a vacuum tube amplifier. But there the similarity ceases. It
has no vacuum, no filament, no glass tube. It is composed
entirely of cold, solid substances.

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 A Brief History

 Jack Kilby at Texas Instruments realized the potential for miniaturization

 Multiple transistors could be built on one piece of silicon.
 first prototype of an integrated circuit, constructed from a germanium slice and gold
wires.
 The invention of the transistor earned the Nobel Prize in Physics in 1956 for
Bardeen, Brattain, and their supervisor William Shockley. Kilby received the Nobel
Prize in Physics in 2000 for the invention of the integrated circuit

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A Brief History
 Transistors can be viewed as electrically controlled switches with a control
terminal and two other terminals that are connected or disconnected
depending on the voltage or current applied to the control.
 Soon after inventing the point contact transistor, Bell Labs developed the
bipolar junction transistor.
 Bipolar transistors were more reliable, less noisy, and more power-efficient.
Early integrated circuits primarily used bipolar transistors.
 Bipolar transistors require a small current into the control (base) terminal
to switch much larger currents between the other two (emitter and
collector) terminals.
 The quiescent power dissipated by these base currents, drawn even when
the circuit is not switching limits the maximum number of transistors that
can be integrated onto a single die.

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A Brief History

 By the 1960s, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) began
to enter production.
 MOSFETs offer the compelling advantage that they draw almost zero control current
while idle.
 They come in two flavors: nMOS and pMOS, using n-type and p-type silicon,
respectively.
 Fairchild’s gates used both nMOS and pMOS transistors, earning the name
Complementary Metal Oxide Semiconductor, or CMOS.
 The circuits used discrete transistors but consumed only nano watts of power, six
orders of magnitude less than their bipolar counterparts.
 With the development of the silicon planar process, MOS integrated circuits
became attractive for their low cost because each transistor occupied less area and
the fabrication process was simpler

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 A Brief History

 Early commercial processes used only pMOS transistors and suffered

from poor performance, yield, and reliability.
 Processes using nMOS transistors became common in the 1970s
 Intel pioneered nMOS technology with its 1101 256-bit static
random access memory and 4004 4-bit microprocessor
4004
microprocessor
Intel 1101
SRAM

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 In 1965, Gordon
Moore observed
that plotting the
number of
transistors that can
be most
economically
manufactured on a
chip gives a
straight line on a
semi logarithmic
scale
[Moore65].
At the time, he
found transistor
count doubling
every 18 months.

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 The level of integration of chips has been classified as
 Small-scale,
 Medium-scale,
 Large-scale, and
 Very large scale.
 Small-scale integration (SSI) circuits, such as the 7404 inverter, have fewer
than 10 gates, with roughly half a dozen transistors per gate.
 Medium-scale integration (MSI) circuits,such as the 74161 counter, have up to
1000 gates.
 Large-scale integration (LSI) circuits, such as simple 8-bit microprocessors,
have up to 10,000 gates.
 A corollary of Moore’s law is Dennard’s Scaling Law [Dennard74]: as transistors
shrink, they become faster, consume less power, and are cheaper to
manufacture.

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 This frequency scaling hit the power wall around 2004, and clock
frequencies have leveled off around 3 GHz.
 Computer performance, measured in time to run an application,

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Process generations

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 Silicon (Si), a semiconductor, forms the basic starting material for most
integrated circuits.
 Pure silicon consists of a three-dimensional lattice of atoms. Silicon is a Group
IV element, so. it forms covalent bonds with four adjacent atoms
 As all of its valence electrons are involved in chemical bonds,
pure silicon is a poor conductor. The conductivity can be raised by
introducing small amounts of impurities, called dopants, into the silicon lattice.

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 A dopant from Group V of the periodic table, such as arsenic, has five
valence electrons. It replaces a silicon atom in the lattice and still
bonds to four neighbors, so the fifth valence electron is loosely
bound to the arsenic atom
 Thermal vibration of the lattice at room temperature is enough
to set the electron free to move, leaving a positively charged As+ ion
and a free electron.
 The free electron can carry current so the conductivity is
higher

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 Group III dopant, such as boron, has three valence electrons,
 The dopant atom can borrow an electron from a neighboring silicon
atom, which in turn becomes short by one electron. That atom in turn
can borrow an electron, and so forth, so the missing electron, or hole,
can propagate about the lattice.
 The hole acts as a positive carrier so we call this a p-type
semiconductor.

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p-n junction diode structure and symbol

 A junction between p-type and n-type silicon is called a diode

 When the voltage on the p-type semiconductor, called the anode, is

raised above the n type cathode, the diode is forward biased
and current flows. When the anode voltage is less than or equal
to the cathode voltage, the diode is reverse biased and very little
current flows

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n MOS transistor and p MOS transistor
 A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several
layers of conducting and insulating materials to form a sandwich-like
structure.
 These structures are manufactured using a series of chemical processing steps
involving oxidation of the silicon, selective introduction of dopants, and
deposition and etching of metal wires and contacts.
 Transistors are built on nearly flawless single crystals of silicon, which are available as
thin flat circular wafers of 15–30 cm in diameter.
 CMOS technology provides two types of transistors (also called devices): an n-type
transistor (nMOS) and a p-type transistor (pMOS).
 Transistor operation is controlled by electric fields so the devices are also called Metal
Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply FETs.
 The n+ and p+ regions indicate heavily doped n- or p-type silicon.

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 Each transistor consists of a stack of the conducting gate, an insulating layer of
silicon dioxide (SiO2, better known as glass), and the silicon wafer, also called the
substrate, body, or bulk.
 Gates of early transistors were built from metal, so the stack was called metal
oxide- semiconductor, or MOS. Since the 1970s, the gate has been formed from
polycrystalline silicon (poly silicon), but the name stuck. (Interestingly, metal
gates reemerged in 2007 to solve materials problems in advanced
manufacturing processes.)
 An nMOS transistor is built with a p-type body and has regions of n-type
semiconductor adjacent to the gate called the source and drain.

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 The gate is a control input: It affects the flow of electrical current between the
source and drain. Consider an n MOS transistor.
 The body is generally grounded so the p–n junctions of the source and drain
to body are reverse-biased.
 If the gate is also grounded, no current flows through the reverse-biased
junctions. Hence, we say the transistor is OFF.
 If the gate voltage is raised, it creates an electric field that starts to attract
free electrons to the underside of the Si–SiO2 interface.
 If the voltage is raised enough, the electrons outnumber the holes and a thin
region under the gate called the channel is inverted to act as an n-type
semiconductor.
 Hence, a conducting path of electron carriers is formed from source to drain
and current can flow. We say the transistor is ON.

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 For a pMOS transistor, the situation is again reversed. The body is held at a
positive voltage. When the gate is also at a positive voltage, the source and
drain junctions are reverse-biased and no current flows, so the transistor is
OFF.
 When the gate voltage is lowered, positive charges are attracted to the
underside of the Si–SiO2 interface.
 A sufficiently low gate voltage inverts the channel and a conducting path of
positive carriers is formed from source to drain, so the transistor is ON.
Notice that the symbol for the pMOS transistor has a bubble on the gate,
indicating that the transistor behavior is the opposite of the nMOS.

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General logic gate using pull-up and pull-down
networks

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Connection and behavior of series and parallel
transistors

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Output states of CMOS logic gates

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CMOS compound gate for function Y = (A · B) +
(C · D)

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Sketch a static CMOS gate computing Y = (A + B + C) ·D

 OR-AND-INVERT-3-1 (OAI31) gate. The nMOS pull-down network pulls

the output low if D is 1 and either A or B or C are 1,so D is in series
with the parallel combination of A, B, and C.
 The pMOS pull-up network is the conduction complement, so D must
be in parallel with the series combination of A, B, and C.

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Various implementations of a CMOS 4-input AND gate

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Tristates buffer

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Tristate Inverter

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Multiplexers
 Multiplexers are key components in CMOS memory elements and
data manipulation structures. A multiplexer chooses the output from
among several inputs based on a select signal.

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What is this schematic ?

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CMOS VLSI design, an alternate circuit
representation
Alternate circuit representation refers to different ways of modeling or visualizing a
digital circuit beyond the traditional transistor-level schematic. Some common
representations include:
1. Stick Diagrams
•A simple graphical representation using color-coded lines to depict transistors and
interconnections.
•Helps visualize layout before actual mask design.
2. Layout Diagrams
•A physical representation of the circuit showing how transistors and interconnections
are placed on a silicon wafer.
•Created using EDA tools like Cadence or Synopsys.
3. Boolean Expressions
•Represents the circuit using Boolean algebra, showing the logic function without
specifying transistor details.
•Example: F=A⋅B+C F = A dot B + C (AND-OR logic).
4. Karnaugh Maps (K-Maps)
•Dr.AAbdullah
graphical
Gubbi
method for simplifying Boolean expressions. 39
•Helps minimize logic before implementing in CMOS.
Alternate circuit representation
Logic Gate Representation
•Uses standard logic symbols (AND, OR, NOT, XOR, etc.).
•Abstracts transistor-level details, making it useful for high-level design.
6. Transmission Gate Logic
•Instead of conventional CMOS gates, it uses pass transistors or transmission gates to
implement logic functions.
•Used in low-power designs.
7. RTL (Register Transfer Level) Representation
•Describes the circuit in terms of data flow between registers.
•Used in HDL-based design (VHDL, Verilog).
8. Netlist Representation
•A textual representation listing all components and their interconnections.
•Used for circuit simulation and synthesis.
Each representation serves a different purpose in CMOS VLSI design,

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Difference between CMOS and NMOS Technology
 CMOS technology is the leading semiconductor technology for ASICs,
memories, microprocessors. The main advantage of CMOS technology
over BIPOLAR and NMOS technology is the power dissipation – when
the circuit is switched then only the power dissipates.
 CMOS Technology is used to construct ICs and this technology is used
in digital logic circuits, microprocessors, microcontrollers, and static
RAM.
 CMOS technology is also used in several analog circuits like data
converters, image sensors, and in highly integrated transceivers.
 The main features of CMOS technology are low static power
consumption and high noise immunity.

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Comparisons between CMOS and bipolar technologies

 CMOS technology Bipolar technology

 • Low static power dissipation • High power dissipation
 • High input impedance • Low input impedance
 (low drive current) (high drive current)
 • Scalable threshold voltage Low voltage swing logic
 • High noise margin
 • High packing density • Low
packing density
 • High delay sensitivity to load Low delay
sensitivity to load
 (fan-out limitations)
 • Low output drive current • High output
drive current
 • Low gm,(.gm α vin) High gm (gmα evin)
 • Bidirectional capability High ft, at low currents
 (drain and source are Essentially
unidirectional
 interchangeable)
 • A near ideal switching device
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CMOS Advantages
 CMOS transistors use electrical power efficiently.
 These devices are used in a range of applications with analog circuits like
image sensors, data converters, etc. The advantages of CMOS technology
over NMOS are as follows.
 Very low static power consumption
 Reduce the complexity of the circuit
 The high density of logic functions on a chip
 Low static power consumption
 High noise immunity
 When CMOS transistors change from one condition to another, then they
use electrical current.
 In addition, the complimentary semiconductors limit the o/p voltage by
working mutually. The outcome is a low-power design that provides less
heat.
 Because of this reason, these transistors have changed other earlier designs
like CCDs in camera sensors as well as used in most current processors.
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 CMOS: CMOS stands for Complementary metal-oxide-semiconductor
 NMOS:NMOS stands for N-type metal oxide semiconductor
 CMOS: This technology is used to make ICs which are used in different applications like batteries,
electronic components, image sensors, digital cameras.NMOS technology is used to make logic gates as
well as digital circuits
 CMOS employs symmetrical as well as complementary pairs of MOSFETs like p-type & n-type MOSFETs
for the operation of logic functions The operating of NMOS transistor can be done by making an
inversion layer within a p-type transistor body
 The modes of operation of CMOS are accumulation like depletion and inversion
 NMOS has four modes of operations that simulate other types of MOSFETs like a cut-off, triode,
saturation & velocity saturation.
 The CMOS characteristics are low static power consumption as well as high noise immunity and.
 The NMOS transistor characteristics are, when the voltage increases on the top electrode, then electrons
attraction will be there toward the surface. At a specific voltage range, which we will shortly describe
like the threshold voltage, where the density of electron at the outside will exceed the density of holes.
 CMOS is used in Digital logic circuits, Microprocessors, SRAM (Static RAM) & Microcontrollers NMOS is
used to implement digital circuits as well as logic gates.
 The CMOS logic level is 0/5V
 The NMOS logic level mainly depends on beta ratio as well as poor noise margins

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 The transmission time of CMOS is tI=tf The transmission time of CMOS is tI>tf
 Layout of CMOS is more regular
 The layout of NMOS is irregular
 Load or drive ratio of CMOS is 1:1/2:1
 Load or drive ratio of NMOS is 4:1
 Packing density is less, 2N device for N-inputs
 Packing density is denser, N+1 device for N-inputs
 The power supply may change from 1.5 to 15V VIH/VIL, a fixed fraction of VDD
 The power supply is fixed based on VDD
 Transmission gate of CMOS will pass both logic well
 NMOS :Only pass ‘0’, well pass ‘1’ will have VT drop
 Pre-charging scheme of CMOS is, for both n & p are accessible for the pre-
charging bus to VDD/VSS Simply charges from VDD to VT except utilize
bootstrapping
 Power dissipation is zero in standby
 In NMOS, when output is ‘0’ then power dissipates
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 Latch-up in CMOS circuits

 A problem which is inherent in the p-well and n-well processes is

due to the relatively large number of junctions which are formed in
these structures and, the consequent presence of parasitic
transistors and diodes.
 Latch-up is a condition in which the parasitic components
give rise to the establishment of low-resistance conducting
paths between VDD and Vss with disastrous results.
 Latch-up may be induced by glitches on the supply rails or by
incident radiation.

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Once latched-up, this condition will be maintained until the latch-up
current
drops below Ii. It is essential for a CMOS process to ensure that v,
and I, are
not readily achieved in any normal mode of operation.

Latch-up current versus voltage

Latch-up circuit
model
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Origin and model of CMOS latchup

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Latch-up effect in p-well structure

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 With no injected current, the parasitic transistors will exhibit high
resistance, but sufficient substrate current flow will cause switching to
the low-resistance state
 Remedies for the latch-up problem include:
 1. an increase in substrate doping levels with a consequent drop in
the value of Rs;
 2. reducing Rp by control of fabrication parameters and by ensuring a
low contact resistance to VSS
 3. other more elaborate measures such as the introduction of guard
rings.

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Remedies for the latch-up problem
 Every well should have at least one tap.
 All substrate and well taps should connect
directly to the appropriate supply in metal.
 A tap should be placed for every 5–10
transistors, or more often in sparse areas.
 nMOS transistors should be clustered
together near GND and pMOS transistors
should be clustered together near VDD,
avoiding convoluted structures that
intertwine nMOS and pMOS transistors in
checkerboard patterns.

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Latch-up Circuit for n-well process

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Flip-Flops
 By combining two level-sensitive latches, one negative-sensitive and
one positive-sensitive, we construct the edge-triggered flip-flop

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Sequential Circuits
 Sequential circuits have memory: their outputs depend on both
current and previous inputs. Using the combinational circuits
developed so far, we can now build sequential circuits such as latches
and flip-flops.
 Elements receive a clock, CLK, and a data input, D, and produce an
output, Q. A D latch is transparent when CLK = 1, meaning that
Q follows D.
 It becomes opaque when CLK = 0, meaning Q retains its
previous value and ignores changes in D.
 An edge-triggered flip-flop copies D to Q on the rising edge of
CLK and remembers its old value at other times.

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Latches :CMOS positive-level-sensitive D latch
 A D latch built from a 2-input multiplexer and two inverters
 The multiplexer can be built from a pair of transmission gates
 The D latch is also known as a level-sensitive latch because the state
of the output is dependent on the level of the clock signal,

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CMOS positive-edge-triggered D flip-flop Clk=0; clk
=1

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 Good design practice would buffer the input and output with
inverters, to preserve what we call “modularity.”
 Modularity allows that each block or module can be designed
relatively independently from each other, since there is no
ambiguity about the function and the signal interface of these
blocks. All of the blocks can be combined with ease at the end
of the design process, to form the large system

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 MOS Transistor
Theory
Text book 1

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 The three-terminal symbols are used in the great majority
of schematics.
 The MOS transistor is a majority-carrier device in which the
current in a conductingchannel between the source and
drain is controlled by a voltage applied to the gate.
 In an nMOS transistor, the majority carriers are electrons; in
a pMOS transistor, the majority carriers are holes.

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MOS structure

 Negative voltage is applied to the gate, so there is negative charge

on the gate. The mobile positively charged holes are attracted to the
region beneath the gate. This is called the accumulation mode.

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MOS structure

 Small positive voltage is applied to the gate, resulting in some

positive charge on the gate. The holes in the body are
repelled from the region directly beneath the gate, resulting in a
depletion region forming below the gate.

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MOS structure

 Higher positive potential exceeding a critical threshold voltage Vt is

applied, attracting more positive charge to the gate. The holes are repelled
further and some free electrons in the body are attracted to the region
beneath the gate. This conductive layer of electrons in the p-type body is
called the inversion layer.

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nMOS transistor demonstrating cutoff,
linear, and saturation regions of
operation

 The gate-to-source voltage Vgs is less than the threshold

voltage.
 Small amounts of current leaking through OFF transistors can
become significant, especially when multiplied by millions or billions
of transistors on a chip.

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 The transistor consists of the MOS stack between two n-type regions
called the source and drain.
 The gate-to-source voltage Vgs is less than the threshold voltage.
 The source and drain have free electrons. The body has free holes but
no free electrons.
 The junctions between the body and the source or drain are zero-
biased or reverse-biased, so little or no current flows. We say the
transistor is OFF

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  The gate voltage is greater than the
threshold voltage. Now an inversion region
of electrons (majority carriers) called the
channel connects the source and drain,
creating a conductive path and turning the
transistor ON.
 The number of carriers and the
conductivity increases with the gate
voltage.

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 When a small positive potential Vds is applied to the drain current Ids
flows through the channel from drain to source. This mode of
operation is termed linear, resistive, triode, nonsaturated, or
unsaturated;

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 Saturation: Channel Pinched Off Ids Independent of Vds
 However, conduction
 is still brought about by the drift of electrons under the influence of
the positive drain voltage.
 In summary, the nMOS transistor has three modes of operation.
 If Vgs < Vt , the transistor is cutoff (OFF). If Vgs > Vt , the transistor
turns ON. If Vds is small, the transistor acts as a linear resistor in
which the current flow is proportional to Vds. If Vgs > Vt and Vds is large,
the transistor acts as a current source in which the current flow
becomes independent of Vds .

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pMOS transistor
 The pMOS transistor operates in just the opposite fashion.
 The n-type body is tied to a high potential so the junctions with
the p-type
 source and drain are normally reverse-biased.
 When the gate is also at a high potential, no current flows between
drain and source. When the gate voltage is lowered by a
threshold Vt , holes are attracted to form a p-type channel
immediately beneath the gate, allowing current to flow between drain
and source.
 The threshold voltages of the two types of transistors are not
necessarily equal, so we use the terms Vtn and Vtp to distinguish the
nMOS and pMOS thresholds.
 In static CMOS gates, the source is the terminal closer to the supply
rail and the drain is the terminal closer to the output.
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 The delay of MOS circuits is determined by the time required for this
current to charge or discharge the capacitance of the circuits.
 The gate of an MOS transistor is inherently a good capacitor with a
thin dielectric; indeed, its capacitance is responsible for
attracting carriers to the channel and thus for the operation
of the device.
 The p–n junctions from source or drain to the body contribute
additional parasitic capacitance.
 idealized I-V model provides a general qualitative understanding
of transistor behavior but is of limited quantitative value.
 On the one hand, it neglects too many effects that are
important in transistors with short channel lengths L.
Therefore, the model is not sufficient to calculate current accurately.

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Long-Channel I-V Characteristics

 Mos transistors have three regions of operation:

 Cutoff or subthreshold region
 Linear region
 Saturation region
 Derive the Ids equation
 long-channel, ideal, first-order, or Shockley model
 The model assumes that the channel length is long enough that the lateral electric
field (the field between source and drain) is relatively low, which is no longer the
case in nanometer devices.

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 pMOS transistors behave in the same way, but with the signs of all
voltages and currents reversed. The I-V characteristics are in the third
quadrant.
 The current flows from source to drain in a pMOS transistor.
 The mobility of holes in silicon is typically lower than that of
electrons.
 pMOS transistors provide less current than nMOS transistors
of comparable size and hence are slower.
 The symbols µn and µp are used to distinguish mobility of electrons
and of holes in nMOS and pMOS transistors,

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Non ideal I-V Effects
 The long-channel I-V model of EQ) neglects many effects that are
important to devices with channel lengths below 1 micron.
 The saturation current increases less than quadratically with
increasing Vgs . This is caused by two effects: velocity saturation
and mobility degradation.
 At high lateral field strengths (Vds /L), carrier velocity ceases to
increase linearly with field strength called velocity saturation and
results in lower Ids than expected at high Vds .
 At high vertical field strengths (Vgs /tox ), the carriers scatter off the
oxide interface more often, slowing their progess.
 This mobility degradation effect also leads to less current than
expected at high Vgs .

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 The saturation current of the non ideal transistor increases somewhat with V ds .
This is caused by channel length modulation, in which higher Vds increases the
size of the depletion region around the drain and thus effectively shortens the
channel.
 The threshold voltage indicates the gate voltage necessary to invert
the channel and is primarily determined by the oxide thickness and
channel doping levels.
 However, other fields in the transistor have some effect on the
channel, effectively modifying the threshold voltage.
 Increasing the potential between the source and body raises
the threshold through the body effect.
 Increasing the drain voltage lowers the threshold through
drain-induced barrier lowering.
 Increasing the channel length raises the threshold through the
short channel effect.
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 The current into the gate Ig is ideally 0. However, as the thickness of
gate oxides reduces to only a small number of atomic layers,
electrons tunnel through the gate, causing some gate leakage
current.
 The source and drain diffusions are typically reverse-biased diodes
and also experience junction leakage into the substrate or well.
 Both mobility and threshold voltage decrease with rising
temperature.

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Mobility Degradation
 The constant of proportionality is called the carrier mobility, µ.
 The long-channel model assumed that carrier mobility is
independent of the applied fields.
 for low fields, breaks down when strong lateral or vertical fields are
applied.
 A high voltage at the gate of the transistor attracts the carriers
to the edge of the channel, causing collisions with the oxide
interface that slow the carriers. This is called mobility
degradation
 Mobility degradation can be modeled by replacing µ with a smaller µ eff
that is a function of Vgs.

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velocity saturation
 Recall from EQ that carrier drift velocity, and hence current, is
proportional to the lateral electric field Elat = Vds /L between source
and drain.
 This is analogous to carriers scattering off the silicon lattice
(technically called collisions with optical phonons). The faster you try
to go, the more often you collide. Beyond a certain level of fatigue,
you reach a maximum average speed. In the same way, carriers
approach a maximum velocity vsat when high fields are applied. This
phenomenon is called velocity saturation
 Velocity saturates at high fields.

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 The critical voltage Vc is the drain-source voltage at which the critical
effective field is reached: Vc = Ec L.

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Channel Length Modulation
 Ideally, Ids is independent of Vds for a transistor in saturation, making
the transistor a perfect current source.
 The p–n junction between the drain and body forms a depletion
region with a width Ld that increases with Vdb ,
 The depletion region effectively shortens the channel length to
 Leff = L- Ld

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Channel Length Modulation

 To avoid introducing the body voltage into our calculations, assume the source
voltage is close to the body voltage so Vdb = Vds.
 Hence, increasing Vds decreases the effective channel length. Shorter channel
length results in higher current;

 VA is the early voltage

 Channel length modulation is very important to analog designers because
it reduces the gain of amplifiers. It is generally unimportant for
qualitatively understanding the behavior of digital circuits
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Threshold Voltage Effects
 Threshold Voltage Vt increases with the source voltage,
 Threshold Voltage Vt decreases with the body voltage,
 Threshold Voltage Vt decreases with the drain voltage, and
 Threshold Voltage Vt increases with channel length

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Body Effect
 When a voltage Vsb is applied between the source and body, it
increases the amount of charge required to invert the channel, hence,
it increases the threshold voltage. The threshold voltage can be
modeled as

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Consider the nMOS transistor in a 65 nm process
with a nominal threshold voltage of
0.3 V and a doping level of 8 × 1017 cm–3. The
body is tied to ground with a substrate contact.
How much does the threshold change at room
temperature if the source is at 0.6 V instead of 0?
 At room temperature, the thermal voltage vT = kT/q = 26 mV and ni = 1.45 ×
1010 cm–3. The threshold increases by 0.04 V.

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Drain-Induced Barrier Lowering
 The drain voltage Vds creates an electric field that affects the
threshold voltage. This drain-induced barrier lowering (DIBL) effect
is especially pronounced in short-channel transistors. It can be
modeled as

 where ŋ is the DIBL coefficient, typically on the order of 0.1 (often

expressed as 100 mV/V).
 Drain-induced barrier lowering causes Ids to increase with
Vds in saturation, in much the same way as channel length
modulation does.

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Short Channel Effect
 The threshold voltage (Vt) increases as the channel length (L)
increases.
 For small L, the source and drain depletion regions extend
into the channel, affecting Vt. This is called the Short Channel
Effect (SCE) or Vt roll-off.
 Reverse Short Channel Effect (RSCE) :In some fabrication
processes, Vt decreases with channel length instead of
increasing.
 Narrow Channel Effect (NCE) Vt also varies with channel width
(W), but this effect is generally less significant than SCE. This
is because the minimum width (W) is usually greater than the
minimum length (L).

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Leakage

 Leakage in OFF-State Transistors

 Even when transistors are nominally OFF, they leak small amounts of
current.
 Types of Leakage Mechanisms
 Subthreshold Conduction: Caused by thermal emission of carriers
over the threshold potential barrier.
 Gate Leakage: A quantum-mechanical effect due to tunneling
through an extremely thin gate dielectric.
 Junction Leakage: Leakage current through the p-n junction between
source/drain diffusions and the body.

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Subthreshold Leakage

1 Current Flow Below Vt

•In long-channel transistors, current flows only when VGS>VT
•In real transistors, current does not abruptly stop below VT​but
drops exponentially.
2.Weak Inversion Region
•When VGS<VTV the transistor is in the weak inversion region.
•The current decline appears as a straight line on a logarithmic
scale.
3.Impact of VDS​on Leakage
•Subthreshold leakage increases significantly with drain-to-
source voltage (Vds).
•This is due to Drain-Induced Barrier Lowering (DIBL).
4.Lower Limit on IDS
•Set by drain junction leakage, which worsens with negative
gate voltage.

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DC Transfer Characteristics
 DC transfer characteristics of a circuit relate the output voltage to the
input voltage, assuming the input changes slowly enough that
capacitances have plenty of time to charge or discharge.
 CMOS Inverter Static Characteristics
 Table shows outlines various regions of operation for the n- and p-
transistors. In this table, Vtn is the threshold voltage of the n-channel
device, and Vtp is the threshold voltage of the p-channel device. Note
that Vtp is negative. The equations are given both in terms of
Vgs/Vds and Vin/Vout. As the source of the nMOS transistor is
grounded, Vgsn = Vin and Vdsn = Vout. As the source of the pMOS
transistor is tied to VDD, Vgsp =Vin – VDD and
Vdsp =Vout – VDD.

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 The objective is to find the variation in output voltage (Vout) as a
function of the input voltage (Vin). This may be done graphically, for
simplicity, we assume Vtp = –Vtn and that the pMOS transistor is 2–3
times as wide as the nMOS transistor so βn = βp.
 • The plot shows Idsn and Idsp in terms of Vdsn and Vdsp for various
values of Vgsn and Vgsp using drain current equation.
 • Fig 1.10(b) shows the same plot of Idsn and |Idsp| now in terms of
Vout for various values of Vin. The possible operating points of the
inverter, marked with dots, are the values of Vout where Idsn = |Idsp|
for same Vin.
 • These operating points are plotted on Vout vs. Vin axes in Fig. (c) to
show the inverter DC transfer characteristics.
 • The supply current IDD = Idsn = |Idsp| is also plotted against Vin in
Fig (d) showing that both transistors are momentarily ON as Vin
passes through voltages between GND and VDD, resulting in a pulse
of current drawn from the power supply.
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 The operation of the CMOS inverter can be divided into five regions
indicated on Fig 1.10(c). The state of each transistor in each region
and state of output is shown in Table 2.
 o In region A, the nMOS transistor is OFF so the pMOS transistor pulls
the output to VDD.
 o In region B, the nMOS transistor starts to turn ON, pulling the output
down.
 o In region C, both transistors are in saturation.
 o In region D, the pMOS transistor is partially ON
 o In region E, pMOS is completely OFF, leaving the nMOS transistor to
pullGubbi
Dr. Abdullah the output down to GND 92
Summary of CMOS Inverter
Operation

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 Feature CMOS nMOS
Output does not settle at
Fully restored logic, output settles at
Logic Levels V_SS (GND), causing
V_DD or V_SS (GND)
degraded noise margin
Transition Rise and fall times are of the same Rise times are inherently
Times order slower than fall times
Pass transistor transfers
Transmission Passes both logic levels well, output can logic ‘0’ well, but logic ‘1’ is
Gates drive other gates degraded. Cannot drive a
second pass transistor
With output ‘0’, power is
Almost zero static power dissipation,
Power dissipated in the circuit, in
but power is dissipated during logic
Dissipation addition to dissipation during
transition
logic transitions
Enhancement mode
Both n-type and p-type devices are
transistor can charge a bus
Precharging available for precharging a bus to VDD
to (VDD - Vt). Bootstrapping
Characteristics and VSS. Nodes can be fully charged to
or hot clocking is needed to
VDD or VSS in a short time
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precharge to VDD95
 Feature CMOS nMOS
Voltage required to switch a
gate is a fixed percentage of Somewhat dependent on supply
Power Supply
V_DD, variable range 1.5V to voltage, fixed
15V
Requires 2N devices for N inputs
Packing
for complementary static gates; Requires (N + 1) devices for N inputs
Density
less for dynamic gates
Load-to-enhancement-driver ratio is
Pull-up to Pull- Load-to-driver ratio is typically
typically 4:1 to optimize logic ‘0’ output
down Ratio 1:1 or 2:1
level and minimize current consumption
Depletion load and different driver
Layout Encourages regular layout styles
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96 layout regularity
Alternative forms of pull-up

 Load resistance RL . This arrangement is not often used because of

the large space requirements of resistors produced in a silicon
substrate.

Dr. Abdullah Gubbi 97

 nMOS depletion mode transistor pull-up (Figure 2-12).
 (a) Dissipation is high since rail to rail current flows when V1,, =
logical 1.
 (b) Switching of output from Ito 0 begins when Vi. exceeds V, of p.d.
device.
 (c) When switching the output from 1 to 0, the p.u. device is non-
saturated initially and this presents lower resistance through which to
charge capacitive loads.

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nMOS depletion mode transistor
pull-up and transfer characteristic

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nMOS enhancement mode pull-up
and transfer characteristic

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