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Tut 5

The document describes four problems related to analyzing the timing characteristics of basic digital logic circuits: 1) Determining the output waveforms and hold time of an S-R latch where each NAND gate has a 1ns delay. 2) Reworking the above problem assuming one NAND gate has a 1ns delay and the other has a 2ns delay. 3) Calculating the setup time of a D-latch where NAND gates have a 1ns delay and NOT gates have a 0.5ns delay. 4) Calculating the setup and hold times of a master-slave D-flip-flop with the same gate delays.

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Archana Tripathi
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85 views1 page

Tut 5

The document describes four problems related to analyzing the timing characteristics of basic digital logic circuits: 1) Determining the output waveforms and hold time of an S-R latch where each NAND gate has a 1ns delay. 2) Reworking the above problem assuming one NAND gate has a 1ns delay and the other has a 2ns delay. 3) Calculating the setup time of a D-latch where NAND gates have a 1ns delay and NOT gates have a 0.5ns delay. 4) Calculating the setup and hold times of a master-slave D-flip-flop with the same gate delays.

Uploaded by

Archana Tripathi
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Indian Institute of Technology, Delhi EEL 201: Digital Electronic Circuits Tutorial 5, 31st August, 2009 1.

For the S-R latch, assume each NAND gate has a delay of 1 nsec. The inputs to the S-R latch are applied as follows. At every 1 nsec, the value at S is given by 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1. At every 1 nsec, the value at R is given by 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1. Find out the waveform at the outputs, Q, Q as functions of time. What is the hold time of this latch? (Here hold time is the minimum pulse-width at the input for a reasonable output.)
S Q

Figure 1: Set-reset latch 2. Now assume that the top NAND gate has a delay of 1 nsec, while the bottom NAND gate has a delay of 2 nsec. Rework the above problem. 3. Assume that the delay of each NAND gate is 1 nsec, the delay of each NOT gate is 0.5 nsec. Compute the setup time of the D-latch. (Here setup time is the minimum time for which the input has to be constant before the clock becomes inactive.) 4. Compute the setup time and the hold time of a falling-edge-triggered master-slave D-ip-op. (Assume NAND gates have a delay of 1 nsec, NOT gates have a delay of 0.5 nsec.)
D Q

Figure 2: D-latch

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