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Veriloglab

The experiment aimed to implement various logic gates using gate level, behavioral, and data flow modeling in Xilinx ISE simulator. The gates modeled were NAND, NOR, XOR, and XNOR. Gate level modeling used primitive gates, behavioral modeling used always blocks, and data flow modeling used assign statements. A test bench was created to simulate and observe the outputs of the gates for different input combinations over time. The result was that various logic gates were successfully implemented using the three different modeling approaches.

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Uttkarsh Singh
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27 views6 pages

Veriloglab

The experiment aimed to implement various logic gates using gate level, behavioral, and data flow modeling in Xilinx ISE simulator. The gates modeled were NAND, NOR, XOR, and XNOR. Gate level modeling used primitive gates, behavioral modeling used always blocks, and data flow modeling used assign statements. A test bench was created to simulate and observe the outputs of the gates for different input combinations over time. The result was that various logic gates were successfully implemented using the three different modeling approaches.

Uploaded by

Uttkarsh Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Experiment-1

Aim: To implement various logic gates using gate level, behavioural and data flow
modelling.

Tool used: Xilinx simulator ISE

Theory:
 NAND : This gate gives output low only if both the inputs are high otherwise gives
output high.
 NOR : This gate gives output high if both the input are low and low otherwise.
 XOR : This gate gives high input if both the input are different .
 XNOR : This gate gives input high if both the input are same.

Code:
Gate level modelling:

module gates2(

input a,

input b,

output y1,

output y2,

output y3,

output y4

);

nand a2(y1,a,b);

nor a3(y2,a,b);

xor a4(y3,a,b);

xnor a5(y4,a,b);

endmodule
Behavioral modelling:

modulebehavioral_model(

inputa,b,

outputand_out,nor_out,nand_out,xor_out,xnor_out);

regand_out,nor_out,nand_out,xor_out,xnor_out;

always@(a or b)

begin

and_out=a&b;

nor_out=~(a|b);

nand_out=~(a&b);

xor_out=a^b;

xnor_out=~(a^b);

end

endmodule

Data flow modelling:

moduledata_flow_model(

inputa,b,

outputand_out,nor_out,nand_out,xor_out,xnor_out);

assignand_out=a&b;

assignnor_out=~(a|b);

assignnand_out=~(a&b);

assignxor_out=a^b;

assignxnor_out=~(a^b);

endmodule
Test Bench:
module gates2_test;

// Inputs

reg a;

reg b;

// Outputs

wire y1;

wire y2;

wire y3;

wire y4;

// Instantiate the Unit Under Test (UUT)

gates2 uut (

.a(a),

.b(b),

.y1(y1),

.y2(y2),

.y3(y3),

.y4(y4)

);

initial begin

// Initialize Inputs
a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

a = 1;

b = 0;

// Wait 100 ns for global reset to finish

#100;

a = 0;

b = 1;

// Wait 100 ns for global reset to finish

#100;

a = 1;

b = 1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule
RTL:

Waveforms:
Result: Various logic gates have been implemented using gate level ,behavioural and date
flow modeling

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