CSE 205: Digital Logic Design

Chapter 6
Registers and Counters
Clocked sequential circuits
⚫ A group of flip­flops and combinational gates.
⚫ Connected to form a feedback path.
⚫ Flip­flops + Combinational gates
(essential) (optional)
Register
⚫ A group of flip­flops.
⚫ Gates that determine how the information is
transferred into the register.
Counter
⚫ A register that goes through a predetermined
sequence of states.
Registers
A n­bit register
⚫ n flip­flops capable of storing
n bits of binary information.
⚫ 4­bit register is shown in Fig.
6.1.

Clear =0 (active low); A x

=0
Clock= ↑; A x=Ix
Normal Operation;
Clear =1

Fig. 6.1 Four­bit

Registers
loading / updating the register:
The transfer of new information
into a register
Parallel loading: When all the
bits of the register are loaded
simultaneously with a common
clock pulse

If some bits must

be left unchanged,
how to do it ?

Fig. 6.1 Four­bit

Registers
loading / updating the register:
The transfer of new information
into a register
Parallel loading: When all the
bits of the register are loaded
simultaneously with a common
clock pulse

The inputs must be held constant

or
Clock must be inhibited
from the circuit

Fig. 6.1 Four­bit

Registers
Problems:
If the inputs are hold constant
⚫ The data bus driving the register
would be unavailable for other
traffic.
Clock is inhibited from the circuit
⚫ Inserting gates into the clock
path is bad practice
⚫ To fully synchronize the system,
we must ensure that all clock
pulses arrive at the same time
anywhere in the system
⚫ All flipflops trigger
simultaneously
Fig. 6.1 Four­bit
Registers
Solution:
control the operation of the register
with the D inputs

Fig. 6.1 Four­bit

4­bit Register with Parallel Load
0 1 0

load 1
'
loa 0
The load input to the d

register determines 1
the action to be taken 0
with each clock pulse
1

1: Paralel load 0
0: No change
1

0
Shift Registers
A register capable of shifting the binary
information held in each cell to its neighbouring
cell, in a selected direction is called a shift
register.
⚫ Clock controls the shift operation

1 0 1 1 0
1 1 0 1 1

Four­bit shift register

Data Transfer
Serial transfer vs. Parallel transfer
⚫ Serial transfer
Information is transferred one bit at a time.
Shifts the bits out of the source register into
the destination register.
⚫ Parallel transfer
All the bits of the register are transferred at
the same time.
Serial transfer from reg A to reg B

Synchrono
us

Fig. 6.4 Serial transfer from register A to register B

Serial transfer from reg A to reg B

serial­
transfer
Serial Addition
Parallel adders
⚫ Faster,
⚫ cost more logic
Serial adders
⚫ Slower
⚫ n­bit addition n clock cycles
⚫ Less hardware
Serial Addition using D Flip­Flops

1 0
0 0
010
001
1
0
1
0 1
1 1
1
001
1
?00
1

Fig. 6.5 Serial adder

Serial Adder using JK FFs (1/2)
Serial adder using JK flip­flops
Serial Adder using JK FFs (2/2)
Circuit diagram
⚫ JQ = xy K Q = x′y′ = (x+y)′
⚫ S=x⊕y⊕Q

C
i

Fig. 6.6 Second form of serial adder

Universal Shift Register
Three types of shift register
⚫ Unidirectional shift register
A register capable of shifting in one direction.
⚫ Bidirectional shift register
A register can shift in both directions.
⚫ Universal shift register
Has both direction shifts & parallel load/out
capabilities.
Universal Shift Register (1/4)
Capability of a universal shift register:
1. A clear control to clear the register to 0;
2. A clock input to synchronize the operations;
3. A shift­right control to enable the shift right operation
and the serial input and output lines associated w/ the
shift right;
4. A shift­left control to enable the shift left operation and
the serial input and output lines associated w/ the shift
left;
5. A parallel­load control to enable a parallel transfer and
the n parallel input lines associated w/ the parallel
transfer;
6. n parallel output lines;
7. A control state that leaves the information in the register
unchanged in the presence of the clock;
Universal Shift Register (2/4)
Example: 4­bit universal shift register

Fig. 6.7 Four­bit universal shift

Universal Shift Register (3/4)
Function Table

Clear S1 S0 A3+ A2+ A1+ A0+ (operation)

0 × × 0 0 0 0 Clear
1 0 0 A3 A2 A1 A0 No change
1 0 1 sri A3 A2 A1 Shift right
1 1 0 A2 A1 A0 sli Shift left
1 1 1 I3 I2 I1 I0 Parallel load
Universal Shift Register (4/4)

Fig. 6.7 Four­bit universal shift register

Counters
Counter : A register that goes through a
prescribed sequence of states.
⚫ Special purpose arithmetic circuits used for the
purpose of counting
⚫ The sequence of states: may follow the binary
number sequence (⇒ Binary counter) or any
other sequence of states (e.g., Gray Code).
Counter circuits server many purposes
⚫ Count occurrences of certain events
⚫ Generate timing intervals for controlling
various tasks in a digital system
⚫ Track elapsed time between events
Counters
Categories of counters
1. Asynchronous counters (Ripple counters) The
flip­flops within the counter do not change
state at the same time
The flip­flop output transition serves as a
source for triggering other flip­flop.
◆ ⇒ no common clock pulse.

2. Synchronous counters
◆ The CLK inputs of all flip­flops receive a
common clock.
Binary Ripple Counter
A n­bit binary counter → n FFs → count from 0 to
2n­1.
Example: 4­bit binary ripple counter
⚫ Binary count sequence: 4­bit
Binary Ripple
Counter
Reset signal sets all
outputs to 0
Negative edge triggered
Count signal toggles
output of low­order flip
flop
Low­order flip flop
provides trigger for
adjacent flip flop
Output of one flipflop
Clock to the next
Not all flops change
value simultaneously
Lower­order flops
change first
Binary Ripple
Counter

A3 A2 A1 A0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0 Ripper Ripper
propagation propagation

Fig. 6.8 Four­bit binary ripple

counter
Asynchronous (Ripple) Counters
Asynchronous counters are commonly referred as
ripple counters
⚫ The effect of the input clock pulse is first felt by
the first flip­flop FF0.
⚫ The effect cannot get to the next flip­flop FF1
immediately as there is a propagation delay
through FF0
⚫ Then there is a propagation delay through FF1
before the next flip­flop FF2 is triggered
⚫ Thus, the effect of an input clock pulse “ripples”
through the counter, taking some time, due to
propagation delays, to reach the last flip­flop.
BCD Ripple Counter
Counter must reset itself after counting the
terminal count

Fig. 6.9 State diagram of a decimal BCD counter

BCD Ripple Counter

Q8 Q4 Q2 Q1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1

Fig. 6.10 BCD ripple counter

BCD Ripple Counter
Three­decade BCD counter

Fig. 6.11 Block diagram of a three­decade decimal BCD counter

Synchronous Counters
All of the FFs are triggered simultaneously by the
clock input pulses.
All FFs change at same time

Synchronous counters can be designed using

sequential circuit procedure
4­Bit Binary Counter
Value increments on positive edge
A3 A2 A1 A0
C_en
0 0 0 0
J=K=0, A0
0 0 0 1

no change; 0
0
0
0
1
1
0
1

J=K=1, 0 1 0 0
C_en A 0
0 1 0 1
complement. A1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
C_en A 0 A1
1 0 1 0
A2
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
4­bit Up/Down
Binary Counter
Up Down Function

0 0 No change
dow u
0 1 Down Count n p
1 0 Up Count

1 1 Up Count
down up
A3 A2 A1 A0 A'0 A0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
down A' 0 up A 0
0 1 0 1
A'1 A1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1 down A' 0 A'1 up A 0 A1
1 1 0 0 A'2 A2
1 1 0 1
1 1 1 0
1 1 1 1
BCD Counters

Simplified functions
4­bit binary counter
with parallel load

Fig. 6.14 Four­bit binary counter with parallel load

 count
loa load'
c_e
d
n

c_en
A0

asyn
c
Fig. 6.14
Four­bit binary counter with parallel load
BCD counter using a counter with
parallel load
Generate any count sequence
⚫ E.g.: BCD counter ⇐ Counter with parallel
load

Fig. 6.15 Two ways to achieve a BCD counter using a counter with
parallel load
Other Counters
Counters
⚫ Can be designed to generate any desired
sequence of states.
Divide­by­N counter (modulo­N counter)
⚫ A counter that goes through a repeated
sequence of N states.
⚫ The sequence may follow the binary count or
may be any other arbitrary sequence.
Counter with unsigned states
A circuit with n flip­flops has 2n states
⚫ We may have to design a counter with a given
sequence (unused states)
⚫ Unused states may be treated as don’t care or
assigned specific next state
⚫ Outside noise may cause the counter to enter
unused state
⚫ Must ensure counter eventually goes to the
valid state
Counter with unsigned states
An example

⚫ Two unused states: 011 & 111

⚫ The simplified flip­flop input equations:
JA = B, KA = B
JB = C, KB = 1
JC = B′, KC = 1
 Counter with unsigned states

The simplified flip­flop

input equations:
JA = B, K A = B
JB = C, K B = 1
JC = B′, K C = 1
Ring counter

A circular shift register with only one flip­flop

being set at any particular time, all others are
cleared (initial value = 1 0 0 … 0 ).
The single bit is shifted from one flip­flop to the
next to produce the sequence of timing signals.
Ring counter
A 4­bit ring counter

A3 A2 A1 A0
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
1 0 0 0

Fig. 6.17 Generation of timing

signals
Ring counter
Application of counters
⚫ Counters may be used to generate timing
signals to control the sequence of operations in
a digital system.
Approaches for generation of 2 n timing signals
1. A shift register with 2n flip­flops
2. An n­bit binary counter together with an n­
to­2n­line decoder
Generation of timing signals

Fig. 6.17 Generation of timing

signals
Ring counter vs. Switch­tail ring counter
Ring counter
⚫ A k­bit ring counter circulates a single bit
among the flip­flops to provide k
distinguishable states.
Switch­tail ring counter
⚫ It is a circular shift register with the
complement output of the last flip­flop
connected to the input of the first flip­flop.
⚫ A k­bit switch­tail ring counter will go through
a sequence of 2k distinguishable states. (initial
value = 0 0 … 0).
An example: Switch­tail ring counter
Johnson counter
A k­bit switch­tail ring counter + 2k decoding gates
Provide outputs for 2k timing signals
⚫ E.g.: 4­bit Johnson counter

The decoding follows a regular pattern

⚫ 2 inputs per decoding gate
Summary
Disadvantage of the switch­tail ring counter
⚫ If it finds itself in an unused state, it will
persist to circulate in the invalid states and
never find its way to a valid state.
⚫ One correcting procedure: DC = (A + C) B
Summary
⚫ Johnson counters can be constructed for any
number of timing sequences
Number of flip­flops = 1/2 (the number of
timing signals).
Number of decoding gates = number of timing
signals 2­input per gate.
Practice: counter with irregular binary
count sequence
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 1 0 1 0
0 1 0 1 0 1
1 0 1 1 1 1
1 1 1 0 0 1

Output Transitions Flip-Flop Inputs

QN QN+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
J0 = 1, K = Q2
J1 = K1 = 1
J2 = K2 = Q1
An analysis shows that if the counter, by accident,
gets into one of the invalid states (0, 3, 4, 6) it will
always return to a valid state according to the
following sequences: 0 3 4 7 and 6 1.