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Vlsi Design Lab Report 12

This lab report describes implementing finite state machines (FSM) using Verilog to model Mealy and Moore models. The student created Verilog modules for Mealy and Moore FSMs to detect sequences with and without overlap, and tested them with testbenches. The outputs from the simulations matched expectations and verified that the FSMs correctly detected the sequences as designed.

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Husn-ulMaab
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38 views14 pages

Vlsi Design Lab Report 12

This lab report describes implementing finite state machines (FSM) using Verilog to model Mealy and Moore models. The student created Verilog modules for Mealy and Moore FSMs to detect sequences with and without overlap, and tested them with testbenches. The outputs from the simulations matched expectations and verified that the FSMs correctly detected the sequences as designed.

Uploaded by

Husn-ulMaab
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EE-16

VLSI DESIGN
LAB REPORT 12
Submitted By: Husn Ul Maab, Roll no: 170401013

170401013
Title: FSM

AIM :
To write verilog code for FSM Mealy and Moore Models

TOOL REQUIRED :
Verilog

INTRO:

Finite State Machines (FSM) are sequential circuit used in many digital systems to
control the behavior of systems and dataflow paths. Examples of FSM include
control units and sequencers. This lab introduces the concept of two types of
FSMs, Mealy and Moore, and the modeling styles to develop such machines.
Mealy Sequency Detector No overlap
Module
Test Bench
Waveform
Conclusion
The result was verified , as observed by the output, the output is 1 when 1101
sequence is detected with no overlap

Mealy Sequence Detector Overlap

Module
Test Bench
Waveform
Conclusion
The result was verified , as observed by the output, the output is 1 twice now , one
with the overlap detected.

Moore No Overlap
Module
TestBench

Same as Mealy testbench with instant for Moore.

OUTPUT
Conclusion

The result was verified with the output as seen if sequence 1101 is detected, output becomes 1 , with
no overlap.

Moore Overlap

Module
TestBench

Same as Mealy testbench with instant for Moore.

OUTPUT
Conclusion

The result was verified with the output as seen if sequence 1101 is detected, output becomes 1 , with
overlap this time.

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