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DICD Tutorial 5

This document contains 9 questions regarding MOSFET circuits and transistor behavior. It provides the questions, asks the reader to determine the solution, and leaves space to write the solution. The questions cover topics such as determining drain current based on given transistor parameters, identifying when a transistor switches between linear and saturation regions, and calculating channel length modulation parameters.

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Pavika Sharma
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125 views5 pages

DICD Tutorial 5

This document contains 9 questions regarding MOSFET circuits and transistor behavior. It provides the questions, asks the reader to determine the solution, and leaves space to write the solution. The questions cover topics such as determining drain current based on given transistor parameters, identifying when a transistor switches between linear and saturation regions, and calculating channel length modulation parameters.

Uploaded by

Pavika Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Tutorial 5

Q1. In the circuit shown below. For the MOS transistors, 𝜇𝑛 𝐶𝑂𝑋 = 100 𝜇𝐴/𝑉2 and
the threshold voltage VT = 1 V. The voltage VX at the source of the upper transistor
is

(a) 1 V
(b) 2 V
(c) 3 V
(d) 3.6 V

Soln:

Q2. When the gate – to – source voltage (V GS) of a MOSFET with threshold
voltage of 400 mV, working in saturation is 900 mV, the drain current is observed
to be 1 mA. Neglecting the channel width modulation effect and assuming that the
MOSFET is operating at saturation, the drain current for an applied V GS of 1400
mV is
(a) 0.5 mA
(b) 2.0 mA
(c) 3.5 mA
(d) 4.0 mA

Soln:

Q3. The drain of an n – channel MOSFET is shorted to the gate so that 𝑉𝐺𝑆= . The
threshold voltage (VT) of MOSFET is 1 V. If the drain current (ID) is 1 mA for VGS
= 2 V, then for 𝑉𝐺𝑆=3 𝑉, ID is
(a) 2 mA
(b) 3 mA
(c) 9 mA
(d) 4 mA

Soln:

Q4. In the CMOS inverter circuit shown if the transconductance parameters of N


MOS and P MOS transistor are
𝐾𝑛 = 𝐾𝑝 = 𝜇𝑛𝐶𝑂𝑋 𝑊𝑛 /𝐿𝑛 = 𝜇𝑝𝐶𝑂𝑋 𝑊/𝑝 𝐿𝑝 = 40 𝜇𝐴/𝑉2
and threshold voltages are 𝑉𝑇 = 1𝑉 the current I is
(a) 0 A
(b) 25 μA
(c) 45 μA
(d) 90 μA
Soln:

Q5. For the n – channel MOS transistor shown in figure, the threshold voltage V TH
is 0.8V. Neglect channel length modulation effects. When the drain voltage V D =
1.6, the drain current ID was found to be 0.5 mA. If V D is adjusted to be 2V by
changing the values of R and VDD, the new value of ID (in m A) is

(a) 0.625
(b) 0.75
(c) 1.125
(d) 1.5
Soln:

Q6. The slope of the 𝐼𝐷 𝑣.𝑉𝐺𝑆 curve of an n – channel MOSFET in linear region is
10−3 Ω−1 at 𝑉𝐷𝑆=0.1𝑉 . For the same device, neglecting channel length modulation,
the slope of the √𝐼𝐷 𝑣𝑠 𝑉𝐺𝑆 curve (𝑖𝑛 √𝐴𝑉⁄) under saturation region is
approximately ________
Soln:

Q7 For the MOSFET M1 shown in figure, assume 𝑊𝐿 ⁄= 2, 𝑉𝐷𝐷 = 2.0𝑉, 𝜇𝑛 𝐶𝑂𝑋 =


100 𝜇𝑚𝑉2 ⁄𝑎𝑛𝑑 𝑉𝑇𝐻 = 0.5𝑉. The transistor M1 switches from saturation region to
linear region when 𝑉𝑖𝑛 (in volts) is ___________
Soln:

Q8. The current in an enhancement mode NMOS transistor biased in saturation


mode was measured to be 1 mA at a drain source voltage of 5V. When the drain
source voltage was increased to 6V while keeping gate source voltage same. The
drain current increased to 1.02 mA. Assume that drain to source saturation voltage
is much smaller than the applied drain source voltage. The channel length
modulation parameter λ (𝑖𝑛 𝑉−1) is ______________.

Soln:

Q9. Consider an n – channel metal oxide semiconductor field effect transistor


(MOSFET) with gate to source voltage of 1.8V. Assume that
𝑊𝐿=4,𝐶𝑂𝑋=70×10−6 𝐴𝑉−2
The threshold voltage is 0.3V, and the channel length modulation parameter is
0.09𝑉−1. In the saturation region, the drain conduction (in micro Siemens) is ?

Soln:

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