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Source Follower: Vgs VP

This document describes the analysis of a common gate JFET amplifier circuit. It provides: 1) Calculations of the circuit's quiescent operating point (Q-point) of 2mA drain current and -2V gate-source voltage. 2) Graphical depiction of the JFET's transfer characteristic curve showing the Q-point. 3) Voltage values at the circuit's terminals: gate (0V), drain (22V), source (2V), and drain-source (20V).

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73 views8 pages

Source Follower: Vgs VP

This document describes the analysis of a common gate JFET amplifier circuit. It provides: 1) Calculations of the circuit's quiescent operating point (Q-point) of 2mA drain current and -2V gate-source voltage. 2) Graphical depiction of the JFET's transfer characteristic curve showing the Q-point. 3) Voltage values at the circuit's terminals: gate (0V), drain (22V), source (2V), and drain-source (20V).

Uploaded by

Sugar Lips
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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SOURCE FOLLOWER

JFET=2N4222

IDSS=8mA

VP=-4V

VDD=25V

(i) Calculate the Q-point (V GSQ and I DQ ) of the circuit using calculation method. The list

of parameter need to be calculated as well are :

vgs
VG-VGS-VS=0 iD= iDSS(1 - )²
vp
−1 kiD
VGS=VG-VS iD=8m(1 - )²
−4
VGS=0-VS iD=8m(1 – 0.25KiD) ²

VGS=-RSID 0=8m-5iD+500iD²

VGS= -1KiD iD=2mA

VGS= -1K×2m

VGS=-2v

b) V G (voltage at gate terminal)

VG=0

because there is no current flow through GATE terminal

cause by RG being short .

c) V D (voltage at drain terminal)


25V

d) V S (voltage at source terminal)

VS= iDRS

VS= 2m× 1K

VS= 2V

e) V DS

VDD-VDS-VS=0

VDS=VDD-VS

VDS=25V-2V

VDS=23V

(II) GRAPHICAL APPROACH

VGS ID
0V 8 mA
-1.2V 4 mA
-2V 2 mA
-4V 0 mA

5
ID

0
-4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0

VGS
(iv) snapshot of circuit
COMMON GATE
JFET=2N4222

IDSS=8mA

VP=-4V

VDD=25V

(i) Calculate the Q-point (V GSQ and I DQ ) of the circuit using calculation method. The list

of parameter need to be calculated as well are :

vgs
VG-VGS-VS=0 iD= iDSS(1 - )²
vp
−1 kiD
VGS=VG-VS iD=8m(1 - )²
−4
VGS=0-VS iD=8m(1 – 0.25KiD) ²

VGS=-RSID 0=8m-5iD+500iD²

VGS= -1KiD iD=2mA

VGS= -1K×2m

VGS=-2v

b) V G (voltage at gate terminal)

VG=0

because there is no current flow through GATE terminal

cause by RG being short .


c) V D (voltage at drain terminal)

VD=VDD-IDRD

=25V-(2m×1.5k)

VD=22V

d) V S (voltage at source terminal)

VS= iDRS

VS= 2m× 1K

VS= 2V

e) V DS

VDD-IDRD-VDS-VS=0

VDS=VDD-VS-IDRD

VDS=25V-2V-3V

VDS=20V

(II) GRAPHICAL APPROACH

VGS ID
0V 8 mA
-1.2V 4 mA
-2V 2 mA
-4V 0 mA
9

5
ID

0
-4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0

VGS

ID=2 , VGS=-2

IDQ
Q-POINT

VGSQ
(iv) snapshot of circuit

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