Scribd
Upload
43 views1 page

Arf Lithography Technologies For 65Nm-Node Cmos (Cmos5) With 30Nm Logic Gate and High Density Embedded Memories

This document summarizes ArF lithography technologies for 65nm CMOS chips with 30nm logic gates and high density embedded memories. It discusses using ArF step-and-scan exposure systems with 0.75NA for all critical layers to narrow the lithography process window. It also discusses a gate fabrication process that includes both 30nm logic gates and high density embedded memory cells, achieved through special process steps implemented with two kinds of lithography.

Uploaded by

razu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
43 views1 page

Arf Lithography Technologies For 65Nm-Node Cmos (Cmos5) With 30Nm Logic Gate and High Density Embedded Memories

This document summarizes ArF lithography technologies for 65nm CMOS chips with 30nm logic gates and high density embedded memories. It discusses using ArF step-and-scan exposure systems with 0.75NA for all critical layers to narrow the lithography process window. It also discusses a gate fabrication process that includes both 30nm logic gates and high density embedded memory cells, achieved through special process steps implemented with two kinds of lithography.

Uploaded by

razu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

ArF Lithography Technologies for 65nm-node CMOS (CMOS5)

with 30nm Logic Gate and High Density Embedded Memories


Kohji Hashimoto, Fumikatsu Uesawa*, Kazuhiro Takahata, Koji Kikuchi*, Hideki
Kanai, Hideo Shimizu*, Eishi Shiobara, Koichi Takeuchi*, Ayako Endo,
Hideaki Harakawa and Shoji Mimotogi
Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation,
*
Technology Development Group, Semiconductor Network Company, Sony Corporation,
8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
Abstract
This paper presents ArF lithography technologies for 65nm-node
CMOS with 30nm logic gate and high density embedded memories. The
technologies consist of two major concepts. One is the approach to narrow
lithography process window. Since ArF step-and-scan exposure systems
with 0.75NA are implemented to all critical layers, the accurate lithography
design for low k1 lithography is needed. The other is gate fabrication
process which includes both 30nm logic gates and high density embedded
memory cells. For this achievement, special process steps are implemented
with two kinds of lithography.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy