UNIT-3

MOS INVERTER
BASIC NMOS INVERTER-

 In ideal inverter circuits, both the input variable A and the output variable B are represented
by node voltages.

 Here the Boolean value of ‘1’ means logic 1 can be represented by a high voltage of 𝑉𝐷𝐷 and
the Boolean value of ‘0’ means logic ‘0’ can be represented by a low voltage of ‘0’. The voltage
𝑉𝑡ℎ is called the inverter threshold voltage.

 For any input voltage between 0 to 𝑉𝑡ℎ the output voltage is equal to 𝑉𝐷𝐷 . The output
switches from 𝑉𝐷𝐷 to 0 when the input is equal to 𝑉𝑡ℎ .
 For any input voltage between 𝑉𝑡ℎ and𝑉𝐷𝐷 , the output voltage is equal to ‘0’. Thus an input
voltage 0≤ 𝑉𝑖𝑛 < 𝑉𝑡ℎ is interpreted by this ideal inverter as a logic ‘0’.While an input voltage
𝑉𝑡ℎ < 𝑉𝑖𝑛 ≤ 𝑉𝐷𝐷 is interpreted as a logic ‘1’.
 The input voltage of the inverter circuit is the gate to source voltage of the NMOS transistor.
While the output voltage of the circuit is equal to the drain to source voltage.
 The source and the substrate terminals of the NMOS transistor are connected to ground
potential. Hence 𝑉𝑆𝐵 = 0. The NMOS transistor is used as a driver transistor.
 The drain of NMOS is connected to the output terminal. The load device is represented as a
two terminal circuit element with terminal current𝐼𝐿 𝑎𝑛𝑑 𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑙 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝐿.
 One terminal of the load device is connected to the drain of the NMOS, while the other
terminal is connected to 𝑉𝐷𝐷 .
VTC Curve-

 VTC curve, which is a plot of input vs output voltage. The VTC indicates that for low input
voltage the circuit output is high and for high input, the output decreases towards 0 volt.
 Applying Kirchhoff’s current law, the load current is always equal to the NMOS drain current.
𝐼𝐷 = 𝐼𝐿
 For very low input voltage levels the output voltage 𝑉𝑜𝑢𝑡 is equal to the high value of 𝑉𝑂𝐻 .
The driver NMOS transistor is in cut off and hence does not conduct any current. The voltage
drop across the load device is very small in magnitude and the output voltage is high.
 As the input voltage 𝑉𝑖𝑛 increases, the driver transistor starts conducting a drain current and
the output voltage starts to decrease. This drop in the output voltage level does not occur
abruptly but in an ideal inverter it occur abruptly.
 In this curve two critical voltage points are present, where the slope becomes equal to -1.
𝑑𝑉𝑜𝑢𝑡
= −1
𝑑𝑉𝑖𝑛

 The smaller input voltage at which first slope occur is called the input low voltage ‘𝑉𝐼𝐿 ’ and
the larger input voltage at which second slope occur is called the input high voltage ‘𝑉𝐼𝐻 ’.
 As the input voltage is further increased, the output voltage continues to drop and reaches a
value of ′𝑉𝑂𝐿 ‘, when the input voltage is equal to ‘𝑉𝑂𝐻 ’. The inverter threshold voltage 𝑉𝑡ℎ
which is considered as the transition voltage is defined as the point where 𝑉𝑂𝑈𝑇 = 𝑉𝑖𝑛 .

RESISTIVE LOAD INVERTER-

Here, enhancement type nMOS acts as the driver transistor. The load consists of a simple linear
resistor RL. The power supply of the circuit is VDD and the drain current ID is equal to the load current
IR .

Circuit Operation

 When the input of the driver transistor is less than threshold voltage, driver transistor is
in cut off region and does not conduct any current. So, the voltage drop across the load
resistor is zero and output voltage is equal to the 𝑉𝐷𝐷 .
 Here𝐼𝑅 = 𝐼𝐷 .
 So, output voltage 𝑉𝑜𝑢𝑡 is

𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝐼𝑅 𝑅
 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅
 So, Drain current equation will be
𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡
𝐼𝐷 =
𝑅
 When the input voltage increases further, driver transistor will start conducting the non-
zero current and NMOS goes in saturation region.
 if MOSFET is there in saturation region then
𝐾
𝑉𝑖𝑛 − 𝑉𝑇𝑜 < 𝑉𝑜𝑢𝑡 and 𝐼𝐷 = 2 ( 𝑉𝐺𝑆 − 𝑉𝑇𝑂 ) 2
 If MOSFET is there in linear region then
𝐾
𝑉𝑖𝑛 − 𝑉𝑇𝑜 > 𝑉𝑜𝑢𝑡 and 𝐼𝐷 = 2 [2(𝑉𝐺𝑆 − 𝑉𝑇𝑂 )𝑉𝐷𝑆 − 𝑉𝐷𝑆 2 ]
VTC curve-
 Initially when input is at lower voltage, the NMOS is at cut off region, the 𝑉𝑜𝑢𝑡 is equal to
𝑉𝐷𝐷 until the NMOS is not turned ON.
 Once the NMOS turned ON, slow decrease in output voltage starts.

𝐕𝐎𝐇-
 Output voltage 𝑉𝑜𝑢𝑡 is

𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅

=> 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷

=> 𝑉𝑂𝐻 = 𝑉𝐷𝐷
𝐕𝐎𝐋 -
 When 𝑉𝑖𝑛 − 𝑉𝑇𝑜 > 𝑉𝑜𝑢𝑡 , MOSFET is there in linear region, so, drain current will be
 𝐾
𝐼𝐷 = 2 [2(𝑉𝑖𝑛 − 𝑉𝑇𝑂 )𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2 ]
 According to kirchoff’s law in the drain current is
𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡
𝐼𝐷 =
𝑅
 If we compare these two equations
𝑉𝐷𝐷 −𝑉𝑜𝑢𝑡 𝐾
= 2 [2(𝑉𝑖𝑛 − 𝑉𝑇𝑂 )𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2 ]
𝑅

𝑉𝐷𝐷 −𝑉𝑂𝐿 𝐾
=> = 2 [2(𝑉𝐷𝐷 − 𝑉𝑇𝑂 )𝑉𝑂𝐿 − 𝑉𝑂𝐿 2 ]
𝑅

=> 𝑉𝑂𝐿 2 − 2(𝑉𝐷𝐷 − 𝑉𝑇𝑂 + 1⁄𝐾𝑅)𝑉𝑂𝐿 + 2⁄𝐾𝑅 𝑉𝐷𝐷 = 0

 If we solve the above equation, we get

1 2 2𝑉𝐷𝐷
𝑉𝑂𝐿 = 𝑉𝐷𝐷 − 𝑉𝑇𝑂 + 1⁄𝐾𝑅 − √(𝑉𝐷𝐷 − 𝑉𝑇𝑂 + ) −
𝐾𝑅 𝐾𝑅
𝐕𝐈𝐋 -
 When 𝑉𝑖𝑛 − 𝑉𝑇𝑜 < 𝑉𝑜𝑢𝑡 MOSFET is there in saturation region, so drain current will be
𝐾
( 𝑉 − 𝑉𝑇𝑂 ) 2
𝐼𝐷 =
2 𝑖𝑛
 Again compare the equation with circuit drain current equation
𝑉𝐷𝐷 −𝑉𝑜𝑢𝑡 𝐾
= 2 ( 𝑉𝑖𝑛 − 𝑉𝑇𝑂 ) 2
𝑅
 We have to differentiate it with respect to 𝑉𝑖𝑛
𝑉𝐷𝐷 −𝑉𝑜𝑢𝑡 𝑑𝑉𝑜𝑢𝑡 𝐾 𝑑𝑉𝑜𝑢𝑡
( ) 𝑑𝑉 = [ 2 ( 𝑉𝑖𝑛 − 𝑉𝑇𝑂 ) 2 ]
𝑅 𝑖𝑛 𝑑𝑉𝑖𝑛

1 𝑑𝑉𝑜𝑢𝑡
=≻ − 𝑅 = 𝐾 (𝑉𝑖𝑛 − 𝑉𝑇𝑂 )
𝑑𝑉𝑖𝑛

1
=≻ 𝑅 = 𝐾(𝑉𝐼𝐿 − 𝑉𝑇𝑂 )

=> 𝑉𝐼𝐿 = 𝑉𝑇𝑂 + 1⁄𝐾𝑅

𝐕𝐈𝐇 -
 When 𝑉𝑖𝑛 − 𝑉𝑇𝑜 > 𝑉𝑜𝑢𝑡 MOSFET is there in linear region, so drain current will be
𝐾
𝐼𝐷 = 2 [2(𝑉𝑖𝑛 − 𝑉𝑇𝑂 )𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2 ]

Compare the equation with circuit drain current equation

𝑉𝐷𝐷 −𝑉𝑜𝑢𝑡 𝐾
= 2 [2(𝑉𝑖𝑛 − 𝑉𝑇𝑂 )𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡 2 ]
𝑅
 We have to differentiate it with respect to 𝑉𝑖𝑛
 1 𝑑𝑉𝑜𝑢𝑡 𝑑𝑉 𝑑𝑉
−𝑅 = 𝐾⁄2 [2(𝑉𝑖𝑛 − 𝑉𝑇𝑂 ) 𝑑𝑉𝑜𝑢𝑡 + 2𝑉𝑜𝑢𝑡 − 2𝑉𝑜𝑢𝑡 𝑑𝑉𝑜𝑢𝑡 ]
𝑑𝑉𝑖𝑛 𝑖𝑛 𝑖𝑛

1
=≻ = 𝐾⁄2 [−2(𝑉𝐼𝐻 − 𝑉𝑇𝑂 ) + 4 𝑉𝑜𝑢𝑡 ]
𝑅
1
=> = −(𝑉𝐼𝐻 − 𝑉𝑇𝑂 ) + 2 𝑉𝑜𝑢𝑡
𝐾𝑅
1
=> = −𝑉𝐼𝐻 + 𝑉𝑇𝑂 + 2𝑉𝑜𝑢𝑡
𝐾𝑅
1
=> 𝑉𝐼𝐻 = 𝑉𝑇𝑂 + 2𝑉𝑜𝑢𝑡 −
𝐾𝑅

INVERTER WITH N-TYPE MOSFET LOAD-

The main advantage of using MOSFET as load device is that the silicon area occupied by the
transistor is smaller than the area occupied by the resistive load. Here, MOSFET is active load
and inverter with active load gives a better performance than the inverter with resistive load.
Enhancement load-
Load transistor can be operated either, in saturation region or in linear region, depending on
the bias voltage applied to its gate terminal. The saturated enhancement load inverter is
shown in the first figure. It requires a single voltage supply and simple fabrication process
and so VOH is limited to the VDD − VT.

The linear enhancement load inverter is shown in the second figure. It always operates in
linear region; so VOH level is equal to VDD.
 Linear load inverter has higher noise margin compared to the saturated enhancement
inverter. But, the disadvantage of linear enhancement inverter is, it requires two separate
power supply and both the circuits suffer from high power dissipation. Therefore,
enhancement inverters are not used in any large-scale digital applications.
Depletion load NMOS-

 Drawbacks of the enhancement load inverter can be overcome by using depletion load
inverter. Compared to enhancement load inverter, depletion load inverter requires few
more fabrication steps for channel implant to adjust the threshold voltage of load.
 The advantages of the depletion load inverter are - sharp VTC transition, better noise
margin, single power supply and smaller overall layout area.
 The gate and source terminal of load are connected; So, VGS = 0. Thus, the threshold voltage
of the load is negative. Hence,
𝑉𝐺𝑆,𝑙𝑜𝑎𝑑 > 𝑉𝑇,𝑙𝑜𝑎𝑑
Therefore, load device always has a conduction channel regardless of input and output
voltage level.
 When the load transistor is in saturation region, the load current is given by
𝐾
𝐼𝐷,𝑙𝑜𝑎𝑑 = 𝑛,𝑙𝑜𝑎𝑑 [−𝑉𝑇,𝑙𝑜𝑎𝑑 (𝑉𝑜𝑢𝑡 )]
2

 When the load transistor is in linear region, the load current is given by
𝐾𝑛,𝑙𝑜𝑎𝑑
𝐼𝐷,𝑙𝑜𝑎𝑑 = [2|𝑉𝑇,𝑙𝑜𝑎𝑑 (𝑉𝑜𝑢𝑡 )|. (𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 ) − (𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 )2 ]
2
The voltage transfer characteristics of the depletion load inverter is shown in the figure
given below −

CMOS INVERTER-
In CMOS inverter NMOS work as driver and PMOS transistors work as load and always one
transistor is ON, other is OFF.

This configuration is called complementary MOS (CMOS). The input is connected to

the gate terminal of both the transistors such that both can be driven directly with input
voltages. Substrate of the NMOS is connected to the ground and substrate of the PMOS is
connected to the power supply, VDD.
So VSB = 0 for both the transistors.
𝑉𝐺𝑆,𝑛 = 𝑉𝑖𝑛
𝑉𝐷𝑆,𝑛 = 𝑉𝑂𝑈𝑇

And,
 𝑉𝐺𝑆,𝑛 = 𝑉𝑖𝑛 − 𝑉𝐷𝐷
𝑉𝐷𝑆,𝑛 = 𝑉𝑜𝑢𝑡 − 𝑉𝐷𝐷

When the input of nMOS is smaller than the threshold voltage (V in < VTO,n), the nMOS is cut
– off and pMOS is in linear region. So, the drain current of both the transistors is zero.
𝐼𝐷,𝑛 = 𝐼𝐷,𝑝 = 0
Therefore, the output voltage VOH is equal to the supply voltage.
𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐻 = 𝑉𝐷𝐷
When the input voltage is greater than the VDD + VTO,p, the pMOS transistor is in the cutoff
region and the nMOS is in the linear region, so the drain current of both the transistors is
zero.
𝐼𝐷,𝑛 = 𝐼𝐷,𝑝 = 0
Therefore, the output voltage VOL is equal to zero.
𝑉𝑜𝑢𝑡 = 𝑉𝑂𝐿 = 0
The nMOS operates in the saturation region if V in > VTO and if following conditions are
satisfied.
𝑉𝐷𝑆,𝑛 ≥ 𝑉𝐺𝑆,𝑛 − 𝑉𝑇𝑂,𝑛
𝑉𝑜𝑢𝑡 ≥ 𝑉𝑖𝑛 − 𝑉𝑇𝑂,𝑛
The pMOS operates in the saturation region if Vin < VDD + VTO,p and if following conditions
are satisfied.
𝑉𝐷𝑆,𝑃 ≤ 𝑉𝐺𝑆,𝑃 − 𝑉𝑇𝑂,𝑃
𝑉𝑜𝑢𝑡 ≥ 𝑉𝑖𝑛 − 𝑉𝑇𝑂,𝑃
For different value of input voltages, the operating regions are listed below for both
transistors.

Region Vin Vout nMOS pMOS

A < VTO, n VOH Cut – off Linear

B VIL High ≈ VOH Saturation Linear

C Vth Vth Saturation Saturation

 D VIH Low ≈ VOL Linear Saturation

E > (VDD + VTO, p) VOL Linear Cut – off

The VTC of CMOS is shown in the figure below −

INTERCONNECT EFFECTS-
DELAY TIME DEFINATION-
The propagation delay times 𝜏𝑃𝐻𝐿 and 𝜏𝑃𝐿𝐻 determine the input to output signal delay
during the high to low and low to high transitions of the output, respectively.
Definition-
𝜏𝑃𝐻𝐿 is the time delay between the 𝑉50% transition of the rising input voltage and the
𝑉50% transition of the falling output voltage.
𝜏𝑃𝐿𝐻 is the time delay between the 𝑉50% transition of the falling input voltage and the
𝑉50% transition of the rising output voltage.
𝜏𝑃𝐻𝐿 becomes the time required for the output voltage to fall from 𝑉𝑂𝐻 to the 𝑉50% level and
𝜏𝑃𝐿𝐻 becomes the time required for the output voltage to rise from 𝑉𝑂𝐿 to the 𝑉50% level.
1
𝑉50% = 𝑉𝑂𝐿 + (𝑉𝑂𝐻 − 𝑉𝑂𝐿 )
2
 = ½ (𝑉𝑂𝐿 + 𝑉𝑂𝐻 )
𝜏𝑃𝐻𝐿 = 𝑡1 − 𝑡0
𝜏𝑃𝐿𝐻 = 𝑡3 − 𝑡2
Average propagation delay is
𝜏𝑃𝐻𝐿 + 𝜏𝑃𝐿𝐻
𝜏𝑝 =
2

INVERTER DESIGN WITH DELAY CONSTRAINTS-

The design of CMOS inverters based on timing specifications is one of the most
fundamental issues in digital circuit design which ultimately determine the overall
performance of complex systems.

The load capacitance 𝐶𝑙𝑜𝑎𝑑 consists of intrinsic components and extrinsic components.
If 𝐶𝑙𝑜𝑎𝑑 consists of extrinsic components and if this overall load capacitance can be
estimated accurately and independently of the transistor dimensions, then the problem of
inverter design can be reduced. Given a required delay value of 𝜏𝑃𝐻𝐿 , the (W/L) ratio of the
NMOS transistor can be found as
𝑊𝑛 𝐶𝑙𝑜𝑎𝑑 2𝑉𝑇,𝑛 4(𝑉𝐷𝐷 − 𝑉𝑇,𝑛 )
= [ + 𝑙𝑛 ( − 1)]
𝐿𝑛 𝜏𝑃𝐻𝐿 µ𝑛 𝐶𝑜𝑥 (𝑉𝐷𝐷 − 𝑉𝑇,𝑛 ) 𝑉𝐷𝐷 − 𝑉𝑇,𝑛 𝑉𝐷𝐷

Similarly, the (W/L) ratio of the PMOS transistor to satisfy a given target value of 𝜏𝑃𝐿𝐻 can
be calculated as
𝑊𝑃 𝐶𝑙𝑜𝑎𝑑 2|𝑉𝑇,𝑃 | 4(𝑉𝐷𝐷 − |𝑉𝑇,𝑃 |)
= [ + 𝑙𝑛 ( − 1)]
𝐿𝑃 𝜏𝑃𝐿𝐻 µ𝑃 𝐶𝑜𝑥 (𝑉𝐷𝐷 − |𝑉𝑇,𝑃 |) 𝑉𝐷𝐷 − |𝑉𝑇,𝑃 | 𝑉𝐷𝐷

Assumed that the combined output load capacitance is mainly dominated by its extrinsic
components, and hence, that is not very sensitive to device dimensions.
𝐶𝑙𝑜𝑎𝑑 = 𝐶𝑔𝑑,𝑛 (𝑊𝑛 ) + 𝐶𝑔𝑑,𝑝 (𝑊𝑝 ) + 𝐶𝑑𝑏,𝑛 (𝑊𝑛 ) + 𝐶𝑑𝑏,𝑝 (𝑊𝑝 ) + 𝐶𝑖𝑛𝑡 + 𝐶𝑔

= f (𝑊𝑛 , 𝑊𝑝 )

The fan out capacitance 𝐶𝑔 is also a function of the device dimensions in the next stage gate.
 Simplified CMOS inverter mask layout used for delay analysis
Here the diffusion areas of both NMOS and PMOS transistors have a simple rectangular
geometry and the drain region length is assumed to be same for both devices. The relatively
small gate to drain capacitances 𝐶𝑔𝑑,𝑛 𝑎𝑛𝑑 𝐶𝑔𝑑,𝑝 will be neglected. The drain parasitic
capacitances can be found as
𝐶𝑑𝑏,𝑛 = 𝑊𝑛 𝐷𝑑𝑟𝑎𝑖𝑛 𝐶𝑗0,𝑛 𝐾𝑒𝑞,𝑛 + 2(𝑊𝑛 + 𝐷𝑑𝑟𝑎𝑖𝑛 )𝐶𝑗𝑠𝑤,𝑛 𝐾𝑒𝑞,𝑛

𝐶𝑑𝑏,𝑝 = 𝑊𝑝 𝐷𝑑𝑟𝑎𝑖𝑛 𝐶𝑗0,𝑝 𝐾𝑒𝑞,𝑝 + 2(𝑊𝑝 + 𝐷𝑑𝑟𝑎𝑖𝑛 )𝐶𝑗𝑠𝑤,𝑝 𝐾𝑒𝑞,𝑝

Where 𝐶𝑗0,𝑛 and 𝐶𝑗0,𝑝 denote the zero bias junction capacitances for n-type and p-type
diffusion regions, 𝐶𝑗𝑠𝑤,𝑛 and 𝐶𝑗𝑠𝑤,𝑝 denote the zero bias sidewall junction capacitances and
𝐾𝑒𝑞,𝑛 and 𝐾𝑒𝑞,𝑝 denote the voltage equivalence factors. The combined output load capacitance
then becomes
𝐶𝑙𝑜𝑎𝑑 = (𝑊𝑛 𝐶𝑗0,𝑛 𝐾𝑒𝑞,𝑛 + 𝑊𝑝 𝐶𝑗0,𝑝 𝐾𝑒𝑞,𝑝 )𝐷𝑑𝑟𝑎𝑖𝑛 + 2(𝑊𝑛 + 𝐷𝑑𝑟𝑎𝑖𝑛 )𝐶𝑗𝑠𝑤,𝑛 𝐾𝑒𝑞,𝑛
+ 2(𝑊𝑝 + 𝐷𝑑𝑟𝑎𝑖𝑛 )𝐶𝑗𝑠𝑤,𝑝 𝐾𝑒𝑞,𝑝 + 𝐶𝑖𝑛𝑡 + 𝐶𝑔

Thus the total capacitive load of the inverter can be expressed as

𝐶𝑙𝑜𝑎𝑑 = 𝛼0 + 𝛼𝑛 𝑊𝑛 + 𝛼𝑝 𝑊𝑝

Where 𝛼0 = 2𝐷𝑑𝑟𝑎𝑖𝑛 (𝐶𝑗𝑠𝑤,𝑛 𝐾𝑒𝑞,𝑛 + 𝐶𝑗𝑠𝑤,𝑝 𝐾𝑒𝑞,𝑝 ) + 𝐶𝑖𝑛𝑡 + 𝐶𝑔

𝛼𝑛 = 𝐾𝑒𝑞,𝑛 (𝐶𝑗0,𝑛 𝐷𝑑𝑟𝑎𝑖𝑛 + 2𝐶𝑗𝑠𝑤,𝑛 )

𝛼𝑝 = 𝐾𝑒𝑞,𝑝 (𝐶𝑗0,𝑝 𝐷𝑑𝑟𝑎𝑖𝑛 + 2𝐶𝑗𝑠𝑤,𝑝 )

 UNIT-4
STATIC COMBINATIONAL, SEQUENTIAL, DYNAMICS LOGIC CIRCUITS
& MEMORIES
STATIC CMOS LOGIC CIRCUITS-
Static CMOS is a logic circuit design technique whereby the output is always strongly driven due
to it always being connected to either VCC or GND (except when switching). This design is in
contrast to Dynamic CMOS which relies on the temporary storage of signal using various load
capacitances.

A static CMOS circuit is composed of two networks:

 pull-up network (PUN) - a set of PMOS transistors connected between Vcc and the output line
 pull-down network (PDN) - a set of NMOS transistors connected between GND and the output
line
Components designed out pull-up and pull-down networks operate in a mutually exclusive way;
in a steady state there is never a direct path between Vcc and GND. Devices that are made up of
PUN/PDN are always strongly driven and therefore offers strong immunity from noise. When
both the pull-up and pull-down networks are OFF, the result is high impedance. That state is
important for memory elements, tristate bus drives, and various other components such as some
multiplexers and buffers. When both the pull-up and pull-down networks are ON, the result is
a crowbarred level. This result is typically an unwanted condition

CMOS NAND2 Gate-

 The below figure shows a 2-input Complementary MOS NAND gate. It consists of two series
NMOS transistors between Y and Ground and two parallel PMOS transistors between Y and
VDD.
 If either input A or B is logic 0, at least one of the NMOS transistors will be OFF, breaking
the path from Y to Ground. But at least one of the PMOS transistors will be ON, creating a
path from Y to VDD.
 Two Input NAND Gate
Hence, the output Y will be high. If both inputs are high, both of the nMOS transistors will be
ON and both of the pMOS transistors will be OFF. Hence, the output will be logic low. The
truth table of the NAND logic gate given in the below table.

Pull-Down
A B Network Pull-up Network OUTPUT Y
0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 ON OFF 0

CMOS TRANSMISSION GATES-

CMOS transmission gate consists of one NMOS and one PMOS transistor, connected in
parallel. The gate voltages applied to these two transistors are also set to be complementary
signals.

Symbols-
The CMOS transmission gate operates as a bidirectional switch between the nodes A and B
which is controlled by signal C.
If the control signal C is
(i) Logic high i.e, equal to𝑉𝐷𝐷 , then both transistors are turned on and provide a low
resistance current path between the nodes A and B.
(ii) Logic low then both transistors will be off and the path between the nodes A and
B will be an open circuit. This condition is called the high impedance state.

The substrate terminal of the NMOS transistor is connected to ground and the substrate
terminal of the PMOS transistor is connected to 𝑉𝐷𝐷 .
C A B
0 0 High impedance State
0 1 High impedance State
1 0 0
1 1 1

COMPLEX LOGIC CIRCUITS-

NMOS Depletion Load Complex Logic Gate

To realize complex functions of multiple input variables, the basic circuit structures and
design principles developed for NOR and NAND can be extended to complex logic gates. The
ability to realize complex logic functions, using a small number of transistors is one of the
most attractive features of nMOS and CMOS logic circuits. Consider the following Boolean
function as an example.
Z=(P(S+T)+QR)’
The nMOS depletion-load complex logic gate used to realize this function is shown in figure.
In this figure, the left nMOS driver branch of three driver transistors is used to perform the
logic function P (S + T), while the right-hand side branch performs the function QR. By
connecting the two branches in parallel, and by placing the load transistor between the
output node and the supply voltage VDD, we obtain the given complex function. Each input
variable is assigned to only one driver.

Inspection of the circuit topology gives simple design principles of the pull-down network

 OR operations are performed by parallel-connected drivers.

 AND operations are performed by series-connected drivers.
 Inversion is provided by the nature of MOS circuit operation.

Complex CMOS Logic Gates-

The realization of the n-net, or pull-down network, is based on the same basic design
principles examined for nMOS depletion-load complex logic gate. The pMOS pull-up
network must be the dual network of the n-net.
It means all parallel connections in the nMOS network will correspond to a series
connection in the pMOS network, and all series connection in the nMOS network correspond
to a parallel connection in the pMOS network. The figure shows a simple construction of the
dual p-net (pull-up) graph from the n-net (pull-down) graph.
Using an arbitrary ordering of the polysilicon gate columns-
X= (A(D+E)+BC)’
If we can minimize the number of diffusion area breaks both for NMOS and for PMOS
transistors, the separation between the polysilicon gate columns can be made smaller,
which will reduce the overall horizontal dimension and hence the circuit layout area. The
number of diffusion breaks can be minimized by changing the ordering of the polysilicon
columns.
A simple method for finding the optimum gate ordering is the Euler-path approach: find a
Euler path in the pull down graph and a Euler path in the pull-up graph with identical
ordering of input labels i.e, find a common Euler path for both graphs.
The Euler path is defined as an uninterrupted path that traverses each edge (branch)
of the graph exactly once.
 There is a common sequence (E-D-A-B-C) in both graphs i.e, a Euler path. The polysilicon
gate columns can be arranged according to this sequence.

AOI and OAI gates-

 The AND-OR-INVERT (AOI) gate enables the sum of products realization of a Boolean
function in one logic stage. The pull down network of the AOI gate consists of parallel
branches of series connected NMOS driver transistors.
 The OAI gate, enables the product-of-sums realization of a Boolean function in one logic
stage. The pull down network of the OAI gate consists of series branches of parallel
connected NMOS driven transistors.

Pseudo-NMOS gates-
 The large area requirements of complex CMOS gates present a problem in high density
designs, since two complementary transistors, one NMOS and one PMOS, are needed for
every input.
 One possible approach to reduce the number of transistor is to use a single PMOS
transistor, with its gate terminal connected to ground, as the load device.
 With this simple pull up arrangement, the complex gate can be implemented with much
fewer transistors.
 The disadvantages of using a pseudo NMOS gate instead of a full CMOS gate is the nonzero
static power dissipation, since the always on PMOS load device conducts a steady state
current when the output voltage is lower than 𝑉𝐷𝐷.

CLASSIFICATION OF LOGIC CIRCUITS BASED ON THEIR TEMPORAL

BEHAVIOUR-
Logic circuits are divided into two categories − (a) Combinational Circuits, and (b)
Sequential Circuits.
In Combinational circuits, the output depends only on the condition of the latest inputs.
In Sequential circuits, the output depends not only on the latest inputs, but also on the
condition of earlier inputs. Sequential circuits contain memory elements.

Sequential circuits are of three types −

Bistable − Bistable circuits have two stable operating points and will be in either of the
states. Example − Memory cells, latches, flip-flops and registers.
Monostable − Monostable circuits have only one stable operating point and even if they are
temporarily perturbed to the opposite state, they will return in time to their stable
operating point. Example: Timers, pulse generators.
Astable – Astable circuits have no stable operating point and oscillate between several
states. Example − Ring oscillator.
SR LATCH CIRCUIT-

SR Latch based on NOR Gate-

If the set input (S) is equal to logic "1" and the reset input is equal to logic "0." then the
output Q will be forced to logic "1". While Q’ is forced to logic "0". This means the SR latch
will be set, irrespective of its previous state.
Similarly, if S is equal to "0" and R is equal to "1" then the output Q will be forced
to "0" while Q’ is forced to "1". This means the latch is reset, regardless of its previously
held state. Finally, if both of the inputs S and R are equal to logic "1" then both output will
be forced to logic "0" which conflicts with the complementarity of Q and Q’.
Therefore, this input combination is not allowed during normal operation. Truth table of
NOR based SR Latch is given in table.

S R Q Q’ Operation

0 0 Q Q’ Hold

1 0 1 0 Set

0 1 0 1 Reset

1 1 0 0 Not allowed

CMOS SR latch based on NOR gate is shown in the figure given below.
If the S is equal to V and the R is equal to V , both of the parallel-connected transistors M1
OH OL

and M2 will be ON. The voltage on node Q’ will assume a logic-low level of V = 0.OL

At the same time, both M3 and M4 are turned off, which results in a logic-high voltage V at
OH

node Q. If the R is equal to V and the S is equal to V , M1 and M2 turned off and M3 and M4
OH OL

turned on.

SR Latch based on NAND Gate

Block diagram and gate level schematic of NAND based SR latch is shown in the figure. The
small circles at the S and R input terminals represents that the circuit responds to active
low input signals. The truth table of NAND based SR latch is given in table

S R Q Q′ OPERATION

0 0 NC NC No change. Latch remained in present

state.

1 0 1 0 Latch SET.
 0 1 0 1 Latch RESET.

1 1 0 0 Invalid condition.

If S goes to 0 (while R = 1), Q goes high, pulling Q’ low and the latch enters Set state
S = 0 then Q = 1 (if R = 1)
If R goes to 0 (while S = 1), Q goes high, pulling Q’low and the latch is Reset
R = 0 then Q = 1 (if S = 1)
Hold state requires both S and R to be high. If S = R = 0 then output is not allowed, as it
would result in an indeterminate state. CMOS SR Latch based on NAND Gate is shown in
figure.

Depletion-load nMOS SR Latch based on NAND Gate is shown in figure. The operation is
similar to that of CMOS NAND SR latch. The CMOS circuit implementation has low static
power dissipation and high noise margin.
CLOCKED SR LATCH-
For synchronous operations the circuit response can be controlled by adding a gating clock
signal to the circuit, so that the outputs will respond to the input levels only during the
active period of a clock pulse.
If the clock (CK) is equal to logic “0”, the input signals have no influence upon the circuit
response. The outputs of the two AND gates will remain at logic “0”, which forces SR latch
to hold its current state regardless of the S and R input signals.
When the clock input goes to logic “1”, the logic levels applied to the S and R inputs are
permitted to reach the SR latch and possibly change its state.
 With both inputs S and R at logic “1”, the occurrence of clock pulse causes both outputs to
go momentarily to zero. When the clock pulse is removed i.e, when it becomes “0”, the state
of the latch is undermined.

CMOS AOI implementation of clocked NOR based SR latch is shown in the figure. If this
circuit is implemented with CMOS then it requires 12 transistors.
 When CLK is low, the latch retains its present state.
 When clock is high, the circuit becomes simply a NOR based CMOS latch which will
respond to input S and R.
CMOS D LATCH-
 The D latch is simply obtained by modifying the clocked NOR based SR latch circuit. Here,
the circuit has a single input D, which is directly connected to the S input of the latch.
 The input variable D is also inverted and connected to the R input of the latch. The output Q
assumes the value of the input D when the clock is active.
 When the clock signal goes to zero, the output will preserve its state. Thus the CK input acts
as an enable signal which allows data to be accepted into the D latch.
 The D latch finds many applications mainly for temporary storage of data or as a delay
element.

D latch using CMOS logic-

. If this circuit is implemented with CMOS then it requires 12 transistors.

D latch using transmission gate-

The transmission gate at the input is activated by the CK signal, whereas the transmission
gate in the inverter loop is activated by the inverse of the CK signal.
The input signal is accepted into the circuit when the clock is high and this information
preserved as the state of the inverter loop when the clock is low.
The operation of the CMOS D latch circuit can be better visualized by replacing the CMOS
transmission gates with simple switches.

BASIC PRINCIPLES OF DYNAMIC PASS TRANSISTOR CIRCUITS-

In static CMOS logic, logic function implemented using large no. of transistors and
which may cause large time delay.
In a high performance digital implementations where reduction of circuit delay and silicon
area is a major objective to achieve these dynamic logic circuits are used.
Here no. of transistor used decreases. The operation of all dynamic logic gates depends on
temporary storage of charge in parasitic node capacitances.
Basic Principle
NMOS dynamic logic circuits, consisting of an NMOS pass transistor driving the gate of
another NMOS transistor.
The pass transistor MP is driven by the periodic clock signal and acts as an access switch to
either charge up or charge down the parasitic capacitance𝐶𝑋 , depending on the input signal
𝑉𝑖𝑛 .
Thus, the two possible operations when the clock signal is active (CK = 1) are the logic “1”
transfer and the logic “0” transfer.

Logic “1” transfer-

Assume that the 𝑉𝑋 node voltage is equal to 0 initially. A logic “1” level is applied to the input
terminal, which corresponds to 𝑉𝑖𝑛 = 𝑉𝑂𝐻 = 𝑉𝐷𝐷 . When the clock signal at the gate of the pass
transistor becomes active, the pass transistor MP starts to conduct and that MP will operate
in saturation.

The voltage rises from its initial value of 0V and approaches a limit value for large t, but it
cannot exceed its limit value of 𝑉𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑇,𝑛 .

The pass transistor will turn off when 𝑉𝑋 = 𝑉𝑚𝑎𝑥 , since at this point , its gate to source voltage
will be equal to its threshold voltage. Therefore the voltage at node X can never attain the
full power supply voltage level of 𝑉𝐷𝐷 during the logic “1” transfer.
Logic “0” transfer-
Assume that the node voltage 𝑉𝑋 is equal to a logic “1” level initially i.e, 𝑉𝑋 (𝑡 = 0) = 𝑉𝑚𝑎𝑥 =
(𝑉𝐷𝐷 − 𝑉𝑇,𝑛 ).A logic “0” level is applied to the input terminal, which corresponds to 𝑉𝑖𝑛 =0V.

The pass transistor MP starts to conduct as soon as the clock signal becomes active and the
direction of drain current flow through MP will be opposite to that during the charge up
(logic “1” transfer).

RAM-
The read/write memory is commonly called Random Access Memory(RAM). Here the stored
data is volatile i.e, the stored data is lost when the power supply voltage is turned off.
 Based on the operation type of individual data storage cells, RAMs are classified into two
categories-
1) Dynamic RAMs (DRAM)
 The DRAM cell consists of a capacitor to store binary information, 1 or 0 and a transistor
to access the capacitor.
 Cell information is degraded mostly due to a junction leakage current at the storage node.
Therefore the cell data must be read and rewritten periodically (refresh operation) even
when memory arrays are not accessed.
 Due to advantage of low cost and high density, DRAM is widely used for the main memory
in personal and mainframe computers and engineering workstations
2) Static RAMs (SRAM)
 SRAM cell consists of a latch, therefore the cell data is kept as long as the power is turned
on and refresh operation is not required.
 SRAM is mainly used for the cache memory in microprocessors, mainframe computers,
engineering workstations due to high speed and low power consumption.
DYNAMIC RAM-
The binary information is stored in the form of charge in the parasitic node capacitance C1.
The storage transistor M2 is turned on or off depending on the charge stored in C1, and the
pass transistors M1 and M3 act as access switches for data read and write operations.

 The operation of the three transistor DRAM cell and the peripheral circuitry is based on a
two phase non- overlapping clock scheme.
1) The precharge events are driven by ∅1 .
2) The “read” and “write” events are driven by ∅2 .
 Every “data read” and “data write” operation is preceded by a precharge cycle, which is
initiated with the precharge signal PC going high.
 During the precharge cycle, the column pull up transistors are activated and the
corresponding column capacitances C2 and C3 are charged up to logic high level.

Write “1”-

 The inverse data input is at the logic low level, because the data to be written onto the
DRAM cell is logic “1”.
 The “write select” signal WS is pulled high during the active phase of ∅2 .
 The transistor M1 is turned on. With M1 conducting, the charge on C2 is shared with C1.
 Since the capacitance C2 is very large compared to C1, the storage node capacitance C1
attains approximately the same logic high level as the column capacitance C2 at the end of
the charge sharing process.
Read “1”-
 With the storage node capacitance C1 charged up to a logic high level, transistor M2 is
conducting.
 In order to read this stored “1”, the “read select” signal RS pulled high during the active phase
of ∅2 , following a precharge cycle.
 As the transistor M3 turns on, M2 and M3 create a conducting path between the column
capacitance C3 and the ground.
 The capacitance C3 discharges through M2 and M3, and the falling column voltage is
interpreted as a stored logic “1”.
Write “0”-

 The inverse data input is at the logic high level, because the data to be written onto the
DRAM cell is a logic “0”.
 The “write select” signal WS is pulled high during the active phase of ∅2 , following a
precharge cycle.
 As a result, the transistor M1 is turned on. The voltage level on C2, as well as that on the
storage node C1, is pulled to logic “0” through M1.
 At the end of the write “0” sequence, the storage capacitance C1 contains a very low charge
and the transistor M2 is turned off since its gate voltage is approximately equal to zero.
Read “0”-
 In order to read this stored “0”, the read select signal RS pulled high during the active phase
∅2 , following a precharge cycle.
 The transistor M3 turns on, but since M2 is off, there is no conducting path between the C3
and ground. So, C3 does not discharge and the logic high level on the 𝐷𝑜𝑢𝑡 column is
interpreted as a stored “0” bit.

STATIC RAM (SRAM)-

A low power SRAM cell designed simply by using cross coupled CMOS inverters. The memory
cell consists of a simple CMOS latch (two inverters connected back to back), and two
complementary access transistors (M3 and M4).

The cell will preserve one of its two possible stable states as long as the power supply is
available. The access transistors are turned on whenever a word line is activated for read or
write operation, connecting the cell to the complementary bit line columns.
Read “0” operation-
 Assuming that a logic “0” is stored in the cell. Here the transistors M2 and M5= off and M1 and
M6= On (operate in linear mode).
 The internal node voltages are 𝑉1 =0V and 𝑉2 = 𝑉𝐷𝐷 before M3 and M4 are turned on.
 The voltage level of column C’ will not show any significant variation since no current flow
through M4.
 On the other half of the cell, M3 and M1 will conduct a non-zero current and the voltage level
of column C will begin to drop slightly.
 The capacitance 𝐶𝑐 is very large, therefore the amount of decrease in the column voltage is
limited to a few hundred millivolts during read phase.
Write “0” operation-

 Assuming that a logic “1” is stored in the SRAM cell initially. Here the transistors M1 and M6=
off and M2 and M5= On (operate in linear mode).
 The internal node voltages are 𝑉1 = 𝑉𝐷𝐷 and 𝑉2 = 0𝑉 before M3 and M4 are turned on.
 The column voltage 𝑉𝑐 is forced to logic “0” level by the data write circuitry. Once the pass
transistors M3 and M4 are turned on, we expect that the node voltage 𝑉2 remains below the
threshold voltage of M1.
 To change the stored information i.e, to force 𝑉1 𝑡𝑜 0𝑉 and 𝑉2 𝑡𝑜 𝑉𝐷𝐷 , the node voltage 𝑉1
must be reduced below the threshold voltage of M2 . so that M2 turns off.
 Similarly read “1” and write “0” operation can be done.
Basic Requirements-
The two basic requirements which dictate the (W/L) ratios are-
(a) The data read operation should not destroy the stored information in the SRAM cell.
(b) The cell should allow modification of the stored information during the data write phase.
Advantages-
1) The static power dissipation is very small.
2) High noise immunity due to larger noise margins and the ability to operate at lower power
supply voltages.
FLASH MEMORY-
Flash memory is a non- volatile memory chip used for storage. Flash memory is a type of
Electronically Erasable Programmable Read Only Memory (EEPROM).

In flash memory, each memory cell looks like standard MOSFET except that the transistor has
two gates instead of one.
The cells can be seen as an electrical switch in which current flows between two terminals
and is controlled by a floating gate and a control gate.
The control gate is similar to the gate in the MOS transistors, but below this there is the
floating gate insulated all around by an oxide layer.
The Floating gate is electrically isolated by its insulating layer, electrons placed on it are
trapped. This makes flash memory non-volatile.
It works by adding or removing electrons to and from a floating gate. A bit “0” or “1” state
depends upon whether or not the floating gate is charged or uncharged.
When electrons are present on the floating gate, current cannot flow through the transistor
and the bit state is “0”.
When electrons are removed from the floating gate, current is allowed to flow and the bit
state is “1”.
Two processes are used to add electrons in the floating gate:
1) Fowler Nordheim tunneling –

 It requires a strong electric field between negatively charged source and the
positively charged control gate to draw electrons into the floating gate.
 The electrons move from the source through the thin oxide layer to the floating gate,
where they are trapped between the oxide insulation layers.
2) Hot electron injection-

 It uses a high current in the channel to give electrons sufficient energy to break
through the oxide layer.
  A positive charge on the control gate attracts the electrons from the channel into the
floating gate, where they become trapped.
Fowler-Nordheim tunneling is also used to remove electrons from the floating gate. A strong
negative charge on the control gate forces electrons through the oxide layer into the channel,
where the electrons are drawn to the strong positive charge at the source and the drain

Types of flash memory-

1) NOR flash memory
2) NAND flash memory
 In both, memory cells are arranged differently. In a NAND memory chip, all floating gate
MOSFETs are organized in series. Here bit line is pulled low only if all the word lines are
pulled high.
 In a NOR flash, at least one memory cell must conduct in order to pull down the bit line,
because they are connected in parallel to ground.
 NOR flash uses more space than NAND to save the same amount of information, since two
flash cells share the same ground potential in this configuration. Therefore NAND is
cheaper.
 NOR memory needs less time to read a bit because of its direct access to individual cells.