Inverter 4027

The basic element required to produce a complete

range of logic circuit is incr

n
Er
UDD The basic construction
depletion mode NMOS inverter
1 n MOSFET of an

Vouet involves a depletion mode

enhancement mode n the

MOSFET in
in 4 n MOSFET
1 pull up section where
AND
drain is connected to

power supply Upp and gate is shorted to source

was _o to keep the transistor always ON

In the pull down section an n enhancement

mode transistor is placed to whose che
gate
given and whose is
input Vin is source
connected to ground
pie
As gate is shorted to mode
source of depletion
MOSFET Va 0 and transistor is always ON

and acts as a constant current source

when Vin _I The n Mos enhancement transistor

in the pull down section is ON As the
depletion mode transistor is always ON
 it the
charges output node Vane
Now as enhancement mode transistor is ON
this down
voltage Vout is pull as Ids flows
in the transistor and Now becomes 0

rDD

Iu mon

Vin
µFf't Vout llVpD
OFF No
Vin
EE
t ON
Crowe is
1 AND discharged
CND

Derivation invester transfer characteristics

of NMOS

mole
depletion
T7IYIgs oD

To obtain the transfer characteristics of NMOS

inverter the depletion mode transistor Vgs 0

curve is superimposed on the

family of curves

MOSFET enhancement
of n
 The points of intersection of the curves give
points on the transfer characteristics

The transfer characteristics

are drawn between
Vim and Vouet

Z impedance of the
transistor yw
The point at which
is denoted
YYI.fi
4317
inv 2
varied
of 2pu 2pa ratio of the inverter
are

the transfer curves shift either up en down

thwngy.nu
of 2puzpd is decreased curves shift up
of 2pmEpd is increased curves shift down

The ideal characteristics inverter area

Vonth
of an
llogic when Vin _0 Vouet UDD
output
Fir
iii
THE Vin
 Determination of pull up to pull down ratio
2pu zpd for investor driven another
an
by
inverter VDD
o

Do Vin Do
ss
Hout trout
Gmosinvester Gmos inverters
Ving
Let us consider an investor driven by
the output of another invester Inverters
The conditions to implement the
primary
above design are

Vgs _o fer depletion mode MOSFET in the inverter

Vin Yone Vin so that the voltage levels are
not degraded
Yout
set

I
Vinu O 5 Vpp is for equal
margins
At Vim both depletion mode
and enhancement mode transistors voltage transfer
characteristics
in the inverter are in saturation
The current equation of a MOSFET in saturation
is
Ids K
wz K
wz fmG L

for depletion Mosfet K 5 since Vgs _0

Ids hippy
 For enhancement MOSFET
Ids _K Wpd
Y tT Vim is input
Z voltage E Investor
i
Ugs Viner

since bolts transistors are in saturation

Equating and

ei I
ya5
YT.hn XwIpnu
substitute 2 Values in Utdthreshold voltage ofdepletion
Zpu MOSFET
2pd Lpd
Wpu Wpd VE Threshold voltage of
1 Vinr Vt
2 enhancement MOSFET
C Ved
Zpd Wpa width g deep MOSFET

Vt 1 Uta
inv Lpn lengthof deep MOSFET
d Wpd width of enh MOSFET
v Vt D length g en h MOSFET

Fated
substitute typical Values in Eqn Ve O 2Vpp

Ved O 6 VDD

0.5W I 0 2 Vpp t O D Vine 0.5 VDD

Fasd
2pu 4
zpd
 to down ratio
Determination of pull up pull
for an investor driven through one or more

pan transistors UDD UDD Vpp VDD

Invested
f L I I Invester2
A
Vin f.yoB mrtf.ve 7Tlout2
pan transistors

suppose Vin OV The Voltage at Point B is Vpp

when Vpp is parsed through a series of
Pan transistors the voltage at point c is

DD Utp
The voltage is Vpp Vfp only irrespective of the
number transistors in the series chain
of
Vince Vpp Utp Vip threshold voltage
of Pan transistor
This concept applies when Vin _OU also
consider inverter 1 with input Up
Investerl Inverter 2

pointing
HDD
f
Ti
b
T
Depletion mode 1811 YEE
mode
181,2
MOSFET 1 IN
Enhancement
Mifune Inn enfjfee.tl 4oue a
mode MOSFET.ly ly
input_UDD input_Vpp Wep
 to Inverter 1 is Vpp the enhancement
of input
mode transistor Tz in the pull down network will
conduct in resistive linear regions
Hence it is represented as R
The transistor T will be in saturation region
and is represented as constant current Source
linear region
operating in
transistor MOSFET
For pull down p lineer region
Ids K WPI current
Npp Vt Vds tlds eyetion
Lpdi f
R Vds neglected
T dsl Vds is smell in linear region and
can be ignored

iY I ie
soZpdl
operated in saturation
region
For pull up transistor depletion mode transistor Vgs 0

I Ids K Wpa Ved

2
MOSFET saturates
current equation
put 2
1
I R _Hout 2pm
IR substitute
out
duo
2
Now consider Inverter 2
input VOD Vtp
using the same above concept 49 similar

REIT 2PM
u.pe py.ve IF
w
E k
Itai II
Youtz Iz R2
t
I lu
investerz have the
is to same output
If
Voltage under these conditions then
Vonly V'out 2
I R 12122

dueI z
IluIF.rIYIZpu2
E.ie
Zpd2
Zpu1 VDD Vt
Vpp Utp Vt
2pm

Substituting typical Values If _O LUDD Vtp 0.3Upp

 Zpn2 Zpu I O 2 VDD
47dL Zpd I 0.3 O 2 VDD

0.8 4
Epuz 2pm thi
from previous
O 5
Zpd2 Tpdl
a o

d2 inverter
2 4 0 0 8 1 assumption
X
summery Hi
1 An inverter driven directly from the output
of another inverter should have a zpulzpd
ratio of 34 1
2 An inverter driven through one or more

pass transistors should have ZpYzpd ratio

of 341
 Different types of loads in a naos inverter

Resistive Load inverter

Operation
load device
Rtg Hout Vos
Vin is less
than the threshold
the driver
driver device Voltage of
Vin transistor nmosFET
71
it is in cut off region
and doesn't conduct
since Voltage drop Vpn across Resistor is negligible
out DD
when Vin is above threshold driver transistor
operates in saturation region and Hout O
output voltageCvl
Vo Out put high
OH
µ Voltage
VOL _out put
low

i
u
Few
Vert input High
Voie I voltage
7
IH
onput Voltage GD
IL

arch
Disadvantaged Resistors occupies more

and difficult to fabricate

2 tn
VSnm r

D
DD I 7 Enhancement load
mode
device
MOSFET as

ftp.r.ae
Enhancement mode
inf Cy MOSFET as driver device
1
AND

Requires single
supply voltage and
simple fabricelies
Process

Voy VDD VEI

Transistor
always operate
in linear region
Voltage transfer characteristics
1 Linear Load Resistive load inverter has better
noise than Enhancement Lord
inverter
margin
2 Power dissipation is
high when Vin l
3
trout can never reach Upp due to threshold
voltage drop in
4 Vaa need not be Vpp always to reduce power
it can be connected to a clock
5 The output never reaches zero

vmr
Dy ni

UDD

TK dfw.TW
My out

zhg.IE
vin
lfz
1
ND

Power dissipation is high because when Vin _I

ON and there is a direct
both transistors are

and AND as both transistors

path between Upp
are conducting
transistor is mor
2 when Vin of the enhancement
than threshold voltage then switching of output
Vf
from 1 to 0 begins as Tz starts conducting
 Voltage transfer characteristics
3 The output is never zero when Vin is high fer
Tz resulting in n pE This is because
the out put vow is always getting charged
though it is being discharged through when
T will be initially in non satured stale
Vin l

and acts like a resistor

 Cmos
complementary transistor pull up
Cmos

Upp A p MOS transistor is

used in section
Ljhmvin O pull up
when Vin O p MOS
µqvout
Vin transistor
is off
is on and pros

f
when
Vin I to UDD
Uout is charged
AND hence Vout I
when Vin 4 n Mos is ON
and pros is off Vout is discharged
MoS and trout through
L

Transfer characteristics of Cmos inverter

 There is static DC path as
no
path
n MoS and pros are
Not at the same
time
Full logic 1 and O are presented at the

output
slower
For devices
of same size Pros
is

than naos
on the three regions
of operation both
transistors are on for small period of signal
transition and
power is consumed only
for that duration
The current Equations for a 905 inverter are

Ci Resistive region
Ids K
wz Vgs VE Vds VdsYz
ii saturation region
K K E
Ids E Cgt D
oµ
K is technology dependent parameter
Let us write
K
f wz
the above with
replacing ef's f
Ids f Ngs 4 Yes VdsYz
Ids 4
p 22
In saturation be applied to NMOS and PMOS
B may
transistors as

Cins
Effin WI Wn Wp are widths
pn
Lp Ln are lengths
Cins.C WI
pp o.MN D thickness of oxide
D Lp
CMOS inverter has 5 regions of operation
Region
Vin 0
transistor is
pros
turned ON
fully
while mthos is

fully turned OFF

There is no

current flowing
in the inverter A good logic l is present
at output

Region 5
transistor is ON while
Vin I NMOS
fully
p transistor is
fully OFF No current
0
flows and good bogie appears at the

output
Region
n Mos transistor
As input voltage has increased above Vf
NMOS conducts in saturation region due to
large Vds
P Mos transistor
pmos also conducts but
only Small voltage of
Vds St is in resistive region Cor non saturated
region
A small current flows from Vpp to Uss
Region
P Nos transistor
As input voltage has increased above Vt
P MOS conducts in saturation region due to
large Vds
N Mos transistor
nmos also conducts but
only small voltage of
Vds St is in resistive region Cor non saturated
region
A small current flows from Vpp to Vss

Regions
Both NMOS and PROS are in saturation
and exhibits gain
 Idsp Idsn Both transistors are

Series

Idsp Bad Xin Upp Hp

Idsn Vin Vtn

r
both as current is same
Equating Egas
in both devices

Vin UDD http 1 Vtn Bf

pp Y2

Both transistors are in saturation Region 3

is highly unstable and change over from one

logic to another is rapid quick

and
G for pp Utn Vtp

µin
change over between logic lysis Symmetrically
disposed about the point at which
Vin V'out OJUDD
 since
fn Bp
pak wz
C k Eins
M E
Ig
Wynn

F T
m En re
h
Mfp n Say Ln 4s

2 5 WI
Wn
25W
wp
 Powerdini pation
There two types of power dissipation
are
1 Dynamic power dissipation
2 Static power dissipation
Dynamic power dissipation
The power dissipated by Logie gate during transition is
vDD called dynamic power
dissipation
of
t

Viq y q ad capacitance

when the
q voltages switches from Low to
input
NMOS
high PMos transistor is cut off and
transistor starts conducting
Thus the discharge current of the capacitor is
b instantaneous drain current of NMOS
qul
transistor

when the input voltages switches from high to

low NMOS transistor is cut off and PMos
transistor starts conducting
Thus the charging current
of the capacitor is
egrel b instantaneous drain current of pros
transistor
average power dissipatedby any device over one period

is

calculated Pang Jotuetsittsdt

1
During switching
the NMOS transistor and pros transistor
in a 6 905 inverter conducts current

for each
one
half cycle
The average power dissipation cows
of
inverter is calculated as power required
to change up and charge down the load
capacitance

Woo Yuet kid

w dt
Paige'T You Ed doe dt
gL d
d
q charging
discharging haycycle
intros on
PMOS on
T

40 D Vout G fallout
Pang
fCG 2

since f
G VDD
Pong
If
Pang I
G Voight
 conclusion
1 The is
average dynamic power dissipation
proportional to switching frequency f or speeds

For more speed more power consumption

2 Average power dissipation is not dependent
on transistor sizes and characteristics because
it is only dependent on charging and
discharging of output capacitance

Static on

The powerdissipated when logic lends are

stable is called static power dissipation
static power dissipation is due to leakage
currents

Pstat I VDD
leakage

Iledge leakage current

The leakage current gatos inverter is
Zero in ideel case since Paros and naos
never switch 0N simultaneously in
steady state
of
operation
But due to leakage current at reverse
biased source and drain junctions
static power is dissipated It is very Small
 ctos Scaling
Scaling models and parameters

Need for scaling

Tosin advantage compared to BJC
Then the size of the MOSFET is reduced
the performance increases
By scaling down more number of transistors
can be packed on the chip with improved
performance supporting Moore's Cow

Scaling Models
1 constant electric field scaling model
2 constant voltage scaling model
3 constant electric field and Voltafe Seeling model

The two Yd and Yp

scaling factors are

Yp is scaling factor for supply voltage Hop

gate oxide thickness D
Ya is scaling facts for all other physical
dimensions
 Seeling factors ter device parameters

I Gate Area Ag
Ag L W L length g channel
wa width of Channel

Ag L w
Iz Ag Lz
i Ag is Sealed by Yar

2 Crete Capacitance Per unit area 6 Con Cox

be
Eon is constant cannotSeeled
G Eon
D D is sealed by YB
G Eon G
P p.co
Typ
I Co is sealed by p times

3 Crete capacitance

Cgz G W L

G pto wy.ly

zia.T
csi
4 Parasitic capacitance Cn

Ge is proportional G AI
d

d is depletion width around Source

and drain scaled by Ya

An is depletion region
ane
g
around source and drain and
scaled by 422
Cn L
YI Cn
Ya
Ca Tf
in channel Qa
5 carrier density
Go Co
Ngs

Qom is average charge per unit area

in channel in ON stale
Vgs is sealed by Yp
co is sealed by p

Qon Own
Eight
QuJ
No change Qon
6 Channel Resistance Ro
Ron
_I 9 constant
is
µ
Qon doesn't change
w L is sated by Ya

Ron
YI wa r
RonJ
Ront No change

7 Gate delay Td
Td is proportional to RonIg
Ron doesnt change
Cg is sealed by Blair

Tai Ron GI
22

fi T
f
8 Maximum operating frequency fo
fo
wz.MG.VDDG.to
YITx
Yy
li
dpIfoP
xg
9 Saturation current Ids
Ids ten Iz Ngs 4 12
G
wz

Ias in cos
41,2 I ftp.y rgs h

to current density
T
p.Ias IIasJ

J Ta
A

g IASI 8
2 wz

g2gT
j

11 Switching Energy per gate Eg

Eg LzCg VDD

Eg's t.CL Cg ftp.JDE

Eg
ETf
Lz
12 Power dissipation Pcr gate Pg
Pg Pgs 1 Pgd
Pgs Static component

Pgd dynamic component

Pgs Viggo
YI fz
Pgd Eg to
 Noise Margin
static characteristics
Noise Margin NM is the amount of noise that
a ciaos circuit could withstand without compromising
the operation of the circuit
Noise margin does make sure that any
signal which is logic l with finite noise
added to it is still recognized as 1 and
not as logic o It is basically the difference
between signal value and noise value
Hence Noise Margin is the measure
of the
sensitivity of the logic gate to noise and
expressed as NML Noise margin Low and
NMH noise margin High
NML VIL VOL
NM VOA VI H
consider the Voltage transfer characteristics of
a emos investor
Vo Thin output Voltage
at which output logictrig

Vol tax output voltage

atwhich output is Low
UIL_Max input voltage at which
input is Low
IH Thin input voltage at
which input is High
 Any Value between VI and You is recognised
as I
logic
Any Value between You and VIL is recognized
0
as logic

the noise
By designing
the noise
margins carefully
immunity is fixed

17 IT PotEtDo
d
OH
IH

min allowable
maximum
allowable Voltage
Voltage

Noise Margins should be designed as

small as possible
Assume that all inverters are identical and the

input voltage of first inverter is equal to

Voy i e logic 1 from previous stage
The output voltage should be logic
of Inverter
I o

which is you Max voltage at which output D

it will not be
Beyond that recognized as o

Due to noise on interconnects wins the

Voltage to second inverter is
VII min voltage
at which input is d else it will not be
recognized as 0
Now the output of second inverter is Voit
min output voltage when output is 1 else 9
will not be
recognized as I
Again of noise is added by interconnects
input to third investor is VI min input voltage
when input is high else it will not be
recognized as I
The output of third investor is Vol Imax output
Voltage when output is low else it will
not be recognized as O
 E up
Latch up is an unwanted abnormal condition
that prevails in ciaos circuits due to parasitic
elements within the structure
Due to large number of junctions within
the CMOS structure parasitic transistors and
diode's form a parasitic Scr silicon controlled
rectifier and unwanted current shoots up
so that device doesn't function in an expected

way
Definition
Latch up is a condition in which the parasitic
components give rise to establishment of low resistan
conducting path between Mpp and Uss

Latch up might be induced becauseof glitches on

the power supply Crisis as GND or due to incident
radiation 4in
Kss
t
Tl if II

F fine
Rs Rp
c
are

Partisans
Red lines Parasitic SCR
 VDD

Dis Ha
L k
in
Tz
To Ks

Iv Ss Latch
up
circuit model

There are parasitic ttansiston Te 14 and two

2

resistances Rg Kp associated with p well and

Kubstrati regions which form a path between
Vpp and Vss AND
Mechanism
substrate current flows to generate
of sufficient
enough voltage across Rs it turns on Tc
Then transistor turns on due to current
drawn through Rp output current g T and
sufficient voltage of VBE of Tz
A self sustaining low resistance path is
established beltran Vpp and Us
 current gains two transistors
of the
are
of
that
such
fixfz 1 catch up occurs

Latch upcurrent
current
M of substrate
doesn't existance
resistance is high and

µ
Leth up doesn't form
gazing q
I to low resistance

p Voltage

once the latch up is formed until the current

falls below Ii the situation prevails

V and I should not be reached in cows

Remedies Solutions to avoid Latch up

I Increase substrate cards with a
doping
consequent drop in value
of Rs
2 Reducing Rp by controlling fabrication
parameters and ensuring low contact resistance
to Vss
3 Gerund rings
 P oau.tn 90SFET

youre ydmin.la

a L Cs

V
SB
Inf il r i

YET
i

t.tt I substrate

Due to the physical structure of MOSFET and

number
of junctions many parasitic capacitors
the switching delay
appear that effects of
the device
Cac _gate to channel capacitance
to Source capacitance
case gate
cap gate to drain capacitance
Css source to substrate capacitance
Cps drain to substrate capacitance
channel to substrate capacitance

These capacitance are desired to be as small

as Possible
 Dynamic characteristics of CMOS invester

Iropegation deley
The propagation delay of a logic gale is the
difference in time calculated d 50 f
of input
output transit on when output switches
VDD

DO
Panos

y jo.ws infinity ok
NMlus

Xi I
l l
l l l
l
1 I rise time
ItpHL
t l t
Il l
I tf fall time
tp
tp propagation
tf i
I
i
tr deley high to low
C
put a propagation dely
Low to High

Average propagation delay ftp.j tp c tpLH

2
 to tph
Ioopagationdeley high

During early phase of discharge

N Hos is saturated PMos is cut.gg

fft
win
High E G load capacitance
Low High

IIont
LIE oUin
ifeng.in
o
Ifm VinYo
iiin
E Vin
hop

at t O at tot at E to
NMosi sin
saturation
PMOS is cut off

tpHL charge once tao

NMOS discharge current

F 051
Nowt
Volt

tpHL t
 Propagation deley Low to high

During early phases of charging 9 Pros is

Schirated and NMOS is cut off
VDD

vin
Efficient
Vss

I'E CE
ou
i
Vin VDD

at t o at tot
VDD

Vo E Upp
Xin 0

Vss
Fa
at t infinity

G t D
tpHL Iz charge an

PMOS charge current

RISE TIME and FALL Time