CO-1 MOSFET

23EC2211 – VLSI DESIGN

2 MOSFET Device Introduction
 MOSFETs
3

 We now turn our attention to another type of transistor, the

MOSFET:
🞑 Metal Oxide Semiconductor Field Effect Transistor
 Many similarities to the BJT:
🞑 Three terminals
🞑 Voltage at one terminal controls current between the other two
 A transconductance device
🞑 Two polarities: N-channel and P-channel MOSFETS
 Our focus will primarily be N-channel MOSFETs (NMOS devices)

N-Channel P-Channel
(NMOS): (PMOS):
 MOSFETs
4

 MOSFETs are actually four-terminal devices

🞑 Fourth terminal is the body, substrate, or bulk
 The body is often tied to the source, and we can mostly
ignore it
🞑 Discrete devices
 Other times we must account for the body potential effect
on device behavior
🞑 Often the case in integrated circuits

NMOS: PMOS:
 Physical Structure - NMOS
5

Sedra/
Smith

 P-type substrate
 N+ source and drain
 Metal gate electrode, and source/drain/body contacts
 Thin oxide insulates the gate from the rest of the device
 Region of substrate between the drain and source is the channel
🞑 Channel dimensions: W and L
🞑 We’ll see later why this is called an n-channel (NMOS) device
 Terminal Voltages and Currents
6

 Terminal voltages and currents named

Again, lower-case 𝑣/𝑖 and upper-case

as shown
🞑
subscript represents total (AC and DC)
voltage and current
 For an NMOS device in typical

𝑣𝐺𝑆 ≥ 0
operation:

𝑣𝐷𝑆 ≥ 0
 Gate oxide does not allow current to
flow, so
𝑖𝐺 = 0
and
𝑖𝐷 = 𝑖𝑆
 MOSFET Operating Regions
7

 Three MOSFET operating regions:

🞑 Cut-off
🞑 Triode
🞑 Saturation

 A MOSFET’s operating region is determined by its

terminal voltages

regions, along with their 𝑖 − 𝑣 characteristics

 Next, we will look in detail at each of these three
8 Cut-Off Region
 Cut-Off Region
9

 Gate and source both

grounded
𝑣𝐺𝑆 = 0
 Drain-to-source pathway looks
like two back-to-back diodes

resistance (𝑟𝐷𝑆 = ∞)
🞑 Very high drain-source

 Even for 𝑣𝐷𝑆 > 0, no

current will flow
𝑖𝐷 = 0
 Looks like an open switch
🞑 Similar to BJT cut-off
operation
10 Triode Region
 Triode Region – Inversion
11

 Now, 𝑣𝐺𝑆 is increased, while 𝑣𝐷𝑆 is kept small

🞑 Electric field established across gate oxide
🞑 Holes in p-type substrate repelled deeper into substrate
Electrons from drain and source attracted to region below the gate
For large enough 𝑣𝐺𝑆, p-type material below the gate is inverted to n-
🞑

type
🞑 An inversion layer

Now, current can flow in response to 𝑣𝐷𝑆, 𝑖𝐷 > 0

🞑 Induced n-type channel connects drain to source
🞑
 Threshold Voltage
12

 Channel is induced once 𝑣𝐺𝑆 exceeds a certain voltage:

The threshold voltage
𝑣𝐺𝑆 ≥ 𝑉𝑡
🞑

Typically, 𝑉𝑡 = 300 𝑚𝑉 … 1 𝑉
🞑 A device parameter

As 𝑣𝐺𝑆 increases beyond 𝑉𝑡, the induced channel gets

🞑

As long as 𝑣𝐷𝑆 is small (𝑣𝐷𝑆 ≪ 𝑉𝑡), channel depth is

deeper

 Overdrive Voltage
13

A channel is induced once 𝑣𝐺𝑆 exceeds the threshold voltage

𝑣𝐺𝑆 in excess of the threshold voltage is called the overdrive



voltage
𝑣𝑂𝑉 = 𝑣𝐺𝑆 −
or effective voltage:
𝑉𝑡
 As we will soon see, 𝑣𝑂𝑉 plays an important role in
determining device behavior
 Triode Region
14

 As 𝑣𝐷𝑆 increases:

𝑣𝑆 near the source, 𝑣𝐷 near the drain

🞑 Voltage varies along the channel


🞑 Gate-to-channel voltage decreases closer to the drain

🞑 Channel depth decreases closer to the drain

More current flows with increasing 𝑣𝐷𝑆, but channel

 Channel is tapered


resistance increases as channel becomes more tapered

 Triode Region - 𝑖-𝑣 Relationship
15

 Drain current in the triode region:

−1
𝑖𝐷 = 𝑣𝐺𝑆 2
�
𝑣𝐷𝑆 𝑣𝐷
𝜇𝑛𝐶𝑜𝑥 𝐿 − 𝑉𝑡
�
𝑆
𝑊 1
𝑖𝐷 = 𝜇𝑛𝐶𝑜𝑥 𝑣𝑂𝑉 − 𝑣
2 𝐷𝑆
𝐿
where: 𝑣𝐷𝑆
𝜇 𝑛 : electron mobility
𝐶𝑜𝑥: oxide capacitance


𝑊: channel width


𝐿: channel length



1
We can also express the drain current as
1


𝑖𝐷 = 𝑣𝑂𝑉 − 𝑣 𝑣𝐷𝑆 = 𝑘𝑛 � − 2
2 𝑣𝑂𝑉𝑣𝐷 2
� �
𝐷
𝑘 𝑛′ 𝑣
′
𝐷𝑆 𝑆
𝐿 𝐿
�
𝑆
where:
𝑘𝑛′ = 𝑛
𝜇 𝐶
 is the process transconductance parameter
𝑜𝑥
 Triode Region - 𝑖-𝑣 Relationship
16

Triode region:
>


𝑣𝐺
𝑉𝑡
𝑣𝐷𝑆
𝑆 < 𝑣
𝑂𝑉

For 𝑣𝐷𝑆 ≪
𝑣𝑜𝑣


1
🞑 Nearly a

𝑟𝐷𝑆
linear

= 𝑘′
resistance
🞑 Resistance 𝑊𝑛
𝐿
linearly
𝑣𝑂𝑉
As 𝑣 𝑣𝑂𝑉
proportional to
𝐷𝑆 increases


🞑 𝑟𝐷𝑆 increases
🞑 Channel taper increases

🞑 𝑖 𝐷 -𝑣𝐷𝑆 slope
decreases
17 Saturation Region
 Device Operation – Channel Pinch-Off
18

 Eventually, for large enough 𝑣𝐷𝑆

𝑉𝑡
🞑 Gate-to-channel voltage near the drain no longer exceeds

🞑 Channel pinch-off occurs

🞑 Channel disappears at the edge of the drain
 Pinch-off occurs when:
𝑣𝐺𝐷 = 𝑉𝑡 = 𝑣𝐺𝑆 − 𝑣𝐷𝑆
𝑣𝐷𝑆
𝑣 𝐷𝑆 =
= 𝑣𝐺𝑆 − 𝑉𝑡
 Saturation Region
19

 Once channel pinch-off

occurs:
🞑 Voltage at the drain-end

remains 𝑣𝑂𝑉, even as 𝑣𝐷𝑆

of the channel

Any increase in 𝑣𝐷𝑆 beyond

increases

𝑣𝑂𝑉 is dropped across the

🞑

depletion region surrounding

the drain

channel is fixed at 𝑣𝑂𝑉

🞑 Voltage across the length of the

does not change with 𝑣𝐷𝑆

🞑 Pinched-off channel shape
 Saturation - 𝑖-𝑣 Relationship
20

 Drain current in the saturation region still given by

𝑊
𝑖𝐷 = 𝑘 𝑛 1 𝑣𝑂𝑉𝑣 − 2
𝐿
′
𝐷
𝑣 2
𝐷𝑆 𝑆

the channel is 𝑣𝑂𝑉

 But now, the voltage from the drain-end to source-end of

 Replacing 𝑣𝐷𝑆 with 𝑣𝑂𝑉, the drain current

relationship becomes
1 𝑊
𝑖� = 2 = 𝑣𝐺𝑆
′ ′ 2
2 1 𝑣𝑂
�
� �
𝑘� 𝑉 𝑘
− 𝑉𝑡
𝐿 𝐿
� �
�

2𝑣𝐺𝑆 (or
𝑣𝑂𝑉)
🞑 Purely a function of

🞑 Independent of 𝑣𝐷𝑆
 Input I-V Characteristic
21

 In saturation, drain current

on 𝑣𝐺𝑆 (𝑣𝑂𝑉)
has a quadratic dependence

1
𝑖𝐷 = 𝑊 𝑣𝐺𝑆 2
�
� − 𝑉𝑡
′
𝑘𝑛
2 1 2
𝑖𝐷 =′ 𝑊
𝑘
2 𝑛�
𝑂
𝑉
𝑣 �
 Output I-V Characteristic
22
 NMOS Operating Regions – Summary
23

 Cutoff:
𝑣𝐺𝑆
< 𝑉𝑡
🞑

𝑖𝐷
=0
🞑

>
𝑣𝐺
Triode:𝑉𝑡
>
🞑

🞑 𝑆


𝑣𝐷𝑆 < 𝑣𝐺
𝑉𝑡
or

𝑖𝐷𝑂𝑉
= � 𝐷� = 𝑘𝑛 𝑣
1 2 1 2
𝑣 𝑛 − −
�

𝜇 𝐶 �𝑂𝑉�𝐷𝑆 2 ′ 𝑊 𝑣𝑂𝑉 𝐷𝑆
🞑
2
�
𝑜𝑥 𝐿 𝐿
 Saturation: 𝑣𝐷𝑆 𝑣𝐷𝑆

🞑
𝑣𝐺
> 𝑉𝑡
𝑆 > 𝑣𝑂𝑉 or 𝑣𝐺𝐷
<1 𝑉𝑡 = 1 𝑘𝑛
🞑
2
𝑣𝑖𝐷 = 2
𝐷 2𝑊 𝑣𝐺𝑆 − 𝑣𝑂𝑉
′ 𝑊
𝑘𝑛
′
🞑
𝑆 2 𝐿
𝐿 𝑉𝑡𝑝
24 P-Channel MOSFETs
 P-Channel MOSFETs
25

 Voltage polarities and doping types reversed relative to NMOS

🞑 N-type substrate

Negative threshold voltage: 𝑉𝑡𝑝 < 0

🞑 P+ drain and source

Negative overdrive voltage: 𝑣𝑂𝑉 = 𝑣𝐺𝑆 − 𝑉𝑡𝑝 < 0

🞑

Channel induced for 𝑣𝐺𝑆 ≤ 𝑉𝑡𝑝

🞑

🞑
🞑 Substrate connected to source or most positive circuit voltage
 PMOS – Operating Regions
26

 Cutoff:
>
𝑣𝐺
𝑉𝑡𝑝
🞑

𝑆 𝑖𝐷 =
0
🞑

>
𝑣𝐺𝑆 𝑉𝑡
 Triode:
𝑣
>𝐺𝑆 <𝑝
𝑣𝐷 𝑣𝑂
< 𝑉𝑡𝑝,𝑣𝑂𝑉, 𝑣
🞑
🞑

� 𝐷
🞑 𝑖𝐷 = 𝑝 � 𝑆𝑣𝑂 = 𝑘𝑝 𝑣𝑂
𝑆 𝑉 1 2 1 2
− −
𝜇 𝐶𝑜𝑥 𝐿 𝑣𝑉 𝐷𝑆 2 ′ 𝑊
𝐿
𝑣𝑉 𝐷𝑆 2
 Saturation: 𝑣𝐷𝑆 𝑣𝐷𝑆

𝑣𝐺𝑆 < 𝑣 > 𝑉

𝐺𝑆 𝑡
𝑉𝑡𝑝, >𝑝
🞑

𝑣𝑂
𝑣𝐷
𝑣1𝐷𝑆 < 𝑉
2
= 1 𝑘𝑝 2
𝑣𝑂𝑉, ′ 𝑊 𝑣𝑆
𝐺𝑆 − 𝑣𝑂𝑉
′ 𝑊
🞑

2 𝐿
𝑉𝑡𝑝
🞑 𝑖𝐷 = 2
 CMOS
27

 Complementary MOS or CMOS

🞑 Both NMOS and PMOS fabricated on the same chip
 P-type substrate
 PMOS devices fabricated in n wells
 Most modern MOS chips are fabricated using CMOS technology
28 Large-Signal MOSFET Model
 DC Operating Point – Example 1
Determine 𝐼𝐷 and 𝑉𝐷
31

 𝑐𝑚2
𝜇𝑛 = 500
𝑉
for the following circuit ⋅𝑠
𝑓𝐹
𝐶𝑜𝑥 =
Is the device operating in 3.8
𝜇𝑚2
🞑
the saturation region?
𝑉𝑡 =
500 𝑚𝑉

The process 𝐿 = 0.5

𝑊
𝜇𝑚= 50


transconductance 𝜇𝑚
parameter:
3.8 × 𝜇
−4𝑚 =
𝑘𝑛′ = 𝜇𝑛 𝐶 = 500 × 10 𝑉 ⋅ 𝑠⋅ 10
2
1 −15 𝐹
× 𝐴
𝑜𝑥 190 𝑉
10−12 𝑚2 2
 DC Operating Point – Example 1
32

 Drain current in saturation:

1
𝐼� = 𝑉𝐺𝑆
′ 2
2
�
𝑛
𝑘� − 𝑉𝑡
𝐿
�
1 50
𝜇𝑚 800 𝑚𝑉 − 2
�
2
𝜇𝐴 0.5
𝑉 500 𝑚𝑉
𝐼 = ⋅ 1902 𝜇𝑚
�

⋅ 𝐷 = 855
𝐼
𝜇𝐴

𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷
 Voltage at the drain:

𝑉𝐷 = 3.3 𝑉 − 855 𝜇𝐴 ⋅
1.8 𝑘Ω
𝑉𝐷 =
1.76 𝑉
 The device is operating in the saturation region
🞑 The drain-to-source voltage exceeds the overdrive
voltage
𝑉𝐷𝑆 = 𝑉𝐷 = 1.76 𝑉 > 𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡
 DC Operating Point – Example 2
33

𝑉𝐺𝑆 for 𝑉𝐷 = 1 𝑉
 For the same circuit, determine
𝑐𝑚2
𝜇𝑛 = 500
𝑉
Is the device still operating in the ⋅𝑠
𝑓𝐹
🞑

𝐶𝑜𝑥 =
saturation region?
3.8
For 𝑉𝐷 = 1
𝜇𝑚2
𝑉𝑡 =
𝑉 𝑉𝐷𝐷 − 𝑉𝐷


3.3 𝑉 500 𝑚𝑉
�� 𝐿=
�=
−1𝑉 =
0.5 𝜇𝑚
𝑅 1.8 𝑘Ω 𝑊 = 50
𝜇𝑚
�
𝐷

𝐼𝐷 = 2.3 𝑉 = 1.28
1.8 𝑘Ω
 𝑚𝐴 saturation-region operation
Assuming
1 𝑊 2 1 𝜇𝐴 50
𝐼� = 𝑉 = ⋅ ⋅ ⋅ 𝑉2𝑂𝑉 =
′
2 𝜇𝑚 𝑂
𝑛 2
𝑘� 190
𝑉 1.28 𝑚𝐴
𝐿 2 𝑉 0.5
𝜇𝑚
Solving for the overdrive voltage


𝑉𝑂𝑉 = 367 𝑚𝑉
 DC Operating Point – Example 2
34

 The required gate-to-source voltage is

𝑉𝐺𝑆 = 𝑉𝑡 + 𝑉𝑂𝑉

𝑉𝐺𝑆 = 500 𝑚𝑉 + 367 𝑚𝑉

𝑉𝐺𝑆 =
867 𝑚𝑉
 The drain-to-source voltage exceeds
the overdrive voltage
🞑 The transistor is operating in the
saturation region

𝑉𝐷𝑆 = 1𝑉 > 𝑉𝑂𝑉 = 367 𝑚𝑉

 DC Operating Point – Example 3
Find 𝑅𝐷 and 𝑅𝑆 for
35

𝜇


𝐴
𝐼𝐷 = 200 𝜇𝐴 and 𝑉𝐷 = 𝑘𝑛′
= 400 𝑉 2
200 𝑚𝑉 𝑉𝑡 =
500 𝑚𝑉
𝑅𝐷− 𝑉𝐷
𝑉𝐷𝐷 1𝑉−
��
First, determine 𝐿 = 0.5
𝑊
𝜇𝑚= 15


200 𝑚𝑉 =
�� = 𝐼 200 𝜇𝐴
𝜇𝑚

𝑅𝐷 = 4 𝑘Ω
𝐷

 Drain current in saturation is given by

1 2𝐼𝐷
𝐼� = � 𝑉𝑂𝑉 →
′ � 2
2 𝑛
𝐿
𝑘� 𝑘𝑛′ �
𝐿 𝑉𝑂𝑉 = �
2 ⋅ 200 𝜇𝐴 0.5𝜇𝑚
𝑉𝑂𝑉
= 182.6
= 400 𝜇𝐴/𝑉2 15 𝜇𝑚
𝑚𝑉
 DC Operating Point – Example 3
36

 The gate-to-source voltage is

𝑉𝐺𝑆 = 𝑉𝑡 + 𝑉𝑂𝑉 = 500 𝑚𝑉 +
182.6 𝑚𝑉
𝑉𝐺𝑆 = 683 𝑚𝑉
 The gate is grounded, so the source
voltage is
𝑉𝑆 = 𝑉𝐺 − 𝑉𝐺𝑆 = −683 𝑚𝑉

𝑉𝑆 resistance
− 𝑉𝑆𝑆 −683 𝑚𝑉by−
��
The source is given
−1 𝑉


��= 𝐼
=
200 𝜇𝐴
𝐷
𝑅𝑆 = 1.59
𝑘Ω
 DC Operating Point – Example 4
Find 𝐼𝐷 and 𝑅𝐷 for 𝑉𝐷 = 100
37

𝑚
𝑚𝑉


� = 𝐴2
�
𝑘𝑛′
2 𝑉
𝐿
𝑉𝑡 =
resistance, 𝑟𝐷𝑆? 500 𝑚𝑉
🞑 What is the drain-to-source

 The device is in the triode

region:
𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡 = 2 𝑉

− 500
Drain 𝑚𝑉in
current =triode
1.5 𝑉 is given by
𝑉𝐷𝑆 = 100 𝑚𝑉 < 𝑉𝑊
𝐼𝐷 = 1
𝑂𝑉
𝑉𝑂𝑉− 𝑉𝐷𝑆
𝑘 𝑛′ 𝑉𝐷𝑆
𝐿
𝐼𝐷 = 2𝑚𝐴
22 1.5 𝑉 − 50 𝑚𝑉
𝑉
100 𝑚𝑉

𝐼𝐷 = 290
𝜇𝐴
 DC Operating Point – Example 4
38

 The required drain resistance:

𝑉𝐷𝐷 − 𝑉𝐷 1.9
��
𝑉
�� = 𝐼
=
290
𝑅𝐷𝜇𝐴= 6.55
𝐷 𝑘Ω

 The drain-to-source resistance in the triode

region is given by:
1
𝑟𝐷𝑆
= 𝑘′𝑛
𝑊𝐿

𝑟𝐷𝑆 𝑚𝑉
= 2𝐴 1.5
𝑂
𝑉 2

𝑉 𝑉1
𝑟𝐷𝑆 = 333 Ω
 DC Operating Point – Example 5
Find 𝐼𝐷, 𝑉𝐺 , 𝑉𝐷, and 𝑉𝑆
39

for the following circuit

𝑊
𝑘𝑛′ � 𝑚𝐴
 The gate voltage is simply set by the
voltage divider = 1 𝑉2
10 𝑀Ω 𝑉𝑡 =
�
1𝑉
𝑉𝐺 = 10 𝑉
10 𝑀Ω + 10 𝑀Ω
𝑉𝐺 =
5𝑉
 Assuming operation in the saturation region, drain current is
1 𝑊
𝐼� = 𝑉 = 𝑉𝐺 − 𝐼𝐷𝑅𝑆
′ 2 ′ 2
2 1
�
𝑛 𝐺𝑆 𝑛
𝑘� −𝑡 𝑉 𝑘 − 𝑉𝑡
𝐿 𝐿
�
𝑚𝐴
𝐼� = 0.5 2 5 𝑉 −𝐷𝐼 𝑅 − 2
1�𝑉 𝑉 𝑆
2
 DC Operating Point – Example 5
𝑚𝐴
40

𝐼� = 0.5 4 𝑉 −�𝐼 ⋅
6�𝑘Ω 𝑉2

2
�

𝐼𝐷 𝐼 = 18𝐸3 𝐼2 − 24 𝐼 +
 This is a quadratic equation for
𝐷 𝐷
8𝐸 − 3
�
�
 Two possible solutions:
𝐼𝐷 = 889 𝜇𝐴 or 𝐼𝐷 = 500 𝜇𝐴
 For 𝐼𝐷 = 889 𝜇𝐴
𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷 = 10 𝑉 − 889 𝜇𝐴 ⋅ 6
𝑘Ω = 4.67 𝑉
𝑉𝑆 = 𝐼𝐷 ⋅ 𝑅𝑆 = 889 𝜇𝐴 ⋅ 6 𝑘Ω = 5.33 𝑉
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = −333 𝑚𝑉
 DC Operating Point – Example 5
For 𝐼𝐷 = 889 𝜇𝐴
41

🞑 𝑉𝐺𝑆 < 0
🞑 The transistor is in the cut-off region
 The valid solution to the quadratic equation
must be
𝐼𝐷 = 500
𝜇𝐴
 The drain and source voltages are
𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 10 𝑉 −
500 𝜇𝐴 ⋅ 6 𝑘Ω
𝑉𝐷 =
7𝑉
𝑉𝑆 = 𝐼𝐷 ⋅ 𝑅𝑆 = 500 𝜇𝐴
⋅ 6 𝑘Ω
𝑉𝑆 =
3𝑉
MOS CV Characteristics
MOS Capacitor

MOS Capacitor : An MOS

capacitor is a structure that
consists of a metal gate, a
semiconductor body, and an
insulating layer of silicon dioxide.
MOS Capacitor

• Capacitance and Voltage: The capacitance of an MOS capacitor

changes depending on the voltage applied to the gate, affecting
how charges are distributed within the device.

• Flat Band Voltage: This critical voltage level signifies no net

charge across the capacitor, establishing a baseline for measuring
other phenomena in the device.

• Threshold Voltage: This is the point at which the depletion layer

vanishes, and strong inversion begins, pivotal for the capacitor’s
operation within transistors.

• C-V Curve Analysis: The capacitance-voltage curve helps identify

the capacitor’s behavior in different charge accumulation states,
crucial for understanding and designing circuits with MOS
MOS CV Characteristics
Second order Effects
Definition
42 Channel-Length Modulation
 Channel-Length Modulation
43

current as independent of 𝑣𝐷𝑆

 So far, our MOSFET model in the saturation region models drain

1 ′ �
𝑖𝐷 =
2 � 𝑣𝑂 2
𝑘𝑛 𝑉
𝐿 region
In reality, current increases as 𝑣𝐷𝑆
🞑 Flat I-V characteristic in the saturation


increases

 Increase in 𝑖𝐷 due to channel-length modulation

 Channel-Length Modulation
44

 Justification for constant saturation current was:

Any additional 𝑣𝐷𝑆 is dropped across the depletion

🞑 Channel shape does not change after pinch-off occurs
🞑

But, as 𝑣𝐷𝑆 increases, the drain depletion region

region surrounding the drain


increases, and the channel length decreases

 Channel-Length Modulation
45

𝑖𝐷 ∝1
 Drain current is inversely proportional to channel length
𝐿

 So, as 𝑣𝐷𝑆 increases, 𝐿 decreases, and 𝑖𝐷 increases

🞑 Non-zero slope in the saturation region of the 𝑖𝐷 -𝑣𝐷𝑆
curve:
 Channel-Length Modulation
46

modulation parameter, 𝜆
 This effect is accounted for by the channel-length

1 ′
𝑖� = 𝑊 � 𝑣𝐺𝑆 − 𝑉2𝑡 1 + 𝐷
𝑘�
𝐿 𝜆𝑣
𝑆
2
🞑 𝜆 is inversely proportional to channel
�

𝐿
🞑 𝜆 related to the Early voltage: 𝜆
1
𝑉
=
length,
𝐴
 Output Resistance
Slope of the 𝑖𝐷 -𝑣𝐷𝑆 characteristic is the inverse of
47

the
transistor’s output resistance
🞑 Resistance seen looking into the drain
 Constant saturation current implies infinite output
resistance
 Output Resistance
48

 Output resistance given by

𝜕𝐷
−
𝑟� 𝑖 𝐷
1

=� 𝜕𝑣
🞑 The inverse of the slope of the𝑆𝑖𝐷 -𝑣𝐷𝑆 characteristic
 Channel-length modulation results in finite output resistance
 Output Resistance
49

 Model the finite output resistance due to channel-length modulation

by adding a resistor to our large-signal model

 Output resistance given by

𝜕𝑖 𝜕 1
− −
𝑟𝑜 = 𝑘𝑛′ 𝑊 𝑣𝐺 1+
𝐷 1 2 1
𝜕𝑣𝐷𝑆
𝑡 𝐷
= −𝑆𝑉 𝜆𝑣 𝑆
𝜕𝑣𝐷𝑆 2 𝐿
𝜆
−
𝑟𝑜 = 𝑊𝑘𝑛′ 𝑣𝐺𝑆 2 1
2
− 𝑉𝑡 𝐿
1
𝑟𝑜 = 𝑉� 𝐴′ =�
𝜆𝐼
� �

𝐼′
50 The Body Effect
 The Body Effect
51

 So far, we have largely ignored the connection to the

substrate
🞑 Equivalently, we have assumed it to be tied to the
source:
NMOS: PMOS:

 This a valid assumption for discrete devices

🞑 Not so for MOSFETs on integrated circuits (ICs)
 The Body Effect
52

 For integrated circuits, the substrate is typically tied

to the most negative supply voltage for NMOS
devices
🞑 PMOS n-wells tied to the most positive supply voltage
 Substrate for a given device may well be biased
below its source voltage (above for PMOS)

For 𝑉𝑆𝐵 > 0 (𝑉𝑆𝐵 < 0 for PMOS), the

🞑 This is the bias voltage for the channel region


threshold voltage is effectively increased

🞑 This is the body effect
Subthreshold Conduction (Leakage Current)
Subthreshold Conduction (Leakage Current)
Slope factor / Subthreshold Swing (S)
Drain Induced Barrier Lowering (DIBL)
Drain Induced Barrier Lowering (DIBL)

• If Drain voltage increases in the short channel device the depletion

region of the drain gets larger.
• When VDS​ increases, the electric field from the drain reduces the
potential barrier for electrons at the source-channel junction.
• This lowering of the barrier makes it easier for electrons to flow from
the source to the drain, even at lower VGS.

• As the VDS increases, the conduction band at the source-channel

interface is pulled down, reducing the gate's control over the channel
and effectively lowering the Vth.
Drain Induced Barrier Lowering (DIBL)

Key effects of DIBL

• Reduction in Threshold Voltage .

• Increase in Subthreshold Leakage.
• Degradation of Device Performance

DIBL is quantified as the change in threshold voltage (​) per unit change
in drain voltage (ΔVDS​).
Fabrication of CMOS integrated circuits - Process

• N-well regions are created for PMOS transistors, by

impurity implantation into the substrate.
• This is followed by the growth of a thick oxide in the
regions surround the NMOS and PMOS active
regions.
• The thin gate oxide is subsequently grown on the
surface through thermal oxidation.
• After this n+ and p+ regions (source, drain and
channel-stop implants) are created.
• The metallization step (creation of metal
interconnects) forms the final step in this process.

Simplified Process Sequence For Fabrication Of CMOS ICs

Fabrication Flow Basic Steps
Fabrication Flow Basic Steps
Fabrication Flow Basic Steps