Advanced Topics: ATPG

• Introduction
• Defect-based Testing
• Advanced ATPG
 N-detect ATPG (Stanford 1995)
 Introduction
 ATPG
 Experimental Results
 Cell-aware ATPG (Mentor 2009)
 Timing-aware ATPG (Mentor 2006)
 Power-aware ATPG (KIT 2005)
• Conclusion

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 N-detect Test Set
• What is N-detect test set?
 Detect each fault at least N times, if possible
 Every detecting pattern can be different (but not required)
 Can be applied to any fault model e.g. SSF, TDF
• Discovered by IBM and other companies
 but first published by Stanford Murphy experiment [Ma 95]
• Why N-detect test set useful?
 Improve DPM
 Increase diversity of test patterns
 Increase probability to detect un-modeled defects

𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑓𝑎𝑢𝑙𝑡𝑠 𝒅𝒆𝒕𝒆𝒄𝒕𝒆𝒅 𝒂𝒕 𝒍𝒆𝒂𝒔𝒕 𝑵 𝒕𝒊𝒎𝒆𝒔

𝑭𝒂𝒖𝒍𝒕 𝑪𝒐𝒗𝒆𝒓𝒂𝒈𝒆𝑵−𝒅𝒆𝒕 = × 100%
𝑛𝑢𝑚𝑏𝑒𝑟 𝑜f tota𝑙 𝑓𝑎𝑢𝑙𝑡𝑠

2 VLSI Test 18.4 © National Taiwan University

 Example 1
• {00, 11} single-detect SSF test set
 But does not detect bridging fault
• {00, 11, 01, 10 } 2-detect SSF test set
 More likely to detect bridging fault

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 Example 2
• Diversified test patterns help to detect different bridging faults

[Benware 03]

Detection condition
highlighted

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 N-detect ATPG Algorithm [Benware 03]
N-detect ATPG (N) // N = number of detections

1 Perform single-detect ATPG obtain test pattern set T1

2 TFMD = all faults detected by single-detect fault simulation with T1
3 for i = 1 to N-1
4 Perform multiple-detect fault sim with T1 to Ti for TFMD faults
5 Save faults detected exactly i times to Fi
6 Target faults Fi and perform single-detect ATPG
7 Save patterns to Ti+1
8 Perform multiple-detect fault simulation with T1 to TN for all faults
to obtain multiple-detect fault coverage profile

50
T1 50
T1+T2 50
T1+T2+T3
# of faults

40 40 40
30 30 30
20 20 20
10 10 10
0 0 0
F1 F2 F3 F4 F5 or F1 F2 F3 F4 F5 or F1 F2 F3 F4 F5 or
more more more

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 Example (1/2)
X X Consider only 4 faults
A/1 A/0
X
X
K/1
J/1

T1 A B C E H J K Detected faults
P1 0 1 0 1 0 0 1 A/1, J/1
P2 0 0 0 0 0 1 0 K/1
P3 1 1 1 1 1 0 0 A/0, K/1

F1 ={A/1, A/0, J/1} F2 ={K/1} F3 ={}

i = 1, target fault list = F1
T2 A B C E H J K Detected faults
P4 0 0 1 1 0 0 1 J/1, A/1
P5 1 1 0 1 1 0 0 A/0, K/1

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 Example (2/2)
X X
A/1 A/0
X
X
K/1
J/1

T2 A B C E H J K Detected faults
P4 0 0 1 1 0 0 1 J/1, A/1
P5 1 1 0 1 1 0 0 A/0, K/1

F1 ={} F2 ={J/1, A/1, A/0} F3 ={K/1}

i = 2, target fault list = F2
T3 A B C E H J K Detected faults
P6 0 1 0 1 0 0 1 J/1, A/1
P7 1 0 1 1 1 0 0 A/0, K/1

7 Patterns, FC3-det=100%
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 Stanford Experiments
• Murphy experiment: 0.7 mm • ELF experiment: 0.35 mm
 Total 5.5K chips tested  Total 10K chips tested
 116 defective chips 324 defective chips

Number of test escapes [McCluskey 04]

Number of test escapes [McCluskey 00]

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 LSI/Mentor Experiments [Benware 03]

• Test effectiveness increase with N

PFA photo of chip failed N-detect test

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 Quiz
Q: Consider 3 SSF, what is F1, F2, F3 of this test set?
What is 2-detect SSF fault coverage?
A: F1={ }, F2={ }, F3={ }
FC2-det=
A B C E H J K Detected faults
P1 1 1 0 1 1 0 0 L/0
P2 0 0 0 0 0 1 0 C/1
P3 1 0 1 1 1 0 0 L/0
P4 0 0 1 1 0 0 1 K/0

X
L/0
X
K/0

X
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 Advanced Topics: ATPG
• Introduction
• Defect-based Testing
• Advanced ATPG
N-detect (Stanford 1995)
 Cell-aware (Mentor 2009)
 Introduction
 Experimental Results
 Timing-aware (Mentor 2006)
 Power-aware (KIT 2005)
• Conclusion

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 Problems with N-detect
• Test length grows (almost linearly) with N
Too long for large N
• Do not know reasons why and which defects are detected
 Some patterns are more useful than others
 Hard to Compress
5000
4500
4000
3500
Test Length

3000
2500
2000
1500
1000
500 [McCluskey 00]
0
0 5 10 15 20
N

TL Too Long for Large N

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 Gate-level Fault Model Not Enough

Fault Models for Logic Circuits

“High” level Gate level Transistor level

or Functional level (inter-cell) (intra-cell)
or RT-level
X X
X Stuck-open Stuck-on Cell-aware
X
X X X X
X

Stuck-at Bridging Transition Delay Path delay

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 Cell-aware Test (CAT) [Hapke 09]
• Consider different defects types inside cell: open, bridge, transistor
• Need layout extraction and analog fault simulation (SPICE)

[Mentor website]
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 Why CAT more Effective?
• 4 test patterns detect 8 SSF at MUX I/O pins
in0
 100% SSF coverage
out
in0 in1 ctrl out detected SSF
ctrl SA1, out SA1, in0 SA1 in1
0 1 0 0
1 0 0 1 in1 SA1
ctrl
1 0 1 0 ctrl SA0, out SA0, in0 SA0

1 1 1 1 in1 SA0

in0
• CAT adds {000} to detect in1/w bridging 0
in0 in1 ctrl out
1 0/1
0 1 0 0
1 0 0 1 in1
1 0 1 0 0
1 1 1 1
0 0 0 0/1 CAT is Effective
but Longer 0
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 CAT Test Generation

Library cell layout

Layout Extraction

Fault list

SPICE Simulation

Gate input patterns

ATPG

CAT Test Patterns

𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑓𝑎𝑢𝑙𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑒𝑑 𝑐𝑒𝑙𝑙 − 𝑎𝑤𝑎𝑟𝑒 𝑓𝑎𝑢𝑙𝑡𝑠
𝑭𝒂𝒖𝒍𝒕 𝑪𝒐𝒗𝒆𝒓𝒂𝒈𝒆𝑪𝑨𝑻 = × 100%
𝑛𝑢𝑚𝑏𝑒𝑟 𝑜f tota𝑙 𝐶𝑒𝑙𝑙 − 𝑎𝑤𝑎𝑟𝑒 𝑓𝑎𝑢𝑙𝑡𝑠
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 AMD Experiments [Hapke 14]
• AMD 32 nm, total 800K chips tested
• 699 chips failed only CAT, passed other tests

CAT CAT
(static) (delay)
90 141 468

Number of IC failed CAT

CAT Improves 885 DPM

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 Pros and Cons of CAT
• ☺ Advantage
Reduce DPM effectively
 Helps to diagnose yield loss due to library cells
•  Disadvantage
 Test length is longer than traditional test
 Needs Layout extraction and SPICE simulation for library cells

P. Maxwell, et.al, “Cell-Aware Diagnosis: Defective Inmates Exposed in their Cells”,

European Test Symposium (ETS) 2016
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 Quiz
Q: Suppose CAT requires 4 gate inputs {00, 01, 10, 11} for OR
gate. Please add test pattern to improve the following test set.
A:

A B C E H J K
P1 1 1 0 1 1 0 0
P2 0 0 0 0 0 1 0
P3 1 0 1 1 1 0 0
P4 0 1 1 1 0 0 1

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 Summary
• N-detect test (Stanford 1995)
Detects fault at least N times to increase diversity of test patterns
 ☺ Early effective test method to reduce DPM
  Very long test length for large N
  Do not know real reasons for test effectiveness
• Cell-aware test (Mentor 2009)
 ☺ Clearly know reasons for test effectiveness
 Useful for diagnosis of yield problems
  Also test length is longer
  Cell library preparation is difficult
 Layout extraction and analog fault simulation

Needs More Test Cost to Reduce DPM

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 References
• [Benware 03] B. Benware , C. Schuermyer , S. Ranganathan , R.
Madge , P. Krishnamurthy,” Impact of multipledetect test patterns on
product quality, “IEEE Int’l Test Conference, 2003.
• [Hapke 09] F. Hapke, et al. "Defect-oriented cell-aware ATPG and
fault simulation for industrial cell libraries and designs." IEEE Int’l
Test Conference, 2009.
• [Ma 95] Ma, S.C., P. Franco, and E.J. McCluskey, “ An Experimental
Chip To evaluate Test Techniques Experimental Results,” Proc. ITC,
pp.663-672, 1995.
• [McCluskey 00] E. J. McCluskey and C. W. Tseng, "Stuck-fault tests
vs. actual defects," Int’l Test Conf., 2000.
• [McCluskey 04], EJ McCluskey, JCMLi, et al “ELF-Murphy Data on
Defects and Test Sets,” VTS 2004.

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