VLSI Testing

積體電路測試

Sequential ATPG

Professor James Chien-Mo Li 李建模

Lab. of Dependable Systems
Graduate Institute of Electronics Engineering
National Taiwan University

* Some picture are courtesy of Prof. Jiun-Lang Huang, NTU

1 VLSI Test 8.1 © National Taiwan University

 Course Roadmap (EDA Topics)
Logic Sim. Fault Collapsing

Fault Simulation Testability

Comb. ATPG

Diagnosis Seq. ATPG

2
Delay Test VLSI Test 8.1 © National Taiwan University
 Motivating Problem
 You already know ATPG for combinational circuits
 But manager asks you to generate a test for sequential circuits
 No scan allowed in flip-flops (FF)
a

X
SA1 y Y1
1
FF1
y2 Y2
FF2

3 VLSI Test 8.1 © National Taiwan University

 Why Am I Learning This?
 Sequential ATPG
 Generate test patterns for sequential circuits
 Without DFT or scan

“If life is a test,

one should wish it to be short.”

( Bernardin de Saint-Pierre )
4 VLSI Test 8.1 © National Taiwan University
 Test Generation

Fault Combinational Sequential

Models Circuits Circuits
(or Sequential
ckt. with scan)
No fault model PET Checking experiment

Single Stuck-at D Extended D

Fault Model PODEM 9-valued
FAN
Delay Fault Model Path Delay Launch on Capture
Transition Delay Launch on Shift
Fault

5 VLSI Test 8.1 © National Taiwan University

 Sequential ATPG
 Introduction
 Time-frame expansion methods
 Simulation-based methods * (not in exam)
 Issues of Sequential ATPG * (not in exam)
 Conclusions

6 VLSI Test 8.1 © National Taiwan University

 Huffman Model for Sequential Ckt. [Huffman 53]
 xi = primary inputs (PI)
 zi = primary outputs (PO)
 yi = FF (or latch) current states
 Yi = FF (or latch) next states

(WWW Fig 3.3)

Can be either
Moore or Mealy

7 VLSI Test 8.1 © National Taiwan University

 Sequential ATPG Assumptions
 NO SCAN ALLOWED!
 Control only PI
– FF not controllable
 Observe only PO
– FF not observable
 Faults in CL only
 NO fault in FF/latches

8 VLSI Test 8.1 © National Taiwan University

 Challenges of Sequential ATPG
 1. FF/latches states uncontrollable and unobservable
 FF/latch unknown initial states
 2. Long run time
 Comb. ATPG complexity (for a given fault)
– O(2number_of_PI)
 Seq. ATPG complexity (for a given fault)
– O(2number_of_PI x 9number_of_FF) *9-vlued logic will be covered soon

 3. Large memory space required

 Time frame expansion
 4. Low fault coverage
 Much worse than Comb. ATPG

Seq. ATPG is More Difficult Than Comb. ATPG

9 VLSI Test 8.1 © National Taiwan University
 Quiz
Q: For a sequential circuit with 100 flip-flops, what is worst
case sequential ATPG complexity?
A: 9100
B: 2100
C: 1002

 ANS: 9100 >> number of atoms in universe (1080 ) !

VLSI Test 8.1 © National Taiwan University

 Sequential ATPG
 Introduction
 Time-frame expansion methods
 The extended D-algorithm [Kubo 68]
 9-valued D algorithm [Muth 76]
 EBT [Marlett 78], BACK [Cheng 88] *
 Summary
 Simulation-based methods*
 Issues of Sequential ATPG*
 Conclusions

11 VLSI Test 8.1 © National Taiwan University

 Time Frame Expansion
 IDEA: Replicate circuits and connect time frames by wires
 yi = “states”; No FF!
 Replace clock cycles by space
 Becomes combinational ATPG problem
 NOTE: Target fault appears in every time frame

previous current next

Time frame -1 Time frame 0 Time frame 1

Xi-1 Xi Xi+1
C/L = comb. logic
xi = PI; zi = PO

12 VLSI Test 8.1 © National Taiwan University

 Extended D-Algorithm [Kubo 68]
1. Select a target fault f
2. Create a copy of the combinational logic, set it to time frame 0
3. Generate a test for f for time frame 0 using D-algorithm
4. If the fault effect is propagated to the FF’s, continue fault effect
propagation in the next time frame
5. If there are values required in the FF outputs, continue the
justification in the previous time frame

Time frame -1 Time frame 0 Time frame 1

13 VLSI Test 8.1 © National Taiwan University

 Example (1)
 STEP 2: create Time frame 0
 STEP 3: generate a test
 a0=1; y1=0 ; Y1=D’
a Time frame 0

a0
z
1
z0
X
SA1 y y2 Y2
1 Y1
FF1
y1 X Y1
y2 Y2 0 D’
FF2 SA1

Still Need Propagation

14 VLSI Test 8.1 © National Taiwan University
 Example (2)
 STEP4: Fault effect propagation to time frame 1
 a1=1

Time frame 0 Time frame 1

a0 a1
1 1
D’
z z
0

X X
0 D’
D’

Still Need Activation

15 VLSI Test 8.1 © National Taiwan University
 Example (3)
 STEP 5: Fault activation back to time frame -1
 a-1=0

Time frame -1 Time frame 0 Time frame 1

a-1 a0 a1
0 1 1
D’
z-1 z0 z1

X X X
0 D’ D’
SA1

Test Generated = 0, 1, 1
16 VLSI Test 8.1 © National Taiwan University
 Quiz
Q: Generate a test for stuck-at zero fault in sequential circuit.

z
SA0 X

y1 Y1
FF1
y2 Y2
FF2

VLSI Test 8.1 © National Taiwan University

 ANS
 No way to propagate
 This fault is untestable by sequential ATPG
 Endless timeframe expansion …
 Memory explosion!

Time frame 0 Time frame 1 Time frame 2

a-1 a0 a1

z-1 z0 z1

18 VLSI Test 8.1 © National Taiwan University

 Summary
 Sequential ATPG
 Time and space consuming
 Low fault coverage
 Time-frame expansion methods - extended D-algorithm
 Replicate circuits into many time frames
 Propagate forward, the then activated backward
 create new time frame if needed

19 VLSI Test 8.1 © National Taiwan University

 FFT
 In comb. ATPG, first fault activation, then propagation
 In seq. ATPG, first propagation, then activation
 why?

Time frame -1 Time frame 0 Time frame 1

a-1 a0 a1
0 1 1
D’
z-1 z0 z1

X X X
0 D’ D’
SA1

20 VLSI Test 8.1 © National Taiwan University