U20ECCJ12 DIGITAL ELECTRONICS UNIT3 IMPORTANT QUESTIONS WITH ANSWERS

UNIT3 SYLLABUS

Unit III Analysis And Design Of Synchronous Sequential Circuits

• Storage Elements- SR Latch, D Latch,
• Storage Elements – Edge Triggered Flip Flop,
• Characteristics tables,
• Characteristic Equations,
• Direct Inputs,
• Analysis of Clocked Sequential Circuits-
• State Equations,
• State table,
• State Diagram,
• Flip Flop Input Equations,
• Mealy and Moore Models of Finite State Machines,
• State Reduction and Assignment,
• Synthesis Using T Flip-Flops,D Flip Flop and JK Flip Flop, Registers and Counters

Important questions

1
Important Question:What is and what are the types of Latch or Flip-flop storage elements?. What is triggering and various types of triggering?. Differentiate Latch and flipflop (6)
• Answer:
1.1).What is latch? a).What are the types of triggering?
• It is a sequential circuit that checks all of its inputs continuously and changes its output • They are
at any time. Many times enable signal is provided with the latch. When Enable or EN 1). Level triggering
signal is active output changes occur as input changes. 2). Edge triggering
1.2).What is flip-flop? • Various types of flip flops based on this triggering are given below.
• It is a sequential circuit that checks all of its inputs continuously and changes its output b).What are the types of flip flop based on triggering?
at any time. All times Clock or CLK signal is provided with the flip flop. When Clock or • They are
CLK signal is active output changes occur as input changes. 1).Level triggering Latch
2).Edge triggering flip flop
1.1). Differentiate Flip-flop and latches. • If output of the flip flop changes during the level of the CLK signal as shown in fig.1
• They are shown in table.1.1 given below. means that flip flop is called level triggering flip flop. When the inputs to the FF change
during the presence of the clock pulse, uncertainty in the output occurs. This problem
can be avoided by using Master-Slave FFs or edge triggered FFs.
• If output of the flip flop changes during the edges of the CLK signal as shown in fig.1
means that flip flop is called edge triggering flip flop.
• The various types of edge triggering flip flop are given below.
c).What are the edge triggering flip flops?
• They are
1).Negative edge triggering flip flop
2).Positive edge triggering flip flop
• If output of the flip flop changes during the positive edge of the CLK signal as shown
in fig.1 means that flip flop is called positive edge triggering flip flop.
• If output of the flip flop changes during the negative edge of the CLK signal as shown
in fig.1 means that flip flop is called negative edge triggering flip flop.
• The symbols of level, positive and negative edge flip flops are shown in figure.2(a),(b)
• There applications are given below. and (c) given below.
1.2).Where Latch or Flip-flop can be used?
• They can be used in 𝑄𝑄 𝑄𝑄
𝑄𝑄
1) storage circuits
2) counters Latch FF FF
3) shift register 𝐸𝐸𝐸𝐸 𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶
4) and many other computer applications 𝑄𝑄� 𝑄𝑄� 𝑄𝑄�
• Its various types are given below. (𝑏𝑏)
1.3).What are the t ypes of Latches? (𝑎𝑎) (𝑏𝑏)
𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿ℎ with 𝐹𝐹𝐹𝐹 with 𝐹𝐹𝐹𝐹 with
• They are Negative edge
1) SR Latch Level CLK Positive edge
CLK CLK
2).JK Latch
3).T Latch
4).D Latch • The difference between Latch anf flip flop are given below.
1.4).What are the t ypes of flip-flops?
• They are 1.6).What is the difference betw een Latch and flip-flops?
1) SR Flip Flop • A storage element if it operate only during level triggering of the clock(CLK) signal
2).JK Flip Flop means it is called latch.
3).T Flip Flop • A storage element If it operate only during edge triggering of the CLK signal means it
4).D Flip Flop is called flip flop or FF.
• Its triggering and its various types of triggering are given below. • The main problem of this latch and flip flop are race around condition which is given
1.5).What is flip-flop triggering? What are its t yp es? below.
• The condition of the outputs changes from one state to another is called triggering. 1.7).What is Race Around Condition? How to eliminate it?
The triggering is happening in FFs only due to the clock signal (CLK) which is shown • Duration of the CLK signal, the output will oscillates back and forth between 0 and
in figure.1 given below. one. This situation is referred as race around condition.
𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 • This race around condition can be eliminate by using Master slave FF.
𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒

𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
𝑜𝑜𝑜𝑜
𝐶𝐶𝐶𝐶𝐶𝐶
𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑜𝑜𝑜𝑜
𝑡𝑡ℎ𝑒𝑒 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
Figure.1.1
• The above figure.1 shows that the duration of one clock pulse. It also shows that each
pulse has three elements. They are 1).positive edge 2).Level 3).negative edge
• Based on these elements, various types of triggering are given below.

2
Important Question:Briefly explain SR,JK,D and T Latches with its symbol, operation, truth table and its logic circuit diagram.(10)
• Answer:
SR Latch JK Latch T Latch D Latch
1.1).What is its s ymbol? 2.1).What is its s ymbol? 3.1).What is its s ymbol? 4.1).What is its s ymbol?
• It is shown below. • It is shown below. • It is shown below. • It is shown below.

𝑆𝑆 𝑄𝑄 𝐽𝐽 𝑄𝑄 𝑇𝑇 𝑄𝑄 𝐷𝐷 𝑄𝑄
𝐸𝐸𝐸𝐸 𝑆𝑆𝑆𝑆 𝐽𝐽𝐽𝐽 𝑇𝑇 𝐷𝐷
𝐸𝐸𝐸𝐸 𝐸𝐸𝐸𝐸 𝐸𝐸𝐸𝐸
Latch Latch Latch Latch
𝑅𝑅 𝑄𝑄� 𝐾𝐾 𝑄𝑄� 𝑄𝑄� 𝑄𝑄�
• Its operation is given below. • Its operation is given below. • Its operation is given below. • Its operation is given below.
1.2).What is its operation? 2.2).What is its operation? 3.2).What is its operation? 4.2).What is its operation?
• Its operation is shown in its truth table • Its operation is shown in its truth table • Its operation is shown in its truth table • Its operation is shown in its truth table
given below. given below. given below. given below.
1.3).What is its truth table? 2.3).What is its truth table? 3.3).What is its truth table? 4.3).What is its truth table?
• It is shown below. • It is shown below. • It is shown below. • It is shown below.

Table.1.1 Table.2.1 Table.3.1 Table.4.1

• Its state table is given below. • Its state table is given below. • Its state table is given below. • Its state table is given below.
1.3).What is its charecteristics 2.3).What is its charecteristics 3.3).What is its charecteristics 4.3).What is its charecteristics
table or state table? table or state table? table or state table? table or state table?
• The table indicates all transitions from • The table indicates all transitions from • The table indicates all transitions from • The table indicates all transitions from
each present state to the next state for each present state to the next state for each present state to the next state for each present state to the next state for
different values of the input signal is different values of the input signal is different values of the input signal is different values of the input signal is
called charecteristics table. called charecteristics table. called charecteristics table. called charecteristics table.
• It is also called state table. • It is also called state table. • It is also called state table. • It is also called state table.
• It is given below. • It is given below. • It is given below. • It is given below.

Table.1.2 Table.2.2 Table.3.2 Table.4.2

• Its charecteristics equation is given • Its charecteristics equation is given • Its charecteristics equation is given • Its charecteristics equation is given
below. below. below. below.
1.4).What is its charecteristics 2.4).What is its charecteristics 3.4).What is its charecteristics 4.4).What is its charecteristics
equation or state equation? equation or state equation? equation or state equation? equation or state equation?
• It can be obtained from its state table. • It can be obtained from its state table. • It can be obtained from its state table. • It can be obtained from its state table.
• Its charecteristics equation or state • Its charecteristics equation or state • Its charecteristics equation or state Its charecteristics equation or state
equation as shown below. equation as shown below. equation as shown below. equation as shown below.
� 𝑸𝑸𝒏𝒏
𝑸𝑸𝒏𝒏+𝟏𝟏 = 𝑺𝑺 + 𝑹𝑹 …(1.1) ����
𝑸𝑸𝒏𝒏+𝟏𝟏 = 𝑱𝑱𝑸𝑸 �
𝒏𝒏 + 𝑲𝑲𝑸𝑸𝒏𝒏 …(2.1) ����
𝑸𝑸𝒏𝒏+𝟏𝟏 = 𝑻𝑻𝑸𝑸 �
𝒏𝒏 + 𝑻𝑻𝑸𝑸𝒏𝒏 …(3.1) 𝑸𝑸𝒏𝒏+𝟏𝟏 = 𝑫𝑫 …(4.1)
• Its logic diagram is as shown below. • Its logic diagram is as shown below. • Its logic diagram is as shown below. • Its logic diagram is as shown below.
1.5).What is implementation of 2.5).What is implementation of 3.5).What is implementation of 4.5).What is implementation of
logic circuits of Eqn.1.1? logic circuits of Eqn.2.1? logic circuits of Eqn.3.1? logic circuits of Eqn4.1?
• It is shown in fig.1.1 given below. • It is in fig.2.1 given below. • It is in fig.3.1 given below. • It is in fig.4.1 given below.

𝑆𝑆 𝑄𝑄 𝑇𝑇
𝐽𝐽 𝑄𝑄 𝑄𝑄 𝐷𝐷
𝑄𝑄
𝐸𝐸𝐸𝐸 𝐸𝐸𝐸𝐸
𝐸𝐸𝐸𝐸
𝑄𝑄� 𝑄𝑄� 𝐸𝐸𝐸𝐸
𝑅𝑅 𝐾𝐾 𝑄𝑄�
𝑄𝑄�

Figure 4.1
Figure1.1 Figure 3.1
Figure 2.1

3
Important Question:Briefly explain the construction, Graphic symbol, logic diagram, charecteristics table,characteristics equation,state table, state equation ,state diagram and
operation of various storage elements such as RS,D,JK and T Flip-flops.(Each 10 marks).
• Answer:

1). SR or RS Flip Flop 2). JK Flip Flop 3). T Flip Flop 4). D Flip Flop

Important Question:Briefly explain the Important Question:Briefly explain the Important Question:Briefly explain the Important Question:Briefly explain the
construction, Graphic symbol, logic construction, Graphic symbol, logic construction, Graphic symbol, logic construction, Graphic symbol, logic
diagram, charecteristics diagram, charecteristics diagram, charecteristics diagram, charecteristics
table,characteristics equation,state table, table,characteristics equation,state table, table,characteristics equation,state table, table,characteristics equation,state table,
state equation ,state diagram and operation state equation ,state diagram and operation state equation ,state diagram and operation state equation ,state diagram and operation
of RS flip flop.(10 MARKS) of JK flip flop. (10 MARKS) of T flip flop. (10 MARKS) of D flip flop. (10 MARKS)
• Answer: • Answer: • Answer: • Answer:
1.1).What are its s ymbols? 2.1).What are its s ymbols? 3.1).What are its s ymbols? 4.1).What are its s ymbols?
• They are given below. • They are given below. • They are given below. • They are given below.
𝑆𝑆 𝑄𝑄 𝑆𝑆 𝑄𝑄 𝑆𝑆 𝑄𝑄 𝐽𝐽 𝑄𝑄 𝐽𝐽 𝑄𝑄 𝐽𝐽 𝑄𝑄 𝑇𝑇 𝑄𝑄 𝑇𝑇 𝑄𝑄 𝑇𝑇 𝑄𝑄 𝐷𝐷 𝑄𝑄 𝐷𝐷 𝑄𝑄 𝑇𝑇 𝑄𝑄
𝑆𝑆𝑆𝑆 𝑆𝑆𝑆𝑆 𝐽𝐽𝐽𝐽 𝐽𝐽𝐽𝐽 𝐽𝐽𝐽𝐽 𝑇𝑇 𝑇𝑇 𝑇𝑇 𝐷𝐷 𝐷𝐷 𝐷𝐷
𝑆𝑆𝑆𝑆
FF 𝐶𝐶𝐶𝐶𝐶𝐶 FF 𝐶𝐶𝐶𝐶𝐶𝐶 FF FF FF
FF 𝐶𝐶𝐶𝐶𝐶𝐶 FF 𝐶𝐶𝐶𝐶𝐶𝐶FF FF 𝐶𝐶𝐶𝐶𝐶𝐶FF 𝐶𝐶𝐶𝐶𝐶𝐶 FF FF 𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶
𝑅𝑅 𝑄𝑄� 𝑅𝑅 𝑄𝑄� 𝑅𝑅 𝑄𝑄� 𝐾𝐾 𝑄𝑄� 𝐾𝐾 𝑄𝑄� 𝐾𝐾 𝑄𝑄� 𝑄𝑄� 𝑄𝑄� 𝑄𝑄� 𝑄𝑄� 𝑄𝑄� 𝑄𝑄�
(𝑎𝑎) (𝑏𝑏) (𝑐𝑐) (𝑎𝑎) (𝑎𝑎) (𝑏𝑏) (𝑐𝑐) (𝑎𝑎) (𝑏𝑏)
(𝑏𝑏) (𝑐𝑐) (𝑐𝑐)
𝑆𝑆𝑆𝑆 𝑆𝑆𝑆𝑆 with 𝑆𝑆𝑆𝑆 with 𝐽𝐽𝐽𝐽 𝑇𝑇 𝑇𝑇 with 𝑇𝑇 with 𝐷𝐷 𝐷𝐷 with
𝐽𝐽𝐽𝐽 with 𝐽𝐽𝐽𝐽 with 𝐷𝐷 with
Without Positive edge negative edge Without Without Positive edge negative edge Without Positive edge
Positive edge negative edge negative edge
CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK
CLK CLK
• Its operation is given below. • Its operation is given below. • Its operation is given below. • Its operation is given below.
1.2).What is its operation? 1.2).What is its operation? 1.2).What is its operation? 4.2).What is its operation?
• Its operation is shown in its • Its operation is shown in its • Its operation is shown in its • Its operation is shown in its
charecteristics table or state table given charecteristics table or state table given charecteristics table or state table given charecteristics table or state table given
below. below. below. below.
1.3).What is its charecteristics 2.3).What is its charecteristics 3.3).What is its charecteristics 4.3).What is its charecteristics
table or state table? table or state table? table or state table? table or state table?
• The table indicates all transitions from • The table indicates all transitions from • The table indicates all transitions from • The table indicates all transitions from
each present state to the next state for each present state to the next state for each present state to the next state for each present state to the next state for
different values of the input signal is different values of the input signal is different values of the input signal is different values of the input signal is
called charecteristics table. called charecteristics table. called charecteristics table. called charecteristics table.
• It is also called state table. • It is also called state table. • It is also called state table. • It is also called state table.
• It is given below. • It is given below. • It is given below. • It is given below.
Present Next Present Next Present Next Present Next
SR Flip-flop JK Flip-flop T Flip-flop D Flip-flop
state state state state state state state state
S R 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡+1 J K 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡+1 T 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡+1 D 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡+1
0 × 0 0 0 × 0 0 0 0 0 0 0 0
1 0 0 1 1 × 0 1 1 0 1 1 0 1
0 1 1 0 × 1 1 0 1 1 0 0 1 0
× 0 1 1 × 0 1 1 0 1 1 1 1 1
Table.1.1 Table.2.1 Table.3.1 Table.4.1
• Its charecteristics equation can be • Its charecteristics equation can be • Its charecteristics equation can be • Its charecteristics equation can be
evaluated as given below. evaluated as given below. evaluated as given below. evaluated as given below.
1.4).What is its charecteristics 2.4).What is its charecteristics 3.4).What is its charecteristics 4.4).What is its charecteristics
equation or state equation? equation or state equation? equation or state equation? equation or state equation?
• It can be obtained by mark above • It can be obtained by mark above • It can be obtained by mark above • It can be obtained by mark above
table.1.1 values into 3 variable K-Map table.2.1 values into 3 variable K-Map table.3.1 values into 2 variable K-Map table.4.1 values into 2 variable K-Map
as given below. as given below. as given below. as given below.
3 variable K-Map 3 variable K-Map 2 variable K-Map 2 variable K-Map
𝑆𝑆𝑆𝑆 � � 𝐽𝐽𝐽𝐽 ̅ �
𝑄𝑄𝑡𝑡 𝑆𝑆 𝑅𝑅 𝑆𝑆� 𝑅𝑅 𝑆𝑆𝑆𝑆 𝑆𝑆𝑅𝑅� 𝑄𝑄𝑡𝑡 𝐽𝐽 𝐾𝐾 ̅
𝐽𝐽𝐾𝐾 𝐽𝐽𝐽𝐽 �
𝐽𝐽𝐾𝐾 𝑄𝑄𝑡𝑡𝑇𝑇 𝑇𝑇� 𝑇𝑇
𝑄𝑄 𝐷𝐷 𝐷𝐷
�
𝑡𝑡
𝐷𝐷
0 1 3 2 0 1 3 2 0 1 0 1
���
𝑄𝑄𝑡𝑡 1 ���
𝑄𝑄𝑡𝑡 1 1 ���
𝑄𝑄𝑡𝑡 1 ���
𝑄𝑄𝑡𝑡 1
4 5 7 4 5 7 6 2 3 2 3
6 1
𝑄𝑄𝑡𝑡
1 1 𝑄𝑄𝑡𝑡 1 1 𝑄𝑄𝑡𝑡 1
𝑄𝑄𝑡𝑡
• If evaluated this, we can get its • If evaluated this, we can get its • If evaluated this, we can get its • If evaluated this, we can get its
charecteristics equation or state charecteristics equation or state charecteristics equation or state charecteristics equation or state
equation as shown below. equation as shown below. equation as shown below. equation as shown below.
𝑄𝑄𝑡𝑡+1 = 𝑆𝑆 + 𝑅𝑅�𝑄𝑄𝑡𝑡 …(1.1) ���𝑡𝑡 + 𝐾𝐾
𝑄𝑄𝑡𝑡+1 = 𝐽𝐽𝑄𝑄 � 𝑄𝑄𝑡𝑡 …(2.1) ���𝑡𝑡 + 𝑄𝑄𝑡𝑡 𝑇𝑇�
𝑄𝑄𝑡𝑡+1 = 𝑇𝑇𝑄𝑄 …(3.1) 𝑄𝑄𝑡𝑡+1 = 𝐷𝐷 …(4.1)
• Its logic diagram is as shown below. • Its logic diagram is as shown below. • Its logic diagram is as shown below. • Its logic diagram is as shown below.
1.5).What is implementation of 2.5).What is implementation of 3.5).What is implementation of 4.5).What is implementation of
logic circuits of Eqn.1.1? logic circuits of Eqn.2.1? logic circuits of Eqn.3.1? logic circuits of Eqn4.1?
• It is shown in fig.1.1 given below. • It is in fig.2.1 given below. • It is in fig.3.1 given below. • It is in fig.4.1 given below.

𝑆𝑆 𝑄𝑄 𝑇𝑇
𝐽𝐽 𝑄𝑄 𝑄𝑄 𝐷𝐷
𝑄𝑄
𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶
𝐶𝐶𝐶𝐶𝐶𝐶
𝑄𝑄� 𝑄𝑄� 𝐶𝐶𝐶𝐶𝐶𝐶
𝑅𝑅 𝐾𝐾 𝑄𝑄�
𝑄𝑄�

Figure 4.1
Figure1.1 Figure 3.1
Figure 2.1
• Its state diagram of state table is given • Its state diagram of state table is given • Its state diagram of state table is given • Its state diagram of state table is given
below. below. below. below.
1.6).What is its state diagram? 2.6).What is its state diagram? 3.6).What is its state diagram? 4.6).What is its state diagram?
• The state diagram is a graphical • The state diagram is a graphical • The state diagram is a graphical • The state diagram is a graphical
representation of state table. representation of state table. representation of state table. representation of state table.
• Its state of the circuit is represented by • Its state of the circuit is represented by • Its state of the circuit is represented by • Its state of the circuit is represented by
the node, and the directed arcs the node, and the directed arcs the node, and the directed arcs the node, and the directed arcs
represent the state transitions, from represent the state transitions, from represent the state transitions, from represent the state transitions, from
present state (node) to next state (node) present state (node) to next state (node) present state (node) to next state (node) present state (node) to next state (node)
at the occurrence of clock pulse. at the occurrence of clock pulse. at the occurrence of clock pulse. at the occurrence of clock pulse.
• The state diagram of its state table is • The state diagram of its state table is • The state diagram of its state table is • The state diagram of its state table is
given below. given below. given below. given below.

4
 Synthesis or Conversion using SR flip flop, JK Flip Flop,T Flip-Flops and D Flip Flop
• Conversion of one flip-flop using other flip-flops is implemented by the use of characteristic tables and excitation tables.
• Its various types are
1). SR Flip-Flop into D,JK,T Flip-Flop
2). JK Flip-Flop into a SR,D,T Flip-Flop
3). D Flip-Flop into a JK,T Flip-Flop

Important Question:Briefly explain synthesis or conversion using SR flip flop into D,JK,T Flip-Flop with its input equations.(10 marks)
Answer:

1).SR Flip-Flop into D Flip-Flop 2).SR Flip-Flop into T Flip-Flop 3).SR Flip-Flop into JK Flip-Flop

• Step 1: Draw the characteristic table of D flip-flop and • Step 1: Draw the characteristic table of T flip-flop and • Step 1: Draw the characteristic table of JK flip-flop and
excitation table of SR flip-flop as shown below. excitation table of SR flip-flop as shown below. excitation table of SR flip-flop as shown below.
1.1). Characteristic & excitation table 2.1). Characteristic & excitation table 3.1). Characteristic & excitation table

characteristic table excitation table characteristic table excitation table characteristic table of excitation table
of D FF of of T FF of JK FF of
SR FF SR FF SR FF
𝑄𝑄𝑡𝑡 𝐷𝐷 𝑄𝑄𝑡𝑡+1 𝑆𝑆 𝑅𝑅 𝑄𝑄𝑡𝑡 𝑇𝑇 𝑄𝑄𝑡𝑡+1 𝑆𝑆 𝑅𝑅 𝑄𝑄𝑡𝑡 𝐽𝐽 𝐾𝐾 𝑄𝑄𝑡𝑡+1 𝑆𝑆 𝑅𝑅
0 0 0 0 × 0 0 0 0 × 0 0 × 0 0 ×
0 1 1 1 0 0 1 1 1 0 0 1 × 1 1 0
1 0 0 0 1 1 1 0 0 1 1 × 1 0 0 1
1 1 1 × 0 1 0 1 × 0 1 × 0 1 × 0

• Its input equations is given below. • Its input equations is given below. • Its input equations is given below.
1.2).What are its input equations? 2.2).What are its input equations? 3.2).What are its input equations?
• Its input equations are obtained by mark above table • Its input equations are obtained by mark above table • Its input equations are obtained by mark above table
values into 2 variable K-Map as given below. values into 2 variable K-Map as given below. values into 2 variable K-Map as given below.
1.3).2 variable K-Map 2.3).3 variable K-Map 3.3).3 variable K-Map
For S For R For S For R For S For R
𝑄𝑄𝑡𝑡𝐷𝐷 𝐷𝐷
� 𝑇𝑇 � 𝑇𝑇 𝑄𝑄𝑡𝑡𝑇𝑇 𝑇𝑇� 𝐽𝐽𝐽𝐽 ̅ �
𝑄𝑄𝑡𝑡𝐷𝐷 𝐷𝐷
� 𝐷𝐷 𝐷𝐷 𝑄𝑄𝑡𝑡 𝑇𝑇 𝑇𝑇 𝐽𝐽𝐽𝐽 ̅ � ̅
𝐽𝐽𝐾𝐾 � 𝑄𝑄𝑡𝑡 𝐽𝐽𝐾𝐾 ̅
𝐽𝐽𝐾𝐾 �
𝐽𝐽𝐽𝐽 𝐽𝐽𝐾𝐾
0 1 𝑄𝑄𝑡𝑡 𝐽𝐽𝐾𝐾 𝐽𝐽𝐽𝐽 𝐽𝐽𝐾𝐾
0 1 0 1 0 1
���
𝑄𝑄𝑡𝑡 1 𝑄𝑄𝑡𝑡 𝑋𝑋
��� ���
𝑄𝑄𝑡𝑡 1 𝑄𝑄𝑡𝑡 𝑋𝑋
��� ���
𝑄𝑄𝑡𝑡 1 1 ���
𝑄𝑄𝑡𝑡 𝑋𝑋 𝑋𝑋
2 3 1
𝑄𝑄𝑡𝑡
2
𝑋𝑋
3
𝑄𝑄𝑡𝑡 12 3
𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡
2
1
3 𝑄𝑄𝑡𝑡 𝑋𝑋 𝑋𝑋 𝑄𝑄𝑡𝑡 1
𝑋𝑋
����
𝑆𝑆 = 𝑄𝑄𝑡𝑡 𝐽𝐽 𝑅𝑅 = 𝑄𝑄𝑡𝑡 𝐾𝐾
�
𝑅𝑅 = 𝐷𝐷
𝑆𝑆 = 𝐷𝐷 ����
𝑆𝑆 = 𝑄𝑄𝑡𝑡 𝑇𝑇 𝑅𝑅 = 𝑄𝑄𝑡𝑡 𝑇𝑇

• Implement logic circuits of its input equations 𝑆𝑆 = 𝐷𝐷 and • Implement logic circuits of its input equations 𝑆𝑆 = 𝑄𝑄����
𝑡𝑡 𝑇𝑇 and • Implement logic circuits of its input equations 𝑆𝑆 = 𝑄𝑄 ����
𝑡𝑡 𝐽𝐽 and
� are given below.
𝑅𝑅 = 𝐷𝐷 𝑅𝑅 = 𝑄𝑄𝑡𝑡 𝑇𝑇 are given below. 𝑅𝑅 = 𝑄𝑄𝑡𝑡 𝐾𝐾 are given below.
1.4). Implement logic circuits of 𝑺𝑺 = 𝑫𝑫 and 𝑹𝑹 = 𝑫𝑫 � 2.4). Implement logic circuits of 𝑺𝑺 = 𝑸𝑸 ����
𝒕𝒕 𝑻𝑻 and 3.4). Implement logic circuits of 𝑺𝑺 = 𝑸𝑸 ����
𝒕𝒕 𝑱𝑱 and
𝑹𝑹 = 𝑸𝑸𝒕𝒕 𝑻𝑻 𝑹𝑹 = 𝑸𝑸𝒕𝒕 𝑲𝑲
𝐷𝐷 𝑆𝑆 𝑄𝑄
FF 𝑆𝑆 𝑄𝑄 𝑄𝑄 𝑆𝑆 𝑄𝑄 𝑄𝑄
𝐽𝐽
𝐶𝐶𝐶𝐶𝐶𝐶 FF FF
𝑇𝑇
𝑅𝑅 𝑄𝑄� 𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶
𝐾𝐾
𝑅𝑅 𝑄𝑄� 𝑄𝑄� 𝑅𝑅 𝑄𝑄� 𝑄𝑄�

Important Question:Briefly explain synthesis or conversion using JK flip flop into a SR,D,T Flip-Flop with its input equations.(.(10 marks)
Answer:

4).JK Flip-Flop into D Flip-Flop 5).JK Flip-Flop into T Flip-Flop 6).JK Flip-Flop into SR Flip-Flop
Step 1: Draw the characteristic table of D flip-flop and Step 1: Draw the characteristic table of T flip-flop and Step 1: Draw the characteristic table of SR flip-flop and
excitation table of JK flip-flop as shown below. excitation table of JK flip-flop as shown below. excitation table of JK flip-flop as shown below.
4.1).What is its Characteristic & excitation table? 5.1).What is its Characteristic & excitation table? 6.1).What is its Characteristic & excitation table?
• Its shown in table below. • Its shown in table below. • Its shown in table below.
characteristic table excitation table characteristic table excitation table characteristic table of excitation table
of D FF of of T FF of SR FF of
JK FF JK FF SR FF
𝑄𝑄𝑡𝑡 𝐷𝐷 𝑄𝑄𝑡𝑡+1 𝐽𝐽 𝐾𝐾 𝑄𝑄𝑡𝑡 𝑇𝑇 𝑄𝑄𝑡𝑡+1 𝐽𝐽 𝐾𝐾 𝑄𝑄𝑡𝑡 𝑆𝑆 𝑅𝑅 𝑄𝑄𝑡𝑡+1 𝐽𝐽 𝐾𝐾
0 0 0 0 × 0 0 0 0 × 0 0 × 0 0 ×
0 1 1 1 × 0 1 1 1 × 0 1 0 1 1 ×
1 0 0 × 1 1 1 0 × 1 1 0 1 0 × 1
1 1 1 × 0 1 0 1 × 0 1 × 0 1 × 0
× 1 1 × × ×
• Its input equations is given below. • Its input equations is given below. • Its input equations is given below.
4.2).What are its flip flop input equations? 5.2).What are its flip flop input equations? 6.2).What are its flip flop input equations?
• Its input equations are obtained by mark above table • Its input equations are obtained by mark above table • Its input equations are obtained by mark above table
values into 2 variable K-Map as given below. values into 2 variable K-Map as given below. values into 3 variable K-Map as given below.
4.3).2 variable K-Map 5.3).2 variable K-Map 6.3).3 variable K-Map
For J For K For J For K For J For J
𝑆𝑆𝑆𝑆 𝑆𝑆𝑆𝑆
𝑄𝑄𝑡𝑡 𝑆𝑆̅𝑅𝑅� 𝑆𝑆̅𝑅𝑅 𝑆𝑆𝑆𝑆 𝑆𝑆𝑅𝑅� 𝑄𝑄𝑡𝑡 𝑆𝑆̅𝑅𝑅� 𝑆𝑆̅𝑅𝑅 𝑆𝑆𝑆𝑆 𝑆𝑆𝑅𝑅�
𝑄𝑄𝑡𝑡𝐷𝐷 �
𝐷𝐷 𝐷𝐷 𝑄𝑄𝑡𝑡𝐷𝐷 �
𝐷𝐷 𝐷𝐷 𝑄𝑄𝑡𝑡𝑇𝑇 𝑇𝑇� 𝑇𝑇 𝑄𝑄𝑡𝑡𝐷𝐷 𝑇𝑇� 𝑇𝑇
0 1 0 1 0 1 0 1 ���
𝑄𝑄𝑡𝑡 𝑋𝑋 1 ���
𝑄𝑄𝑡𝑡 𝑋𝑋 𝑋𝑋
���
𝑄𝑄𝑡𝑡 1 ���
𝑄𝑄𝑡𝑡 𝑋𝑋 ���
𝑄𝑄𝑡𝑡 1 ���
𝑄𝑄𝑡𝑡 1
𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 1 𝑋𝑋
2 3
1 2 3 2 3 2 3 𝑋𝑋 𝑋𝑋
𝑄𝑄𝑡𝑡 𝑋𝑋 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 𝑋𝑋 𝑄𝑄𝑡𝑡 𝑋𝑋
𝐽𝐽 = 𝑆𝑆 𝐾𝐾 = 𝑅𝑅
�
𝐾𝐾 = 𝐷𝐷 𝐾𝐾 = 𝑇𝑇
𝐽𝐽 = 𝐷𝐷 𝐽𝐽 = 𝑇𝑇
• Implement logic circuits of its input equations 𝑆𝑆 = 𝐷𝐷 and • Implement logic circuits of its input equations 𝑆𝑆 = 𝑇𝑇 and • Implement logic circuits of its input equations 𝐽𝐽 = 𝑆𝑆 and
� are given below.
𝑅𝑅 = 𝐷𝐷 𝑅𝑅 = 𝑇𝑇 are given below. 𝐾𝐾 = 𝑅𝑅 are given below.
4.4). Implement logic circuits of 𝑺𝑺 = 𝑫𝑫 and 𝑹𝑹 = 𝑫𝑫 � 5.4). Implement logic circuits of 𝑺𝑺 = 𝑻𝑻 and 𝑹𝑹 = 𝑻𝑻 6.4). Implement logic circuits of 𝑱𝑱 = 𝑺𝑺 and 𝑲𝑲 = 𝑹𝑹

𝐷𝐷 𝐽𝐽 𝑄𝑄 𝑇𝑇 𝐽𝐽 𝑄𝑄 𝑆𝑆 𝐽𝐽 𝑄𝑄
FF FF FF
𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶
𝐾𝐾 𝑄𝑄� 𝐾𝐾 𝑄𝑄� 𝑅𝑅 𝐾𝐾 𝑄𝑄�

5
 1).D Flip-Flop into T Flip-Flop 2). Master slave JK (or) MSJK Flip-Flop 3).Direct Inputs

Important Question:Briefly explain synthesis or conversion Important Question:Briefly explain Master slave JK FF flip- Important Question:Briefly explain direct inputs or direct
using D flip flop into a T flip-flop with its input equations.(6 flop.(6 marks) preset or direct clear of the flip-flop.(6 marks)
marks) Answer: Answer:
Answ er:
• Step 1: Draw the characteristic table of T flip-flop and 2.1).What is Master slave JK FF? 3.1).What is direct inputs or direct preset or
excitation table of D flip-flop as shown below. • It is a cascade of two FFs. First JK FF act as Master and direct clear?
1.1). Characteristic & excitation table second SR FF act as Slave one. • The inputs which are used to bringing all flip flops to an
• In this Master slave JK FF, the CLK pulse of the master JK initial state prior to their clocked operation is called direct
characteristic table excitation table FF is inverted and then given to the CLK input of the slave inputs of the flip flop.
of T FF of SR FF as shown in figure given below. • They also called direct preset or direct clear of the flip-flop.
D FF • They affect the flip flop on a positive (or negative) value of
𝑄𝑄𝑡𝑡 𝑇𝑇 𝑄𝑄𝑡𝑡+1 𝐷𝐷 the input signal without the need for a clock pulse.
0 0 0 0 𝑄𝑄 𝑆𝑆 𝑄𝑄 • Its symbol is given below.
𝐽𝐽 𝐽𝐽 FF 3.2).What is its s ymbol?
0 1 1 1 FF
1 1 0 0 𝐶𝐶𝐶𝐶𝐶𝐶 Master Slave • The symbol of a negative edge triggered JK flip flop with
1 0 1 1 𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶 direct inputs is shown in fig.1 given below.
𝐾𝐾 𝐾𝐾 𝑄𝑄� 𝑅𝑅 𝑄𝑄�
• Its input equations are given below.
1.2).What are its input equations?
• Its input equations are obtained by mark above table
values into 2 variable K-Map as given below. Figure 2.4
4.2).2 variable K-Map
2.2).What are its main advantages?
For D
• It is mainly used to eliminate Race Around Condition.

𝑄𝑄𝑡𝑡𝑇𝑇 𝑇𝑇� 𝑇𝑇 2.3).What is Race Around Condition? How to Figure.1

0 1 eliminate it? • In this fig.1, the “CP” denotes clock pulse input and “Clear”
���
𝑄𝑄𝑡𝑡 1 • Duration of the CLK signal, the output will oscillates back denotes direct inputs.
and forth between 0 and one. This situation is referred as • If the clear input is maintained at “0”, the flip flop remains
2 3 race around condition. cleared, regardless of the other inputs or the clock signal.
𝑄𝑄𝑡𝑡
1 • This race around condition can be eliminate by using • The operation of a JK flip flop with direct inputs is shown in
Master slave FF. function table given below.
���𝑡𝑡 + 𝑇𝑇� 𝑄𝑄𝑡𝑡 = 𝑇𝑇 ⊕ 𝑄𝑄𝑡𝑡 • Timing diagram of Master-Slave Flip-flop is given below.
𝐷𝐷 = 𝑇𝑇𝑄𝑄
• Implement logic circuits of 2.4). Timing diagram of Master-Slave Flip-flop
𝐷𝐷=𝑇𝑇⊕𝑄𝑄𝑡𝑡 are given below.
4.3). Implement logic circuits of 𝑫𝑫 = 𝑻𝑻 ⊕ 𝑸𝑸𝒕𝒕
CLK
𝑄𝑄 J
𝐷𝐷 𝑄𝑄
𝑇𝑇
FF
𝐶𝐶𝐶𝐶𝐶𝐶
𝑄𝑄� K
𝑄𝑄�
Master
output
Slave
output
Master Master slave Slave Slave
sets resets resets Sets No
slave (output) change
resets Master Master
Sets No
(toggle) change

6
 Meal y and Moore Models of Finite State Machines
Important Question:Briefly explain mealy and moore models of finite state machines with its state table, state diagram and implementation.(10 marks)
Answ er:
1.1).What are the w ays to design clocked sequential circuits?
• There are two basic ways to design clocked sequential circuits. These are using :
1. Mealy Machine.
2. Moore Machine.
1.2).What is Meal y model and Moore model?
• The Mealy model and Moore model differ only in the way the output is generated.
• If the output is a function of both the present state and input means that model is called Mealy model.
• If the output is a function of only the present state means that model is called Moore model.
1.3).What are the main difference betw een these models?
• The main difference between these model finite state machines are given below.

Mealy machine Moore Machine

1). Output is a function of present state as 1). Output is a function of only present
well as present input. state.
2). Input changes may affect the output of 2). Input changes does not affect the
the circuit output.
3). Requires less number of states for 3). Requires large number of states for
implementing same function implementing same function.
Mealy Machine Moore Machine
1.1).What is Meal y machine? 2.1).What is Moore machine?
• If a machine output is a function of both the present state and input means that model is • If a machine output is a function of only the present state means that model is called Moore
called Mealy model machine. model machine.
• It is shown in figure.1.1 given below. • It is shown in figure.2.1 given below.

𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂 𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼
𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼
𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
logic 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
logic

𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝
state
𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚
𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂 𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒
𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 logic
state

Figure.1.1 Figure.2.1
• Its state diagram is given below. • Its state diagram is given below.
1.2).What is its state diagram? 2.2).What is its state diagram?
• It is shown in figure.1.2 given below. • It is shown in figure.2.2 given below.
0/0
Initial
0
Initial
State 0 1
AB=00 0
0/0 0
0/0

1/0
0/0 GOT-11 1/1
AB=10 11/0

1/0
GOT-1
AB=01 111/1

Figure.1.2 Figure.2.2
• This figure.1.2 shows state diagram for Mealy State Machine for ‘111’ Sequence Detector. • This figure.1.2 shows state diagram for Moore State Machine for ‘111’ Sequence Detector.
• The logic diagram for this state machine is given below. • The logic diagram for this state machine is given below.
1.3).What is its logic diagram? 2.3).What is its logic diagram?
• It is shown in figure.1.3 given below. • It is shown in figure.2.3 given below.
X
𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂 J Q Z
Clock
K Q
𝐷𝐷 𝑄𝑄
𝐴𝐴
𝑄𝑄�

D Q
𝐷𝐷 𝑄𝑄
𝐶𝐶𝐶𝐶𝐶𝐶
Q
𝑄𝑄�

Figure.1.3 Figure.2.3
• The timing diagram for Mealy Model Sequence Detector is given below. • The timing diagram for Moore Model Sequence Detector is given below.
1.4).What is its timing diagram? 2.4).What is its timing diagram?
• It is shown in figure.1.4 given below. • It is shown in figure.2.4 given below.

Figure.1.4 Figure.2.4

7
 Counters
Important Question:Briefly explain various counters with its circuits, truth table and timing diagram .(10 marks)
Answ er:
1.1).What are the differences between sequential and combinational logic? 1.2).What is counter?
• They are shown in table given below. • A counter is a register (group of Flip-flop) capable of counting the number of clock pulse
arriving at its clock input. Its types are given below.
1.3).What are the counter t ypes?
• They are two major types
1). Asynchronous or Ripple counter
2). Synchronous counter
1.4).Differentiate ripple counter and s ynchronous counters?
They are shown in table given below.

1).As ynchronous or ripple Up/Dow n counter 2).Synchronous Up/Down Counter 3). Modulo-n-counter

1.1).What is As ynchronous or ripple Up/Dow n 2.1).What is s ynchronous Up/Dow n counter? 2.1).What is Modulo-n-counter?
counter? • The up-down counter has the capability of counting • A Modulo-n-counter will count 'n' states.
• The up-down counter has the capability of counting upwards as well as downwards. • For example a mod-7 counter will count the sequence 000,
upwards as well as downwards. • It is also called multimode counter. 001, 010, 011, 100,101,110 and then recycles to 000.
• It is also called multimode counter. • Its logic circuit diagram is given below. • Mod - 7 counter skips 111 states and it goes through
• Its logic circuit diagram is given below. seven different states.
• Its logic circuit diagram is given below.
1.2).What is its logic circuit diagram? 2.2).What is its logic circuit diagram? 2.2).What is its logic circuit diagram?
• The logic circuit diagram of this 3 bit asynchronous The logic circuit diagram of this 3 bit synchronous Up/Down- The logic circuit diagram of this 3 bit mod-7 counter is shown
Up/Down-counter is shown in fig.1.1 given below. counter is shown in fig.2.1 given below. in fig.3.1 given below.

𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 𝑄𝑄𝐶𝐶 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜

𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 1

𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 𝑄𝑄𝐶𝐶

𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 1
𝐽𝐽𝐴𝐴 𝑄𝑄𝐴𝐴 𝐽𝐽𝐵𝐵 𝑄𝑄𝐵𝐵 𝐽𝐽𝐶𝐶 𝑄𝑄𝐶𝐶
𝐽𝐽𝐴𝐴 𝑄𝑄𝐴𝐴 𝐽𝐽𝐵𝐵 𝑄𝑄𝐵𝐵 𝐽𝐽𝐶𝐶 𝑄𝑄𝐶𝐶
𝑄𝑄�𝐴𝐴 𝐾𝐾𝐵𝐵 𝑄𝑄�𝐵𝐵 𝐾𝐾𝐶𝐶
𝐾𝐾𝐴𝐴
𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑄𝑄�𝐴𝐴 𝐾𝐾𝐵𝐵 𝑄𝑄�𝐵𝐵 𝐾𝐾𝐶𝐶
𝐾𝐾𝐴𝐴
𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷

Figure.1.1 Figure.2.1 Figure.3.1

• Its operation is given below. • Its operation is given below. • Its operation is given below.
1.3).What is its operation? 2.3).What is its operation? 2.3).What is its operation?
• Its operation is shown in its truth table given below. • Its operation is shown in its truth table given below. • Its operation is shown in its truth table given below.
1.4).What is its truth table? 2.4).What is its truth table? 2.4).What is its truth table?
• The truth table for 3 -bit asynchronous Up/Down-counter is The truth table for 3 -bit synchronous Up/Down-counter is • The truth table for 3 -bit mod-7 counter is shown in
shown in table.1.1 given below. shown in table.2.1 given below. table.3.1 given below.

Table.2.1 Table.3.1
Table.1.1
a).During up-counter a).During up-counter
�������� = 1, this 3-bit asynchronous
• In fig.1.1, when 𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 �������� = 1, this 3-bit asynchronous
• In fig.2.1, when 𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷
up/down-counter will perform as up-counter. up/down-counter will perform as up-counter.
• It will count from 000 to 111 . • It will count from 000 to 111 .
�������� = 1 , gates G 2 and G 4 are disabled and
• If 𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 �������� = 1 , gates G 2 and G 4 are disabled and
• If 𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷
gates G 1 and G 3 are enabled. So that the circuit behaves gates G 1 and G 3 are enabled. So that the circuit behaves
as an up-counter circuit. as an up-counter circuit.
b).During down-counter b).During down-counter
�������� = 0, this 3-bit asynchronous
• In fig.1.1, when 𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 �������� = 0, this 3-bit asynchronous
• In fig.2.1, when 𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷
up/down-counter will perform as down-counter. up/down-counter will perform as down-counter.
• It will count down from 111 to 000 . • It will count down from 111 to 000 .
�������� = 0 , gates G 2 and G 4 are enabled and gates
• If 𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 �������� = 0 , gates G 2 and G 4 are enabled and gates
• If 𝑈𝑈𝑈𝑈/𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷
G 1 and G 3 are disabled. So that the circuit behaves as an G 1 and G 3 are disabled. So that the circuit behaves as an
down-counter circuit. down-counter circuit.

8
 4). Decade or mod-10 counter 5). Ring or standard ring counter 6). Twisted ring or Johnson or shift counter

4.1).What is Modulo-n-counter? 5.1).What is Ring or standard ring counter? 6.1).What is Tw isted ring or Johnson or shift
• A Decade or Modulo-10 counter will count '10' states. • In ring counter the output Q of each stage is connected to counter?
• Its logic circuit diagram is given below. the D input of the next stage and the output of the last • In a Johnson counter or twisted ring counter or shift
stage is fed back to the input of first stage. counter, the 𝑄𝑄 output of each stage of Flip-flop is
• Its logic circuit diagram is given below. connected to the D input of the next stage and the
complement output 𝑄𝑄� of the last stage is fed back to the
input of first stage.
• Its logic circuit diagram is given below.
4.2).What is its logic circuit diagram? 5.2).What is its logic circuit diagram? 6.2).What is its logic circuit diagram?
• The logic circuit diagram of this 4 bit mod-10 counter is • The logic circuit diagram of this 4 bit ring counter is shown The logic circuit diagram of this Johnson counter or twisted
shown in fig.4.1 given below. in fig.5.1 given below. ring counter or shift counter, is shown in fig.6.1 given below.
𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂 𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂
𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 𝑄𝑄𝐶𝐶 𝑄𝑄𝐷𝐷 𝑄𝑄𝐷𝐷
𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 𝑄𝑄𝐶𝐶 𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 𝑄𝑄𝐶𝐶 𝑄𝑄𝐷𝐷

J Q J Q J Q J Q D D D
D Q D Q Q Q D Q D Q D Q Q
𝐶𝐶𝐶𝐶𝐶𝐶 𝐵𝐵 𝐶𝐶 𝐷𝐷 𝐷𝐷
𝐴𝐴 𝐵𝐵 𝐶𝐶 𝐵𝐵 𝐶𝐶 𝐷𝐷
𝐴𝐴 𝐴𝐴
K Q K Q K Q K Q Q Q Q
Q Q Q Q Q
+5𝑉𝑉 𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶

𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅
������
𝐶𝐶𝐶𝐶𝐶𝐶 ������
𝐶𝐶𝐶𝐶𝐶𝐶

Fig.4.1 Fig.5.1 Fig.6.1

• Its operation is given below. • Its operation is given below. • Its operation is given below.
4.3).What is its operation? 5.3).What is its operation? 6.3).What is its operation?
• Its operation is shown in its truth table given below. • Its operation is shown in its truth table given below. • Its operation is shown in its truth table given below.
4.4).What is its truth table? 5.4).What is its truth table? 6.4).What is its truth table?
• The truth table for 4-bit mod-10 counter is shown in • The truth table for 4-bit ring counter is shown in table.5.1 • The truth table for 4-bit Johnson counter or twisted ring
table.4.1 given below. given below. counter or shift counter is shown in table.6.1 given below.

9
 Registers
Important Question:Briefly explain various types of registers with its state table, state diagram and implementation.(10 marks)
Answ er:
1.1).What is register? What is its other name?
• A group of flip-flops connected in series/parallel is called a register. It also called shift register. Its uses are given below.
1.2).What are the uses of register or shift register?
• The register or shift register is used to store a data.
• For store N bits, register with N flip-flops are required.
• Data can be stored in parallel or serial order.
• Similarly, serial to parallel conversion, and parallel to serial conversion can be done by using registers.
• The various types of registers or shift register are given below.
1.3).What are the t ypes of registers or shift register?
• Based on the mode of operation shift registers are classified into
i. Serial In-Serial Out or SISO shift registers
ii. Serial In-Parallel Out or SIPO shift registers
iii. Parallel In-Serial Out or PISO shift registers
iv. Parallel In-Parallel Out or PIPO shift registers
v. Bidirectional shift registers
vi. Universal shift registers

1).Serial-in serial-out shift register 2).Serial-in parallel-out shift register 3).Parallel-in parallel-out shift 4).Parallel-in serial-out shift
register register
1.1).What is its s ymbol? 2.1).What is its s ymbol? 3.1).What is its s ymbol? 4.1).What is its s ymbol?
• It is shown in figure 1.1 given below. It is shown in figure 2.1 given below. • It is shown in figure 3.1 given below. • It is shown in figure 4.1 given below.

Figure 1.1 Figure 2.1 Figure 3.1 Figure 4.1

• Its logic diagram is given below. • Its logic diagram is given below. • Its logic diagram is given below. • Its logic diagram is given below.
1.2).What is its logic diagram? 2.2).What is its logic diagram? 3.2).What is its logic diagram? 4.2).What is its logic diagram?
• It is shown in figure 1.2 given below. It is shown in figure 2.2 given below. • It is shown in figure 3.2 given below. • It is shown in figure 4.2 given below.
𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖
𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖
𝐷𝐷𝑖𝑖𝑖𝑖 𝐷𝐷𝑜𝑜𝑜𝑜𝑜𝑜 ��������
𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆/𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 𝑎𝑎 𝑏𝑏 𝑐𝑐
𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 𝑄𝑄𝐶𝐶 𝑐𝑐 𝑑𝑑 𝑑𝑑
(input) (output) 𝐷𝐷𝑖𝑖𝑖𝑖 𝑄𝑄𝐷𝐷 𝑎𝑎 𝑏𝑏
𝐷𝐷𝐴𝐴 𝑄𝑄𝐴𝐴 𝐷𝐷𝐵𝐵 𝑄𝑄𝐵𝐵 𝐷𝐷𝐶𝐶 𝑄𝑄𝐶𝐶 𝐷𝐷𝐷𝐷 𝑄𝑄𝐷𝐷
(input)
𝐴𝐴 𝐵𝐵 𝐶𝐶 𝐷𝐷 𝐷𝐷𝐴𝐴 𝑄𝑄𝐴𝐴 𝐷𝐷𝐵𝐵 𝑄𝑄𝐵𝐵 𝐷𝐷𝐶𝐶 𝑄𝑄𝐶𝐶 𝐷𝐷𝐷𝐷 𝑄𝑄𝐷𝐷
𝐷𝐷𝐴𝐴 𝑄𝑄𝐴𝐴 𝐷𝐷𝐵𝐵 𝑄𝑄𝐵𝐵 𝐷𝐷𝐶𝐶 𝑄𝑄𝐶𝐶 𝐷𝐷𝐷𝐷 𝑄𝑄𝐷𝐷
𝐴𝐴 𝐵𝐵 𝐶𝐶 𝐷𝐷
𝐶𝐶𝐶𝐶𝐶𝐶 𝐴𝐴 𝐵𝐵 𝐶𝐶 𝐷𝐷 𝐷𝐷𝑂𝑂𝑂𝑂𝑂𝑂
𝐶𝐶𝐶𝐶𝐶𝐶 𝐷𝐷𝐴𝐴 𝑄𝑄𝐴𝐴 𝐷𝐷𝐵𝐵 𝑄𝑄𝐵𝐵 𝐷𝐷𝐶𝐶 𝑄𝑄𝐶𝐶 𝐷𝐷𝐷𝐷 𝑄𝑄𝐷𝐷
𝐴𝐴 𝐵𝐵 𝐶𝐶 𝐷𝐷
𝐶𝐶𝐶𝐶𝐶𝐶 𝑄𝑄𝐵𝐵 𝑄𝑄𝐶𝐶 𝑄𝑄𝐷𝐷
𝑄𝑄𝐴𝐴
𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝐶𝐶𝐶𝐶𝐶𝐶

Figure 1.2 Figure 2.2 Figure 3.2 Figure 4.2

• Its operation is given below. • Its operation is given below. • Its operation is given below. • Its operation is given below.
1.3).What is its operation? 1.3).What is its operation? 1.3).What is its operation? 1.3).What is its operation?
• Its operation is shown its truth table. • Its operation is shown its truth table. • Its operation is shown its truth table. • Its operation is shown its truth table.
• Its truth table is given below. • Its truth table is given below. • Its truth table is given below. • Its truth table is given below.
1.4).What is its truth table? 1.4).What is its truth table? 1.4).What is its truth table? 1.4).What is its truth table?
• Its truth table is shown in table 1.1 given • Its truth table is shown in table 2.1 given • Its truth table is shown in table 3.1 given • Its truth table is shown in table 4.1 given
below. below. below. below.

Table 1.1 Table 2.1 Table 3.1 Table 4.1

1).Bidirectional shift register 2).universal shift register

1.1).What is Bidirectional shift register? 2.1).What is universal shift register?

• Bidirectional shift register allows shifting of data either to the left or to the right side. Here, • A shift register is referred to as universal shift register if it has both shifts (right shift and left
������� which allows the data shifting either towards right or
the control signal used is 𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅/𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 shift) and parallel load capabilities. Its logic circuit diagram is given below.
towards left. Its logic circuit diagram is given below. 2.2).What is its logic circuit diagram?
1.2).What is its logic circuit diagram? • A 4-bit unidirectional shift register logic circuit diagram is shown in fig.2.1 given below.
• A 4-bit Bidirectional shift register logic circuit diagram is shown in fig.1.1 given below.
�������
𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅/𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜

𝑄𝑄𝐶𝐶 𝑄𝑄𝐷𝐷
𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵

𝐷𝐷𝐴𝐴 𝑄𝑄𝐴𝐴 𝐷𝐷𝐵𝐵 𝑄𝑄𝐵𝐵 𝐷𝐷𝐶𝐶 𝑄𝑄𝐶𝐶 𝐷𝐷𝐷𝐷 𝑄𝑄𝐷𝐷

𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑖𝑖𝑖𝑖 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑖𝑖𝑖𝑖
𝑓𝑓𝑓𝑓𝑓𝑓 𝑟𝑟𝑟𝑟𝑟𝑟ℎ𝑡𝑡 𝑠𝑠ℎ𝑖𝑖𝑖𝑖𝑖𝑖 𝑓𝑓𝑓𝑓𝑓𝑓 𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 𝑠𝑠ℎ𝑖𝑖𝑖𝑖𝑖𝑖 𝐷𝐷
𝐴𝐴 𝐵𝐵 𝐶𝐶

𝑄𝑄𝐵𝐵 𝐷𝐷𝐷𝐷 𝑄𝑄𝐷𝐷

𝐷𝐷𝐴𝐴 𝑄𝑄𝐴𝐴 𝐷𝐷𝐵𝐵 𝐷𝐷𝐶𝐶 𝑄𝑄𝐶𝐶

𝐴𝐴 𝐵𝐵 𝐶𝐶 𝐷𝐷 𝑆𝑆1
4 𝑡𝑡𝑡𝑡 1 4 𝑡𝑡𝑡𝑡 1 4 𝑡𝑡𝑡𝑡 1 4 𝑡𝑡𝑡𝑡 1
𝑆𝑆0 𝑀𝑀𝑀𝑀𝑀𝑀 𝑀𝑀𝑀𝑀𝑀𝑀 𝑀𝑀𝑀𝑀𝑀𝑀 𝑀𝑀𝑀𝑀𝑀𝑀

𝐶𝐶𝐶𝐶𝐶𝐶

𝑄𝑄𝐷𝐷 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑖𝑖𝑖𝑖 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑖𝑖𝑖𝑖

𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 𝑄𝑄𝐶𝐶 𝑏𝑏 𝑐𝑐 𝑑𝑑
𝑓𝑓𝑓𝑓𝑓𝑓 𝑟𝑟𝑟𝑟𝑟𝑟ℎ𝑡𝑡 𝑠𝑠ℎ𝑖𝑖𝑖𝑖𝑖𝑖 𝑎𝑎 𝑓𝑓𝑓𝑓𝑓𝑓 𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 𝑠𝑠ℎ𝑖𝑖𝑖𝑖𝑖𝑖
𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜
𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖
Figure 1.1 Figure 2.1

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Important Question:Briefly explain state reduction and state assignment.(10 marks)
Answ er:
1).state reduction 2).state assignment
1.1).What is state reduction? 2.1).What is state assignment?
• A technique which reduces the number of Flip-flops and logic gates which reduces the cost • In order to design a sequential circuit, it is necessary to assign binary values to the state is
and circuit complexity of the circuit. called state assignment.
• This state reduction technique avoids the introduction of redundant states. • It can be explained with an example given below.
• It also called state minimization method.
• Here a state reduction algorithm is used to reducing the number of states in the state table.
1.2).What is state reduction algorithm?
• When two states in the state table are equivalent by producing the same next state and
same output then one of the states in the state table can be removed without altering the
input output relationship.
• Two states are said to be equivalent if the two states produces the same next state and
same output for each input. When two states are equivalent, one of them can be removed
without altering the input-output relationship.
• It can be explained with the following example
1.3).Give an example for state reduction. 2.2).Give an example for state assignment
• In table 1.1, two states 'c' and 'e' in the present state are equivalent. Both 'c' and 'e' states • For example, with three bits we can assign codes to maxirnum of 8 states. Here the
(present state) are having the same next states and same outputs. Let 'Z' be the output. reduced state diagram contains 4 states. So the binary code must contain 2 bits, so assign
𝑎𝑎 = 00, 𝑏𝑏 = 01, 𝑐𝑐 = 10 and 𝑑𝑑 = 11. Its state diagram is shown in fig.2.1 given below.

Table.1.1

Figure 2.1
• Since each state is represented by two bits, the circuit for the reduced state diagram must
contain two Flip-flops. If the state is assrgied without state reduction states a,b, c, d and e
are assigned with 3 bit binary code which requires 3 Flipflops for the circuit design. Thus the
state reduction reduces 3 Flip-flops to 2 Flipflops for the given state diagram.
• State diagram with assigned binary values is shown in fig.2.2 given below.

• Since states 'c' and 'e' are equivalent we can remove one of these two states. Here the
state 'e' is removed, replacing ‘e’ by 'c' as shown in table1.2 given below.

Figure 2.2
• Its reduced state table with assigned binary codes is also shown in table.2.1 given below.

Table.1.2
• This Table.1.2 is reduced state table or minimized state table.Its state diagram is shown in
fig.1.1 given below.

Table.2.1

Figure.1.1
The reduced state diagram in fig.1.1 has only 4 states. Thus the 5 states have been
reduced to 4 states.

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