DTE QUESTION BANK

Q1Define: Encoder
an encoder is a combinational circuit that converts data from a 2^n input lines format into an n-bit coded
output. Encoders simplify multiple inputs by encoding active input into a compact binary form.
2. Draw the MUX tree for 32:1 MUX using 4:1 MUX only(Not sure)

3. Minimize the following expression using K-map. f(A, B, C, D) = ∑ m (0, 1, 2, 4, 5, 7, 8, 9,10)

4. Draw the full adder circuit's logic diagram, truth table and K-map simplification
5. Draw the binary to gray code converter with the help of truth table and its Kmap simplification
(NOT FOUND)
6.Draw the 4-Bit adder circuit using IC 7483 and describe its working with suitable examples.

A 4-bit adder using the IC 7483 performs binary addition of two 4-bit numbers. The 7483 IC is a 4-bit
binary full adder, meaning it can add two 4-bit binary numbers along with a carry input and produce a 4-
bit sum and a carry output.
Working:
The IC has:
Inputs: Two 4-bit binary numbers (A and B) and an optional carry-in (Cin).
Outputs: A 4-bit sum (S) and a carry-out (Cout).
When A and B are provided as inputs:
Each bit of A is added to the corresponding bit of B.
Cin (initially 0) is added to the first bit pair.
The addition result for each bit is stored in the sum (S) and any carry generated is passed to the next
higher bit.
The final carry is stored in Cout if the addition exceeds 4 bits.
Example:
For inputs A = 1101 (13) and B = 1011 (11):
The 7483 adds these two 4-bit numbers:
1101+1011=11000.
The output S will display the lower 4 bits 1000 (8) and Cout = 1, representing 18 in decimal (13 + 11).
7. Draw logic diagram of half adder using K-map simplification and write truth table.
8. Draw 16: 1 mux tree using 4:1 .mux(NOT SURE)

Chapter 4

1. Write the one application of SR-FF and mention its one drawback
Application: An SR Flip-Flop (Set-Reset Flip-Flop) is commonly used in latch circuits for storing binary
data, as it holds a value (0 or 1) until it's reset. It's often used in memory storage or simple storage registers.

Drawback: The SR Flip-Flop has an undefined state when both inputs (S and R) are set to 1
simultaneously, which makes it unstable and can cause unreliable output.

2. Name four types of shift register.

Four types of shift registers are:
Serial-In Serial-Out (SISO)
Serial-In Parallel-Out (SIPO)
Parallel-In Serial-Out (PISO)
Parallel-In Parallel-Out (PIPO)
3. Describe the working of clocked SR flip-flop with preset and clear
Working:
Clock Input (CLK): The flip-flop only changes state on the clock’s active edge (usually rising or falling edge),
making it synchronous.
Set (S) and Reset (R): When the clock pulse is active:
If S = 1 and R = 0, the flip-flop sets (Q = 1).
If S = 0 and R = 1, the flip-flop resets (Q = 0).
If S = 0 and R = 0, it retains its previous state.
S = 1 and R = 1 is an invalid state, causing ambiguity.
Preset (PR): When PR = 0 (active low), it forces Q to 1 regardless of the clock or S and R inputs, setting the
flip-flop immediately.
Clear (CLR): When CLR = 0 (active low), it forces Q to 0 regardless of the clock or other inputs, clearing the
flip-flop immediately.
4. Design 4-bit ripple counter and draw output waveform
 5. Describe the working of J-K flip-flop and state the race around
condition.
Working of J-K Flip-Flop
The J-K flip-flop is a modified version of the SR flip-flop, designed to eliminate the invalid
state (when both inputs are 1). It has two inputs, J and K, and operates based on the clock
signal.

 J = 0, K = 0: No change (Q retains its previous state).

 J = 0, K = 1: Reset (Q = 0).
 J = 1, K = 0: Set (Q = 1).
 J = 1, K = 1: Toggle the current state (Q changes to the opposite state of its previous value).

Race Around Condition:

The race-around condition occurs when both J and K are 1 while the clock is active. In this case,
the output Q toggles continuously because the flip-flop keeps changing states rapidly as long as the
clock is high. This causes instability, and the output can oscillate, leading to unpredictable behavior.

To avoid this, a master-slave JK flip-flop configuration is used, where the flip-flop is triggered on
different clock edges to prevent the continuous toggling.

6. Describe the operation of R-S flip-flop using NAND gate.

An RS flip-flop can be constructed using two NAND gates. It has two inputs: R (Reset) and S (Set), and
two outputs: Q and Q' (Q complement).

Working:

1. Inputs and Outputs:

o The first NAND gate has inputs S and Q' (output of the second NAND gate). Its output is Q.
o The second NAND gate has inputs R and Q (output of the first NAND gate). Its output is Q'.
2. States:
o S = 1, R = 0: The output Q = 1 (Set state), and Q' = 0.
o S = 0, R = 1: The output Q = 0 (Reset state), and Q' = 1.
o S = 0, R = 0: The outputs retain their previous state (latching behavior).
 o S = 1, R = 1: This condition creates an invalid state because both Q and Q' would be 1,
violating the basic principle that Q and Q' should always be complementary.

7. Describe the operation of 4 bit serial in serial out shift register.

A 4-bit Serial-In Serial-Out (SISO) shift register consists of four flip-flops connected in series, with each
flip-flop storing one bit of data. The data is shifted in one bit at a time from the serial input (SI) and shifted
out one bit at a time from the serial output (SO).

Working:

1. Shift Register Configuration:

o The register has 4 stages (flip-flops) where each flip-flop stores one bit.
o Data is entered serially, meaning one bit is shifted in on each clock pulse.
o On each clock cycle, the bits shift one position to the right, and the bit from the serial input
(SI) is placed in the leftmost flip-flop (Stage 1).
o The bit in the rightmost flip-flop (Stage 4) is shifted out to the serial output (SO).
2. Data Flow:
o Initially, the shift register is empty or filled with zeros.
o On the first clock pulse, the first bit from the serial input is shifted into the first flip-flop. The
other flip-flops shift their bits to the next position.
o This process continues for each subsequent clock pulse, with the data moving from one flip-
flop to the next until it reaches the last flip-flop and is outputted at SO.

8. Define counter.
A counter is a digital device used to count the number of events or clock pulses. It typically consists of a series of flip-
flops and can count in either a binary or decimal sequence.
9. Draw 4-bit twisted ring counter and explain its working with truth table and waveform.
Twisted Ring Counter:

A Twisted Ring Counter, also known as a Johnson counter, is a type of shift register counter where the
output of the last flip-flop is fed back to the input of the first flip-flop, but with inversion. It is often used for
generating a sequence of states.

Working of Twisted Ring Counter:

1. It typically uses n flip-flops (e.g., for a 4-bit counter, there are 4 flip-flops).
2. The inverted output of the last flip-flop is connected back to the input of the first flip-flop, causing
the state to shift in a specific pattern.
3. For each clock pulse, the state of the flip-flops changes according to the feedback, producing a
specific output sequence.

10. Compare between synchronous and asynchronous counter

11. Draw symbol and write the truth table for T-flip-flop
Chapter 5:

1. List any two specifications/ features of IC 0809.

 4-bit Binary Full Adder: It can add two 4-bit binary numbers along with a carry input and produce a 4-
bit sum and a carry output.

 Low Power Consumption: The IC is designed to operate with low power, making it suitable for use in
digital circuits where efficiency is important.

3. Calculate the analog output of 8 -Bit DAC for digital input 10011100. Assume V full scale=5V
(NOTSURE)
3. Describe the working principle of dual slope type of ADC with neat diagram.
Working Steps:

1. Integration Phase:
o The input analog signal (V_in) is applied to an integrator circuit (a capacitor is charged
through a resistor).
o The integrator continuously integrates the input signal over a fixed period, resulting in a
linearly increasing or decreasing voltage (depending on the polarity of V_in).
o The integrator output (V_out) is proportional to the time it takes for the input to charge the
capacitor to a specific voltage.
2. De-integration Phase:
o After the integration phase, a reference voltage (V_ref) of known polarity and magnitude is
applied to the integrator.
o The reference voltage causes the integrator's output to discharge (de-integrate) at a known
rate, typically in a fixed time period.
o The time required for the integrator output to return to zero is measured.
3. Digital Output:
o The time taken during the de-integration phase is directly proportional to the input voltage
(V_in).
o A counter measures the de-integration time, and the result is converted into a digital value,
representing the input voltage.
4. Compare weighted resister DAC with R-2R ladder type DAC.