Chapter 3 Combinational Circuits
Chapter 3 Combinational Circuits
Combinational Circuits:
A digital logic circuit is defined as the one in which voltages are assumed to be having a finite
number of distinct value. Types of digital logic circuits are combinational logic circuits and
sequential logic circuits. These are the basic circuits used in most of the digital electronic devices
like computers, calculators, mobile phones.
Digital logic circuits are often known as switching circuits, because in digital circuits the voltage
levels are assumed to be switched from one value to another value instantaneously. These
circuits are termed as logic circuits, as their operation obeys a definite set of logic rules.
Classification of logical circuits:
A. Combinational Circuit :
Combinational digital logic circuits are basically made up of digital logic gates like AND
gate, OR gate, NOT gate and universal gates (NAND gate and NOR gate).
All these gates are combined together to form a complicated switching circuit. The logic
gates are building blocks of combinational logic circuits. In a combinational logic circuit,
the output at any instant of time depends only on present input at that particular instant of
time and combinational circuits do not have any memory devices.
Encoders and Decoders are examples of combinational circuit. A decoder converts the
binary coded data at its present input into a number of different output lines. Other
examples of combinational switching circuits are half adder and full adder, encoder,
decoder, multiplexer, de-multiplexer, code converter etc.
Combinational circuits are used in microprocessor and microcontroller for designing the
hardware and software components of a computer.
Classification of combinational digital logic circuits
Combinational digital logic circuits are classified into three major parts – arithmetic or
logical functions, data transmission and code converter.
The following chart will elaborate the further classifications of combinational digital
logic circuit.
Application of combinational circuit :
Adder:
An Adder is a device that can add two binary digits. It is a type of digital circuit that
performs the operation of additions of two numbers. It is mainly designed for the addition
of binary number, but they can be used in various other applications like binary code
decimal, address decoding, table index calculation, etc. There are two types of Adder.
One is Half Adder, and another one is known as Full Adder. The detail explanation of
the two types of the adder is given below
1. Design Half Adder Circuit:
There are two inputs and two outputs in a Half Adder. Inputs are named as A and B, and
the outputs are named as Sum (S) and Carry (C). Half adder, is designed to add two one
bit number with the help of logic gates. The binary addition as shown below.
0+0=0
0+1=1
1+0=1
1 + 1 = 10
Here the output “1” of “10” becomes the carry-out. SUM is the normal output and the
CARRY is the carry-out.
Block diagram of half adder
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From above truth table we know that we have write two k-map solution for two outputs.
For sum (S) output and for carry output (C)
1. K-Map for Sum is as shown below
S = A’B+AB’
Circuit diagram for this output is EX-OR gate as shown below
● Half adders have no scope of adding the carry bit resulting from the addition of previous
bits.
● This is because real time scenarios involve adding the multiple number of bits which can
not be accomplished using half adders.
2.Design Full Adder.
Full Adder-
● It is used for the purpose of adding two single bit numbers with a carry.
● Thus, full adder has the ability to perform the addition of three bits.
● Full adder contains 3 inputs and 2 outputs (sum and carry) as shown
A B Cin S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Step-03:
Draw K-maps using the above truth table and determine the simplified Boolean
expressions-
● It requires n full adders in its circuit for adding two n-bit binary numbers.
Using ripple carry adder, this addition is carried out as shown by the following logic
diagram-
As shown-
● Each full adder takes the carry-in as input and produces carry-out and sum bit as
output.
● The carry-out produced by a full adder serves as carry-in for its adjacent most
significant full adder.
● When carry-in becomes available to the full adder, it activates the full adder.
● The two 4-bit numbers are 0101 (A3A2A1A0) and 1010 (B3B2B1B0).
4-bit Ripple Carry Adder carries out the addition as explained in the following stages-
Stage-01:
● When Cin is fed as input to the full Adder A, it activates the full adder A.
Full adder A computes the sum bit and carry bit as-
Calculation of S0–
S0 = A0 ⊕ B0 ⊕ Cin
S0 = 1 ⊕ 0 ⊕ 0
S0 = 1
Calculation of C0–
C0 = A0B0 ⊕ B0Cin ⊕ CinA0
C0 = 1.0 ⊕ 0.0 ⊕ 0.1
C0 = 0 ⊕ 0 ⊕ 0
C0 = 0
Stage-02:
● When C0 is fed as input to the full adder B, it activates the full adder B.
Full adder B computes the sum bit and carry bit as-
Calculation of S1–
S 1 = A 1 ⊕ B1 ⊕ C0
S1 = 0 ⊕ 1 ⊕ 0
S1 = 1
Calculation of C1–
C1 = A1B1 ⊕ B1C0 ⊕ C0A1
C1 = 0.1 ⊕ 1.0 ⊕ 0.0
C1 = 0 ⊕ 0 ⊕ 0
C1 = 0
Stage-03:
● When C1 is fed as input to the full adder C, it activates the full adder C.
Full adder C computes the sum bit and carry bit as-
Calculation of S2–
S2 = A2 ⊕ B2 ⊕ C1
S2 = 1 ⊕ 0 ⊕ 0
S2 = 1
Calculation of C2–
C2 = A2B2 ⊕ B2C1 ⊕ C1A2
C2 = 1.0 ⊕ 0.0 ⊕ 0.1
C2 = 0 ⊕ 0 ⊕ 0
C2 = 0
Stage-04:
● When C2 is fed as input to the full adder D, it activates the full adder D.
Full adder D computes the sum bit and carry bit as-
Calculation of S3–
S 3 = A 3 ⊕ B3 ⊕ C2
S3 = 0 ⊕ 1 ⊕ 0
S3 = 1
Calculation of C3–
C3 = A3B3 ⊕ B3C2 ⊕ C2A3
C3 = 0.1 ⊕ 1.0 ⊕ 0.0
C3 = 0 ⊕ 0 ⊕ 0
C3 = 0
Thus finally,
● Output Carry = C3 = 0
● Ripple Carry Adder does not allow to use all the full adders simultaneously.
● Each full adder has to necessarily wait until the carry bit becomes available from its
adjacent full adder.
5. Tristate Buffer
Introduction
Before we talk about tri-state buffers, let’s talk about an inverter. You can read about
inverters in the notes about Logic Gates. However, we’ll repeat it here for completeness.
An inverter is called a NOT gate, and it looks like:
You might think that a buffer is useless. After all, the output is exactly the same as the
input. What’s the point of such a gate? The answer is a practical issue from real circuits.
As you may know, logic gates process 0’s and 1’s. 0’s and1’s are really electric current at
certain voltages. If there isn’t enough current, it’s hard to measure the voltage. The
current can decrease if the fan out is large. Here’s an example:
The "fan out" is the number of devices that an output is attached to. Thus, the AND gate
above is attached to the inputs of four other devices. It has a fan out of 4.If the current
coming out of the AND gate is i, then assuming each of the four devices gets equal
current, then each device gets i / 4 of the current. However, if we put in a buffer:
Then the current can be "boosted" back to the original strength. Thus, a buffer (like all
logic gates) is an active device. It requires additional inputs to power the gate, and
provide it voltage and current. You might wonder "Do I really need to know this? Isn’t
this just EE stuff?" That’s true, it is. The point of the discussion was to motivate the
existence of a plain buffer. Tri-state buffer: It’s a Valve A buffer’s output is defined as
z = x. Thus, if the input, x is 0, the output, z is 0. If the input, x is 1, the output, z is 1. It’s
a common misconception to think that 0 is nothing, while 1 is something. In both cases,
they’re something. If you read the discussion in What’s a Wire, you’ll see that a wire
either transmits a 0, a 1, or "Z", which is really what’s nothing. It’s useful to think of a
wire as a pipe and 0 as "red kool aid" and 1 as "green kool aid" and "Z" as "no kool aid".
A tri-state buffer is a useful device that allows us to control when current passes through
the device, and when it doesn’t. Here are two diagrams of the tri-state buffer.
A tri-state buffer has two inputs: a data input x and a control input c. The control input
acts like a valve. When the control input is active, the output is the input. That is, it
behaves just like a normal buffer. The "valve" is open. When the control input is not
active, the output is "Z". The "valve" is open, and no electrical current flows through.
Thus, even if x is 0 or 1, that value does not flow through. Here’s a truth table describing
the behavior of a active-high tri-state buffer.
In this case, when the output is Z, that means it’s high impedance, neither 0, nor 1, i.e., no
current. As usual, the condensed truth table is more enlightening.
As you can see, when c = 1 the valve is open, and z = x. When c = 0 the valve is closed,
and z = Z (e.g., high impedance/no current).Active-low tri-state buffersSome tri-state
buffers are active low. In an active-low tri-state buffer, c = 0 turns open the valve, while c
= 1turns it off.Here’s the condensed truth table for an active-low tri-state buffer.
As you can see, when c = 0 the valve is open, and z = x. When c = 1 the valve is closed,
and z = Z (e.g., high impedance/no current). Thus, it has the opposite behavior of a tri-
state buffer.
Why Tri-State Buffers?
We’ve had a long discussion about what a tri-state buffer is, but not about what such a
device is good for.Recall (from earlier) that a common way for many devices to
communicate with one another is on a bus, andthat a bus should only have one device
writing to it, although it can have many devices reading from it.Since many devices
always produce output (such as registers) and these devices are hooked to a bus, we need
away to control what gets on the bus, and what doesn’t.A tri state buffer is good for
that.Here’s an example:
6. Fan In and Fan Out
Fan In and Fan Out are the characteristics of digital IC. Digital IC’s are complete
functional network.
Fan in:
The term fan in is defined as maximum number of inputs that a logic gate can accept. If
number of input exceeds, the output will be undefined or incorrect. It is specified by
manufacturer and is provided in the data sheet. e.g. for 2 input OR gate fan in = 2
Fan-out:
The fan out term is defined as the maximum number of inputs (load) that can be
connected to the output of a gate without degrading the normal operation. Fan Out is
calculated from the amount of current available in the output of a gate and the amount of
current needed in each input of the connecting gate. It is specified maximum load may
cause a malfunction because the circuit will not be able to supply the demand power.
Ex:If output of an X-OR gate is connected to 3 other external gate without degrading
output performance of the IC then Fan Out =3.
Multiplexer:
Multiplexer means many to one. A multiplexer (MUX) is a combinational circuit which
is often used when the information from many sources must be transmitted over long
distances and it is less expensive to multiplex data onto a single wire for transmission.
Multiplexer can be considered as multi-position or rotary switch as shown in fig. 1. There
are n – inputs and one output. The switch position is controlled by the selector lines. The
select inputs decide which input is connected to the output.
Figure 1 : Multiplexer as multi-position or rotary switch
The basic operation of multiplexer is controlled by a selector lines that routes one of
many input signals to the output. Fig.1 shows the logic symbol of general symbol of
multiplexer.
Multiplexer are also called as DATA Selector or router because it accepts several data
inputs and allows only one of them to get through to the output at a time. The basic
multiplexer has n input lines and single output line. It also has m – select or control lines.
The relation between number of select lines and number of data inputs are
2m=n
As multiplexer selects one out of many, it is often called as 2m to 1 line converter.
Types of Multiplexer
Figure-3(a) : Logic symbols of 2 to 1 and 4 to 1 multiplexers
De-multiplexer
De-multiplexer has a single input and n output lines. De-multiplexer can be visualized as
reverse multi-position switch. The select lines permit input data from single line to be
switched to any one of the many output lines as shown in fig.
Fig : Multi-position switch as De-multiplexer
Thus the de-multiplexer takes one data input source and selectively distributes it to 1 of N
output channels just like multi-position switch. It also has ‘m’ select lines for selecting
the desired output for the input data as shown in fig. The mathematical relation between
select lines and ‘n’ output are:
2m = n
As a de-multiplexer takes data from one input line and distributes over a 2 m output line,
hence it is often referred to as 1 to 2m line converter. There are four basic types de-
multiplexers: 1 to 2demultiplexer, 1 to 4 de-multiplexer, 1 to 8 de-multiplexer and 1 to 16
de-multiplexer as shown in fig. . Number of select lines decides this classification.
Fig : Types of Demux
Decoder
In digital electronics, a decoder can take the form of a multiple-input, multiple-output
logic circuit that converts coded inputs into coded outputs, where the input and output
codes are different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in
applications such as data multiplexing, 7 segment display and memory address decoding.
The example decoder circuit would be an AND gate because the output of an AND gate
is "High" (1) only when all its inputs are "High." Such output is called as "active High
output". If instead of AND gate, the NAND gate is connected the output will be "Low"
(0) only when all its inputs are "High". Such output is called as "active low output". A
slightly more complex decoder would be the n-to-2n type binary decoders. These types of
decoders are combinational circuits that convert binary information from 'n' coded inputs
to a maximum of 2n unique outputs. In case the 'n' bit coded information has unused bit
combinations, the decoder may have less than 2 n outputs. 2-to-4 decoder, 3-to-8 decoder
or 4-to-16 decoder are other examples. The input to a decoder is parallel binary number
and it is used to detect the presence of a particular binary number at the input. The output
indicates presence or absence of specific number at the decoder input.
Let us suppose that a logic network has 2 inputs S1 and S0. They will give rise to 4
states S1, S1’, S0, S0’. The truth table for this decoder is shown below:
For any input combination only one of the outputs is low and all others are high. The low
value at the output represents the state of the input.
Decoder expansion
Combine two or more small decoders with enable inputs to form a larger decoder e.g. 3-
to-8-line decoder constructed from two 2-to-4-line decoders. Decoder with enable input
can function as de-multiplexer.
3:8 decoder
It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs,
NAND gates are used. It has 3 input lines and 8 output lines. It is also called as binary to
octal decoder it takes a 3-bit binary input code and activates one of the 8(octal) outputs
corresponding to that code. The truth table is as follows:
Encoder
An encoder is a device, circuit, transducer, software program, algorithm or person that
converts information from one format or code to another. The purpose of encoder is
standardization, speed, secrecy, security, or saving space by shrinking size. Encoders are
combinational logic circuits and they are exactly opposite of decoders. They accept one
or more inputs and generate a multi bit output code.
Encoders perform exactly reverse operation than decoder. An encoder has M input and N
output lines. Out of M input lines only one is activated at a time and produces equivalent
code on output N lines. If a device output code has fewer bits than the input code has, the
device is usually called an encoder.
Octal to binary encoder
Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the
3-to-8 decoder does. At any one time, only one input line has a value of 1. The figure
below shows the truth table of an Octal-to-binary encoder.