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DIC-Lec4

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25 views29 pages

DIC-Lec4

Uploaded by

郭之一
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Integrated Circuits

CMOS Processing Technology


and Design Rules - II
Advisor: Prof. Yi-Chung Wu (yicwu@nycu.edu.tw)
Credited by: Shyh-Jye Jerry Jou
Institute of Electronics, National Yang Ming Chiao Tung University
Layout Design Rules
• The rules provide a necessary communication link between circuit designer
and process engineer during the manufacturing phase
• Design Rules → not correct or incorrect fabrication, but a tolerance that
ensures high probability of correct fabrication
• More aggressive rules → greater improvements in circuit performance
– May be at the expense of cost (due to low yield)
• One May find that a layout that violates design rules may still function
correctly and vice versa.

2
Origin of Rules
• The Rules are written in consideration of
– Electrical characteristics
• Punch-through break, latch-up, electron migration, antenna effect
– Mask line width variation
– Lithographic variation
– Mask alignment
– Exposure time
– Resistance variation: etching time variation, process variation

3
Example of Variation

Example of mask line width variation, etching process variation and variation due to photolithograph 4
Example of Misalignment

Example of misalignment of the metal, poly and contact mask

5
Types of Design Rules
• Micro Rule: Normal style for industry
• Lambda (l) Rule
– All the rules are expressed in terms of l parameter
– Usually, l = 0.5 * minimum feature size of the process
– Advantages
• Simple: single page rule
• Portable: can be used by many manufactures
• Scalable
– Disadvantages
• Less dense layout (looser)
• Degradation in circuit performance
• Some rules cannot be scalable as minimum feature size reduced
• There is minimum grid dimension in terms of the design rules
6
Terminology about design rules
• Design rules define:
– Widths
– Spacing
– Extensions
– Enclosure
– overlaps

7
Example of Micro Rule (65nm)

8
Example of TSMC 0.18/0.13um CMOS Logic Tech.
• TSMC 0.18um Mixed Signal 1P6M Salicide 1.8V/3.3V
• TSMC 0.13um Mixed Signal 1P8M Salicide 1.2V/2.5V
Parameter Spec.: 0.18/0.13 Unit
VT_N 0.42/0.34 V
ISAT_N 213/117 A
Gate Oxide_N 0.0041/0.0028 um
VT_P -0.50/-0.36 V
ISAT_P 73/38 A
Gate Oxide_P 0.0041/0.0029 um
Metal I 1.0/1.0 mA/um
Metal II, III, IV, V 1.6,1.6,1.6,1.6,1.6 mA/um
CO/via1,2,3 1.06/0.6,0.6,0.96 mA per
9
Layout Design Rules

10
11
Symbolic Layout (Stick Diagram)
• Graphical symbols are placed together relative to each other than in an
absolute manner → diagrams reflects the topology of the actual layout in
silicon → stick layout and compaction

Horizontal N-diffusion and P-diffusion strips.


Vertical polysilicon gates
Metal 1 VDD rail at top and Metal 1 GND rail at bottom 12
CMOS Summary

• Scale down limitation of Planar MOSFET (STI: Shallow Trench Isolation)

13
FinFET (Tri-Gate Transistor)
• Main challenge
– Minimization of leakage current (subthreshold and gate leakage)
– Reduction in the device-to-device variability to increase yield
– Increase the equivalent channel width by 3D structure

14
Case of Four-Fin FinFET
• Effective gate width (W) = n(2h+Tsi), where n is the number of fins
• Increasing h will have higher on current
• Wider transistors with higher on-current are obtained by using multiple fins
• Only n can be determined by designer
• In the 7nm (l=4nm) tech., h=35nm, Tsi=4nm, and pitch p is 24nm (6 l)
– One fin has an equivalent width of 74nm

15
Comparison of TSMC 16nm FinFET and 28m Planar
• At the same speed, the power consumption is reduced by 55%, and the
speed has a gain of 35% at the same power consumption
• DIBL and subthreshold Slope (SS) have made great progress, reaching
40mV/V and 70mV/dec. NBTI (negative-bias temperature instability) is
worse
• In terms of analog and RF characteristics
– it provides up to 3.1x the intrinsic gain
– 1.9x the current efficient

16
How FinFETs work

17
FinFET Advantages & Considerations

18
FinFET Device Complexity

19
Layout of a 2-fin Inverter, 2-fin NOR3 and 4-fin AND3

20
Standard Cell Architecture and Cross-Section

21
Standard Cell Library Height Comparison

22
Key Parameters of the 7nm Process
• Drawn gate length is 2l = 8nm
• Fin width is l = 4nm
• The lower metal pitch = 24nm

23
Key Parameters of the 7nm Process
• The IDsat current for p-channel devices is almost similar to the n-channel
device
• The subthreshold slope (SS) is around 70 mV/decade when measured from
10-7 A to 10-6 A.

24
Model Composition

25
GAA FET and MBCFET
• GAA: Gate-All-Around
• Multi-Bridge Channel

26
3D-stacked Structure
• 3D-stacked CMOS
• NMOS on top

27
Memory Density Comparison

28
Memory Density Comparison

29

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