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Scheme of Valuation/Answer Key
(Scheme of evaluation (marks in brackets) and answers of problems/key)
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
FIFTH SEMESTER B.TECH DEGREE EXAMINATION, DECEMBER 2021
Course Code: ECT 393

Course Name: FPGA BASED SYSTEM DESIGN

Max. Marks: 100 Duration: 3 Hours

PART A
(Answer all questions; each question carries 3 marks) Marks

1 Explanation: Minimum three points (3 marks) 3

Behavioral models in Verilog contain procedural statements, which control the
simulation and manipulate variables of the data types. These all statements are
contained within the proceduresThis initial statement is containing a begin-end block
(also called a sequential block) of statements.
Behavioral modelling is an approach used by companies to better understand and
predict consumer actions. Behavioral modelling uses available consumer and business
spending data to estimate future behavior in specific circumstances.
Behavioral models in Verilog contain procedural statements, which control the
simulation and manipulate variables of the data types. These all statements are
contained within the procedures. Each of the procedure has an activity flow associated
with it.
During simulation of behavioral model, all the flows defined by the ‘always’ and
‘initial’ statements start together at simulation time ‘zero’. The initial statements are
executed once, and the always statements are executed repetitively.
In this model, the register variables a and b are initialized to binary 1 and 0 respectively
at simulation time ‘zero’. The initial statement is then completed and is not executed
again during that simulation run. This initial statement is containing a begin-end block
(also called a sequential block) of statements. In this begin-end type block, a is
initialized first followed by b.
2 Explanation: Minimum three points (3 marks) 3
State machine designs are widely used for sequential control logic, which forms the
core of many digital systems. Typically, the details of control logic are the last to be

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settled in the design cycle, since they are continuously affected by changing system
requirements and feature enhancements.
State machines are required in a variety of applications covering a broad range of
performance and complexity; low-level controls of microprocessor-toVLSI-peripheral
interfaces, bus arbitration and timing generation in conventional microprocessors,
custom bit-slice microprocessors, data encryption and decryption.
A state machine is a programming architecture that allows dynamic flow to states
depending on values from previous states or user inputs. This architecture is suitable for
applications that can be described as a combination of: States. Decision-making logic
that determines when to move to a particular state.

3 Explanation: Minimum three points (3 marks) 3

• The programming of FPGA requires knowledge of VHDL/Verilog
programming languages as well as digital system fundamentals.
• The programming is not as simple as C programming used in processor based
hardware. Moreover engineers need to learn use of simulation tools.
• The power consumption is more and programmers do not have any control on
power optimization in FPGA. No such issues in ASIC.
• Once any particular FPGA is selected and used in the design, programmers need
to make use of resources available on the FPGA IC. This will limit the design
size and features. TO avoid such situation, appropriate FPGA need to be chosen
at the beginning itself.

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4 Explanation: Minimum three points (3 marks)

5 Explanation (3 marks) 3
A configurable logic block (CLB) is the basic repeating logic resource on an FPGA.
When linked together by routing resources, the components in CLBs execute complex
logic functions, implement memory functions, and synchronize code on the FPGA.
Each CLB contains two basic structures called Slice; each basic Slice contains 4 look-
up tables, 4 storage units, a wide function multiplexer, and carry logic; this basic
structure (Slice) is called SLICEL. Besides, some Slice also includes using RAM to
store data and the function of shifting using 32-bit registers.
6 Explain any three points from coarse and fine grained FPGA (1 mark each point) 3
Coarse-grained - larger components than fine-grained, large subcomponents. Simply
wraps one or more fine-grained services together into a more coarse--grained
operation.Coarse-grained materials or systems have fewer, larger discrete components
than fine-grained materials or systems.A coarse-grained description of a system regards
large subcomponents.

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Fine-grained - smaller components of which the larger ones are composed, lower level
service.A fine-grained description regards smaller components of which the larger ones
are composed.

7 Explanation (3 marks) 3
Place and route is a stage in the design of printed circuit boards, integrated circuits, and
field-programmable gate arrays. As implied by the name, it is composed of two steps,
placement and routing. The first step, placement, involves deciding where to place all
electronic components, circuitry, and logic elements in a generally limited amount of
space. This is followed by routing, which decides the exact design of all the wires
needed to connect the placed components. This step must implement all the desired
connections while following the rules and limitations of the manufacturing process.
FPGAs, during which logic elements are placed and interconnected on the grid of the
FPGA.
The process of placing and routing for an FPGA is generally not performed by a person,
but uses a tool provided by the FPGA Vendor or another software manufacturer. The
need for software tools is because of the complexity of the circuitry within the FPGA
and the function the designer wishes to perform. FPGA designs are described using
logic diagrams containing digital logic and hardware description languages such as

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VHDL and Verilog. These will then be put through an automated place-and-route
procedure to generate a pinout, which will be used to interface with the parts outside of
the FPGA
8 Explanation (3 marks)
Benefits of FPGAs in DSP Designs
FPGA devices provide a reconfigurable DSP solution for various DSP applications.
FPGA devices incorporate a variety of embedded features such as embedded
processors, DSP blocks, and memory blocks. These device features provide very high
DSP capability in FPGAs compared to DSP processors. Using FPGAs, DSP designers
can customize their hardware for optimal implementation of their applications.
FPGA devices provide a reconfigurable DSP solution for various DSP applications.
FPGA devices incorporate a variety of embedded features such as embedded
processors, DSP blocks, and memory blocks. These device features provide very high
DSP capability in FPGAs compared to DSP processors.
DSP designers had to implement their systems in FPGAs using the hardware flow based
on a HDL language such as Verilog HDL and VHDL.
9 Explanation (3 marks) 3

10 Explain any three points from combinational & sequential circuit (1 mark each point) 3
Combinational circuits are defined as the time independent circuits which do not
depends upon previous inputs to generate any output are termed as combinational
circuits. Sequential circuits are those which are dependent on clock cycles and depends
on present as well as past inputs to generate any output.
Combinational Circuit – Examples – Encoder, Decoder, Multiplexer, Demultiplexer
1. In this output depends only upon present input.
2. Speed is fast.
3. It is designed easy.
4. There is no feedback between input and output.

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5. This is time independent.

Sequential logic circuit is a form of the binary circuit; its design employs one or more
inputs and one or more outputs, whose states are related to some definite rules that
depend on previous states. ... Examples of such circuits include clocks, flip-flops, bi-
stables, counters, memories, and registers
Sequential Circuit – Examples – Flip-flops, Counters
1. In this output depends upon present as well as past input.
2. Speed is slow.
3. It is designed tough as compared to combinational circuits.
4. There exists a feedback path between input and output.
5. This is time dependent.
PART B
(Answer one full question from each module, each question carries 14 marks)

Module -1

11 a) Program code(3 marks), Truth Table (2 marks), Schematic (3 marks) 8

(Truth table of 4×1 Mux)

The final code for 4×1 MUX in behavioral modeling is as follows:
module m41 ( a, b, c, d, s0, s1, out);
input wire a, b, c, d;
input wire s0, s1;
output reg out;
always @ (a or b or c or d or s0, s1)
begin
case (s0 | s1)
2'b00 : out <= a;

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2'b01 : out <= b;

2'b10 : out <= c;
2'b11 : out <= d;
endcase
end
endmodule

(schematic behavioral modelling)

b) Test bench code(6 marks) 6
A testbench is an HDL code that allows you to provide a set of stimuli input to test the
functionality and wide-range of plausible inputs for support to a system.
The name of the module: top
Output variable: out
Input variables: a, b, c, d
Select lines: s0, s1
Name of the module instance: name
module top;

wire out;
reg a;
reg b;
reg c;
reg d;
reg s0, s1;

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m41 name(.out(out), .a(a), .b(b), .c(c), .d(d), .s0(s0), .s1(s1));

initial
begin
a=1'b0; b=1'b0; c=1'b0; d=1'b0;
s0=1'b0; s1=1'b0;
#500 $finish;
end
always #40 a=~a;
always #20 b=~b;
always #10 c=~c;
always #5 d=~d;
always #80 s0=~s0;
always #160 s1=~s1;
always@(a or b or c or d or s0 or s1)
$monitor("At time = %t, Output = %d", $time, out);
endmodule;

12 a) Program code(3 marks), Truth Table (2 marks), Schematic (3 marks) 8

(Truth table for JK Flip-flop)

The final code for JK Flip flop in behavioral modelling is as follows:

module jkff_behave(clk,j,knq,qbar);
input clk,j,k;
output reg q,qbar;

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always@(posedge clk)
begin
if(k = 0)
begin
q <= 0;
qbar <= 1;
end
always@(posedge clk)
begin
if(k = 0)
begin
q <= 0;
qbar <= 1;
end
else if(j = 1)
begin
q <= 0;
qbar <= 0;
end
else if(j = 0 & k = 0)
begin
q <= q;
qbar <= qbar;
end
else if(j = 1 & k = 1)
begin
q <= ~q;
qbar <= ~qbar;
end
end
endmodule

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(RTL schematic of JK flip flop)

b) Explanation (6 marks) 6
The behavioral modelling style is a higher abstraction in the entire saga of Verilog
programming. By higher abstraction, what is meant is that the designer only needs to
know the algorithm of the circuit to code it. Hence, this modelling style is also
occasionally referred to as an algorithmic modelling style. The designer does not need
to know the gate-level design of the circuit.
Behavioral modelling contains procedural statements that control the simulation and
manipulate the data types of the variables involved. There is a ‘procedure’ under which
these statements are executed, and this procedure contains a ‘sensitivity list’ that
controls the execution of the procedure.
A procedure in Verilog corresponds to the same context that a function in C
programming does. It is a particular block of statements called procedural statements. If
we compare it with the high-level language, it comes out to be that the function
arguments and parameters in a language like C, Python are the same as that of the
procedural statements.
There are two kinds of procedural assignment statements:
Blocking statements
Non-blocking statements
Blocking statements
Blocking assignments are executed in the order they are coded. Hence, they are
sequential. Since they block the execution of the next statement, until the current
statement is executed, they are called blocking assignments. The assignment is made
with the “=” symbol.

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Example:
// Blocking Assignment

initial
begin
// here, the begin-end clause is used because there are more than one statements in the
initial block
#10 a = 0; // 10 time units delay has been given a with value 0
#11 a = 1; // 11 time units delay to a variable with value 1
#12 a = 0; // 12 time units delay to a with value 0
#13 a = 1; // 13 time units delay to a with value 1
end
Non-blocking statements
Non-blocking assignments are executed in parallel. Since the execution of the next
statement is not blocked due to the execution of the current statement, they are called
non-blocking statements. Assignments are made with the “<=” symbol.

Example:
// Non-blocking Assignment

initial
begin
// These statements will get executed without the intervention of the other statements
// In other words, their execution will not be blocked by the other ones
#10 b <= 0; // A delay of 10 time units has been given to the variable b with 0
value.
#11 b <= 1; // 11 time units delay to b with value 1
#12 b <= 0; // 12 time units delay to b with value 0
#13 b <= 1; // 13 time units delay to b with value 1
end

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Module -2
13 a) Explanation (3 marks) , Block Diagram(2 marks) 5
Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized"
by making/ breaking connections among the gates. General purpose logic building
blocks. Each of the AND gates can be programmed to generate a product term of the
input variables and does not generate all the minterms as in the ROM.The AND & OR
gates inside the PLA are initially fabricated with the links (fuses) among them. The
specific Boolean functions are implemented in sum of products form by opening
appropriate links and leaving the desired connections.
It consists of n inputs, m outputs, and k product terms. The product terms constitute a
group of k AND gates each of 2n inputs. Links are inserted between all n inputs and
their complement values to each of the AND gates. Links are also provided between the
outputs of the AND gates and the inputs of the OR gates.

b) Design (3 marks), Truth Table (2 marks), Circuit implementation (4 marks) 9

Solution: Truth table for Boolean functions A, B, C and D can be drawn as:

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Solving K-Map to get the required Boolean expressions:

A PLA program table can be also drawn representing the terms in the Boolean
expression as:

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The logic diagram of the combinational circuit implemented using PLA can be drawn
as:

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14 a) Comparison(2 marks each) 6

b) Design (3 marks), K-map (2 marks), Circuit implementation (3 marks) 8

Karnaugh maps for the above functions are drawn in Figures

To use the PAL device as illustrated from the above expressions, it may be noted that a
problem occurs that the specified PAL device has at the most three product terms
associated with one OR gate, whereas one of the given functions F1 has four product
terms. However, realization of the functions are achievable with the specified PAL
device by the following method.
Now there are three functions each of which contains no more than three product terms
and these can be realizable by the specified PAL. The connection diagram of PAL is
illustrated in Figure

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Here, one sub function F3 has been generated with two product terms, and this sub-
function is connected to one of the inputs to realize the final function F1. To realize F2,
only two terms need to be generated. Since a three-input OR gate is used, the input must
be kept at logic 0, so as not to affect the F2 output.

Module -3
15 a) Explanation (7 marks) , Block Diagram(7 marks) 14
Internal Architecture of FPGA
It consists of three main parts: Configurable Logic Blocks — which implement logic
functions. Programmable Interconnects — which implement routing. Programmable
I/O Blocks — which connect with external components.

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(The basic architecture of an FPGA)

16 a) Explanation (3 marks) , Block Diagram(4 marks) 7
Logic blocks are the most common FPGA architecture, and are usually laid out within a
logic block array. Logic blocks require I/O pads (to interface with external signals), and
routing channels (to interconnect logic blocks).A logic block consists of a few logic
cells (each cell is called an adaptive logic module (ALM), a logic element (LE), slice,
etc.). A typical cell consists of a 4-input LUT, a full adder (FA), and a D-type flip-flop
(DFF), as shown to the right. The LUTs are in this figure split into two 3-input LUTs.
In normal mode those are combined into a 4-input LUT through the left mux. In
arithmetic mode, their outputs are fed to the FA. The selection of mode is programmed
into the middle multiplexer. The output can be either synchronous or asynchronous,
depending on the programming of the mux.

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Logic blocks typically contain a few ALMs/LEs/slices. ALMs and slices usually
contain 2 or 4 structures.

(Logic block pin locations)

Each input is accessible from one side of the logic block, while the output pin can
connect to routing wires in both the channel to the right and the channel below the logic
block.
Each logic block output pin can connect to any of the wiring segments in the channels
adjacent to it.
Similarly, an I/O pad can connect to any one of the wiring segments in the channel
adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the
W wires (where W is the channel width) in the horizontal channel immediately below it.
b) Explanation (3 marks) , Block Diagram(4 marks) 7
IOB (Input Output Block) is a programmable input and output unit, which is the
interface between fpga and external circuits. Used to complete the driving and matching

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requirements for input/output signals under different electrical characteristics.

The I/O in the FPGA is classified into groups, and each group can independently
support different I/O standards. Through the flexible configuration of the software, it
can adapt to different electrical standards and I/O physical characteristics, can adjust the
size of the drive current, and can change the up and down resistance.

Module -4
17 a) Explanation (10 marks) 10
Goal: Determine which logic block within an FPGA should implement each of the
logic blocks required by the circuit.
Objective: Minimize the required wiring (wire-length driven placement).
Balance the wiring density across the FPGA (routability-driven placement).
Maximize circuit speed (timing-driven placement).
3 major classes of placers:
– min-cut (partitioning-based) placers
– analytic placers
– simulated annealing based placers.
Placement algorithms determine which logic block within an FPGA should implement
the corresponding logic block (instance) required by the circuit. The optimization goals
consist in placing connected logic blocks close together to minimize the required wiring
(wire length-driven placement), and sometimes to place blocks to balance the wiring

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density across the FPGA (routability-driven placement) or to maximize circuit speed

(timing-driven placement).

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b) Explanation (4 marks) 4

18 a) Explanation (4 marks), Diagram(4 marks) 8

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{*Can consider - switch Matrix,lut ,

multiplexers,tristate buffer,PLA s etc. for the above
question 18 .a}
Explanation (4 marks), Diagram(4 marks).

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b) Explanation (6 marks) 6
Routing architecture comprises of programmable switches and wires. Routing provides
connection between I/O blocks and logic blocks, and between one logic block and
another logic block.The type of routing architecture decides area consumed by routing
and density of logic blocks.Routing technique used in an FPGA largely decides the
amount of area used by wire segments and programmable switches as compared to area
consumed by logic blocks.
A wire segment can be described as two end points of an interconnect with no
programmable switch between them. A sequence of one or more wire segments in an
FPGA can be termed as a track.Typically an FPGA has logic blocks, interconnects and
Input/Output blocks. Input Output blocks lie in the periphery of logic blocks and
interconnect. Wire segments connect I/O blocks to wire segments through connection
blocks. Connection blocks are connected to logic blocks, depending on the design
requirement one logic block is connected to another and so on.
Xilinx Routing architecture
In Xilinx routing, connections are made from logic block into the channel through a
connection block. As SRAM technology is used to implement Lookup Tables,
connection sites are large. A logic block is surrounded by connection blocks on all four
sides. They connect logic block pins to wire segments. Pass transistors are used to
implement connection for output pins, while use of multiplexers for input pins saves the
number of SRAM cells required per pin. The logic block pins connecting to connection
blocks can then be connected to any number of wire segments through switching
blocks.

Module -5

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19 a) LUT Explanation (2 marks)Design and implement (5 marks) 7

The LUT in an FPGA holds a custom truth table, which is loaded when the chip is
powered up. Think of the LUT as a small scratchpad RAM. The LUT inputs act as the
address lines for a corresponding one-bit-wide RAM cell.

b) Explanation (2 marks) Design and implement (5 marks) 7

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20 a) Explanation (7 marks) , Block Diagram(7 marks) 14

Xilinx Virtex IOB

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Xilinx Virtex CLB

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*********

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