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14 views

Chapter_3

Uploaded by

onurkaraduman.dsm
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ELECTRONICS II

Dr. Aslı TAŞÇI

CHAPTER 3 - REVIEW

THE FIELD EFFECT TRANSISTOR

Contents are created from Microelectronics Circuit Analysis and Design by Donald A. Neamen
In this chapter, we will:
Study and understand the operation and characteristics of the various types of MOSFETs.

Understand and become familiar with the dc analysis and design techniques of MOSFET circuits.

Analyze the dc biasing of multistage or multitransistor circuits.


Basic Structure of MOS Capacitor
Basic Transistor Operation

Before electron inversion After electron inversion


layer is formed layer is formed
Basic Transistor Operation
Current Versus Voltage Characteristics:
Enhancement-Mode nMOSFET
Family of iD Versus vDS Curves:
Enhancement-Mode nMOSFET
Symbols for n-Channel Enhancement-Mode
MOSFET
n-Channel Depletion-Mode MOSFET
Family of iD Versus vDS Curves:
Depletion-Mode nMOSFET
Summary of I-V Relationships
Region NMOS

Nonsaturation vDS<vDS(sat)

Saturation vDS>vDS(sat)

Transition Pt. vDS(sat) = vGS - VTN


Enhancement Mode VTN > 0V
Depletion Mode VTN < 0V
p-Channel Enhancement-Mode MOSFET
Symbols for p-Channel Enhancement-Mode
MOSFET
p-Channel Depletion-Mode
MOSFET
Summary of I-V Relationships

Region PMOS

vSD<vSD(sat)
Nonsaturation

vSD>vSD(sat)
Saturation

Transition Pt. vSD(sat) = vSG + VTN

Enhancement Mode VTP < 0V

Depletion Mode VTP > 0V


Cross-Section of nMOSFET and pMOSFET

Both transistors are used in the fabrication of CMOS circuitry


NMOS Common-Source Circuit
Load Line and Modes of Operation:
NMOS Common-Source Circuit
PMOS Common-Source Circuit
DC equivalent circuit
Problem-Solving Technique:
NMOSFET DC Analysis
1. Assume the transistor is in saturation.
a. VGS > VTN, ID > 0, & VDS ≥ VDS(sat)

2. Analyze circuit using saturation I-V relations.


3. Evaluate resulting bias condition of transistor.
a. If VGS < VTN, transistor is likely in cutoff
b. If VDS < VDS(sat), transistor is likely in nonsaturation region

4. If initial assumption is proven incorrect, make new assumption and repeat Steps 2 and 3.
Ex.3.3: NMOS enhancement mode DC
analysis
Calculate ID and VDS for
the circuit parameters given below;

R1 = 30 kΩ,
R2 = 20 kΩ,
RD = 20 kΩ,
VDD = 5 V,
VTN = 1 V,
Kn = 0.1 mA/V2 .
Ex.3.4: PMOS enhancement mode DC
analysis

Calculate ID and VSD for


the circuit parameters given below;

R1 = R2 = 50 kΩ,
RD = 7.5 kΩ,
VDD = 5 V,
VTP = -0.8 V,
Kp = 0.2 mA/V2 .
Two-Input NMOS NOR Logic Gate

V1 (V) V2 (V) VO (V)


0 0 High
5 0 Low
0 5 Low
5 5 Low
MOS Small-Signal Amplifier
2-Stage Cascade Amplifier

Source follower

Common-source
NMOS
Cascode
Circuit
Design example 3.17

Transistor parameters:
Kn1 = 500 µA/V2
Kn2 = 200 µA/V2
VTN1 =VTN2 = 1.2 V
λ1 = λ2 = 0

Design the circuit such that


IDQ1 = 0.2 mA
IDQ2 = 0.5 mA
VDSQ1 = VDSQ2 = 6 V
Ri = 100 kΩ and Rsi = 4 kΩ
Design example 3.18

Transistor parameters:
Kn1 = Kn2 = 0.8 mA/V2
VTN1 =VTN2 = 1.2 V
λ1 = λ2 = 0
Let
R1 + R2 + R3 = 300 kΩ
RS = 10 kΩ
Design the circuit such that
IDQ = 0.4 mA
VDSQ1 = VDSQ2 = 2.5 V

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