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Analog Circuits (Formula Notes/Short Notes)

𝐸𝐸G/si =1.21− 3.6 × 10−4 .T ev

• Energy gap 𝐸𝐸G/Ge =0.785− 2.23 × 10−4 .T ev
� Energy gap depending on temperature
𝑁𝑁 𝑁𝑁
• EF = EC - KT ln�𝑁𝑁𝐶𝐶 � = Ev + KT ln �𝑁𝑁𝑣𝑣 �
𝐷𝐷 𝐴𝐴
• No. of electrons n = Nc e−(Ec−Ef)/RT (KT in ev)
• No. of holes p = Nv e−(Ef−Ev )/RT
• Mass action law np = n2i = Nc Nv e−EG/KT
• Drift velocity 𝑣𝑣d = μE (for si 𝑣𝑣d ≤ 107 cm/sec)
B.I
• Hall voltage 𝑣𝑣H = . Hall coefficient R H = 1/ρ . ρ → charge density = qN0 = ne …
we
• Conductivity σ = ρμ ; μ = σR H .
q q
• Max value of electric field @ junction E0 = - Nd . nn0 = - NA . np0 .
ϵsi ϵsi
• Charge storage @ junction Q + = - Q − = qA xn0 ND = qA xp0 NA

dp dn
• Diffusion current densities Jp = - q Dp Jn = - q Dn
dx dx
• Drift current Densities = q(p µp + nµn )E
• µp , µn decrease with increasing doping concentration .
Dn Dp
• = = KT/q ≈ 25 mv @ 300 K
µn µp
• Carrier concentration in N-type silicon nn0 = ND ; pn0 = n2i / ND
• Carrier concentration in P-type silicon pp0 = NA ; np0 = ni2 / NA
𝑁𝑁𝐴𝐴 𝑁𝑁𝐷𝐷
• Junction built in voltage V0 = VT ln � 𝑛𝑛𝑖𝑖2
�
2εs 1 1
• Width of Depletion region Wdep = xp + xn = � �
q NA
+ � (V0 + VR )
ND
2𝜀𝜀𝑓𝑓𝑓𝑓
*� = 12.93𝑚𝑚 𝑓𝑓𝑓𝑓𝑓𝑓 𝑠𝑠𝑠𝑠�
𝑞𝑞
xn N
• = A
xp ND
q.NA ND
• Charge stored in depletion region qJ = NA +ND
. A . Wdep
εs A εs A
• Depletion capacitance Cj = ; Cj0 =
Wdep Wdep / VR =0

V m
Cj = Cj0 /�1 + VR �
0
Cj = 2Cj0 (for forward Bias)
Dp
• Forward current I = Ip + In ; Ip = Aq n2i
�𝑒𝑒 𝑉𝑉/𝑉𝑉𝑇𝑇 − 1�
Lp ND
D
In = Aq n2i L Nn �𝑒𝑒 𝑉𝑉/𝑉𝑉𝑇𝑇 − 1�
n A
Dp D
• Saturation Current Is = Aq n2i �L N + L Nn �
p D n A
• Minority carrier life time τp = L2p / Dp ; τn = L2n / Dn

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• Minority carrier charge storage Qp = τp Ip , Q n = τp In

Q = Q p + Q n = τT I τT = mean transist time
𝜏𝜏
• Diffusion capacitance Cd = �𝜂𝜂𝑉𝑉𝑇𝑇 � I = τ.g ⇒ Cd ∝ I.
𝑇𝑇
τ→ carrier life time , g = conductance = I / 𝜂𝜂𝑉𝑉𝑇𝑇
• I02 = 2(T2 −T1 )/10 I01
• Junction Barrier Voltage Vj = VB = Vr (open condition)
= Vr - V (forward Bias)
= Vr + V (Reverse Bias)
1
• Probability of filled states above ‘E’ f(E) = (E−Ef )/KT 1+e
• Drift velocity of e− 𝑣𝑣d ≤ 107 cm/sec
d2 V −ρv −nq dv −nqx
• Poisson equation = = ⇒ =E=
dx2 ϵ ϵ dx ϵ

Transistor :-
• IE = IDE + InE
• IC = ICo – α IE → Active region
• IC = – α IE + ICo (1- eVC /VT )

Common Emitter :-
α
• IC = (1+ β) ICo + βIB β=
1−α
I
• Co
ICEO = 1−α → Collector current when base open
• ICBO → Collector current when IE = 0 ICBO > ICo .
0 V
• VBE,sat or VBC,sat → - 2.5 mv / C ; VCE,sat → BE,sat
10
= - 0.25 mv /0 C
IC − ICBo
• Large signal Current gain β = IB + ICBo
IC
• D.C current gain βdc = = hFE
IB
• (βdc = hFE ) ≈ β when IB > ICBo
∂I hFE
• Small signal current gain β′ = ∂IC � = hfe = ∂h
R VCE 1−(ICBo + IB ) FE
∂IC
βactive
• Over drive factor = ∵ IC sat = βforced IB sat
βforced →under saturation

Conversion formula :-
CC ↔ CE
• hic = hie ; hrc = 1 ; hfc = - (1+ hfe ) ; hoc = hoe

CB ↔ CE
h h h −hfe hoe
• hib = ie ; hib = ie oe - hre ; hfb = ; hob =
1+hfe 1+hfe 1+hfe 1+hfe

CE parameters in terms of CB can be obtained by interchanging B & E .

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Specifications of An amplifier :-

−hf Av .Zi AI.ZL AIs.ZL

• AI = Zi = hi + hr AI ZL Avs = = =
1+h0 ZL Zi +Rs Zi +Rs Rs

AI ZL hf hr Av .Rs Avs .Rs

AV = Y0 = ho - AIs = =
Zi hi + Rs Zi +Rs ZL

Choice of Transistor Configuration :-

• For intermediate stages CC can’t be used as AV < 1
• CE can be used as intermediate stage
• CC can be used as o/p stage as it has low o/p impedance
• CC/CB can be used as i/p stage because of i/p considerations.

Stability & Biasing :- ( Should be as min as possible)

∆IC ∆IC ∆IC

• For S = � S′ = � S ′′ = �
∆ICo V ∆VBE I ∆β V
B0,β C0,β BE,ICo

∆IC = S. ∆ICo + S ′ ∆VBE + S ′′ ∆β

1+β
• For fixed bias S = dI =1+β
1−β B
dIC

1+β 1+β
• Collector to Base bias S = RC 0 < s < 1+ β = RC + RE
1+β 1+β� �
RC +RB RC + RE + RB

1+β Rth
• Self bias S = RE ≈ 1+ Re
βR E > 10 R 2
1+β
RE +Rth

Vcc Rth V R
• R1 = Vth
; R 2 = V cc−Vth
cc th

VCC
• For thermal stability [ Vcc - 2Ic (R C + R E )] [ 0.07 Ico . S] < 1/θ ; VCE < 2

Hybrid –pi(π)- Model :-

g m = |IC | / VT

rb′ e = hfe / g m
rb′ b = hie - rb′ e
rb′ c = rb′ e / hre
g ce = hoe - (1+ hfe ) g b′ c

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¾ 3 Configurations are used on BJT, CE, CB & CC

¾
¾ Common Emitter, VI characteristics

IC
β = VCE
IB

ΔVBE ΔV
¾ Ri = hie = = β re ; rce = r0 = ce
ΔI B ΔI c

AMPLIFIER COMPARISON

COMPARISON
CB CE CF

BE BC
Ri LOW MED HIGH

SATURATION f/b f/b

AI AI β β +1
ACTIVE f/b r/b
AV High High <1

CUT OFF r/b r/b

Ro High High low

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For CE :-
g ′ gm
• fβ = 2π(Cb +e C =
e c) hfe 2π(Ce + Cc )

1 gb′e
• fT = hfe fβ ; fH = = C = Ce + Cc (1 + gm RL )
2π rb′e C 2πC
fT = S.C current gain Bandwidth product
fH = Upper cutoff frequency

For CC :-
1+gm RL gm fT Ce gm + gb′e
• fH = ≈ = =
2πCL RL 2πCL CL 2π(CL + Ce )

For CB:-
1+ hfe
• fα = 2πr = (1 + hfe ) fβ = (1 + β) fβ
b′ e (CC + Ce )

β
• fT = f fα > fT > fβ
1+β α

Ebress moll model :-

IC = - αN IE + ICo (1- eV/VT )

IE = - αI IC + IEo (1- eV/VT )

αI ICo = αN IEo

Multistage Amplifiers :-
fL
• fH * = fH √21/n − 1 ; fL∗ =
�21/n −1
0.35 0.35
• Rise time t r = =
fH B.W
• t ∗r = 1.1 2 2
�t r1 + t r2 + ⋯

• fL∗ = 1.1 �fL21 + fL22 + ⋯

1 1 1
• = 1.1 � 2 + +⋯
f∗H f H1 f2H2

Differential Amplifier :-

• Zi = hie + (1 + hfe ) 2R e = 2 hfe R e ≈ 2βR e

α0 |IEE | I
• gm = = 4VC = g m of BJT/4 α0 → DC value of α
4VT T

h R
• CMRR = R fe+he ; R e ↑ , → Zi ↑ , Ad ↑ & CMRR ↑
s ie

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• AI = (1 + β1 ) (1 + β2 ) ; Av ≈ 1 ( < 1)

(1+hfe )2 Re2
• Zi = Ω [ if Q1 & Q 2 have same type ] = AI R e2
1+hfe hoc Re2

Rs 2h
• Ro = + 1+hie
(1+hfe )2 fe

• g m = (1 + β2 ) g m1

Tuned Amplifiers : (Parallel Resonant ckts used ) :

1
• f0 = 2π√LC Q → ‘Q’ factor of resonant ckt which is very high

• B.W = f0 /Q

∆BW
• fL = f 0 -
2
∆BW
• fH = f0 +
2
• For double tuned amplifier 2 tank circuits with same f0 used . f0 = �fL fH .

FIELD EFFECT TRANSISTOR, FET is Unipolar Device

Construction n-Channel p-Channel

¾ S=Source, G=Gate, D=Drain

¾ GS Junction in Reverse Bias Always
¾ Vgs Controls Gate Width

¾ VI CHARACTERSTICS

Transfer Characteristics Circuit Forward Characteristics

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¾ Shockley Equation
2
⎛ Vgs ⎞ ⎛ V ⎞
¾ I d = I dss ⎜ 1− ⎟⎟ , g m = g m 0 ⎜1− gs ⎟⎟
⎜ V ⎜ V
⎝ p ⎠ ⎝ p ⎠

MOSFET (Metal Oxide Semiconductor FET, IGFET)

Depletion Type Mosfet Symbols Enhancement Mosfet

¾ Depletion Type MOSFET can work width Vgs > 0 and Vgs < 0

¾ Enhancement MOSFET operates with, Vgs > Vt , Vt = Threshold Voltage

• NMOSFET formed in p-substrate

• If VGS ≥ Vt channel will be induced & iD (Drain → source )
• Vt → +ve for NMOS
• iD ∝ (VGS - Vt ) for small VDS

• VDS ↑ → channel width @ drain reduces .

VDS = VGS - Vt channel width ≈ 0 → pinch off further increase no effect

• For every VGS > Vt there will be VDS,sat

2 1 𝑊𝑊
• iD = K ′n [ (VGS - Vt ) VDS - VDS ] � � → triode region ( VDS < VGS - Vt )
2 𝐿𝐿

K ′n = µn Cox

1 𝑊𝑊 2
• iD = K ′n � � [ VDS ] → saturation
2 𝐿𝐿
1
• rDS = 𝑊𝑊 → Drain to source resistance in triode region
K′n � �(VGS − Vt )
𝐿𝐿

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PMOS :-

• Device operates in similar manner except VGS , VDS, Vt are –ve

• iD enters @ source terminal & leaves through Drain .

VGS ≤ Vt → induced channel VDS ≥ VGS - Vt → Continuous channel

𝑊𝑊 2 1
iD = K ′p � � [(VGS − Vt )2 - VDS ] K ′p = µp Cox
𝐿𝐿 2

VDS ≤ VGS - Vt → Pinched off channel .

• NMOS Devices can be made smaller & thus operate faster . Require low power supply .
• Saturation region → Amplifier
• For switching operation Cutoff & triode regions are used

• NMOS PMOS

VGS ≥ Vt VGS ≤ Vt → induced channel

VGS - VDS > Vt VGS - VDS < Vt → Continuous channel(Triode region)

VDS ≥ VGS - Vt VDS ≤ VGS - Vt → Pinchoff (Saturation)

Depletion Type MOSFET :- [ channel is physically implanted . i0 flows with VGS = 0 ]

• For n-channel VGS → +ve → enhances channel .

→ -ve → depletes channel

• iD - VDS characteristics are same except that Vt is –ve for n-channel

• Value of Drain current obtained in saturation when VGS = 0 ⇒ IDSS .

1 𝑊𝑊
∴ IDSS = K ′n � � Vt2 .
2 𝐿𝐿

MOSFET as Amplifier :-

• For saturation VD > VGS - Vt

• To reduce non linear distortion 𝑣𝑣gs < < 2(VGS - Vt )
𝑊𝑊 𝑊𝑊
• id = K ′n � � (VGS − Vt ) 𝑣𝑣gs ⇒ g m = K ′n � � (VGS − Vt )
𝐿𝐿 𝐿𝐿

𝑣𝑣d
• 𝑣𝑣gs
= - gm RD

gm
• Unity gain frequency fT = 2π(C
gs +Cgd )

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JFET :-
• VGS ≤ Vp ⇒ iD = 0 → Cut off

• Vp ≤ VGS ≤ 0, VDS ≤ VGS - Vp

2
𝑉𝑉𝐺𝐺𝐺𝐺 𝑉𝑉 𝑉𝑉𝐷𝐷𝐷𝐷
iD = IDSS �2 �1 − � � 𝐷𝐷𝐷𝐷 � − � � � � → Triode
𝑉𝑉𝑝𝑝 −𝑉𝑉𝑝𝑝 𝑉𝑉𝑝𝑝

• Vp ≤ VGS ≤ 0 , VDS ≥ VGS - Vp

2
𝑉𝑉 I
iD = IDSS �1− 𝐺𝐺𝐺𝐺 � ⇒ VGS = Vp �1−� 𝐷𝐷 �
𝑉𝑉𝑝𝑝 IDSS
2IDSS 𝑉𝑉 2I I𝐷𝐷
� → Saturation
gm = �1− 𝐺𝐺𝐺𝐺 � = DSS �I
|Vp | 𝑉𝑉𝑝𝑝 |Vp | DSS

Zener Regulators :-

Vi − Vz
• For satisfactory operation Rs
≥ IZmin + ILmax
Vsmin − Vz0 − IZmin rz
• R Smax = IZmin + ILmax

• Load regulation = - (rz || R s )

rz
• Line Regulation = Rs +rz
.

• For finding min R L take Vs min & Vzk , Izk (knee values (min)) calculate according to that .

Operational Amplifier:- (VCVS)

• Fabricated with VLSI by using epitaxial method

• High i/p impedance , Low o/p impedance , High gain , Bandwidth , slew rate .
• FET is having high i/p impedance compared to op-amp .
• Gain Bandwidth product is constant .
A
• Closed loop voltage gain ACL = 1± βOLA β → feed back factor
OL

−1
• ⇒ V0 = ∫ Vi dt → LPF acts as integrator ;
RC

−R −L dvi
• ⇒ V0 = ∫ 𝑉𝑉i dt ; V0 = (HPF)
L R dt

−1 dvi
• For Op-amp integrator V0 = ∫ 𝑉𝑉i dt ; Differentiator V0 = - τ
τ dt

∆V0 ∆V0 ∆Vi ∆Vi

• Slew rate SR = ∆t
= ∆t
. ∆t
= A. ∆t

slew rate slew rate

• Max operating frequency fmax = = .
2π . ∆V0 2π × ∆Vi ×A

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• In voltage follower Voltage series feedback

• In non inverting mode voltage series feedback

• In inverting mode voltage shunt feed back

𝑉𝑉
• V0 = -η VT ln �𝑅𝑅I𝑖𝑖 �
0

• V0 = - VBE

𝑉𝑉
= - η VT ln �𝑅𝑅I 𝑠𝑠 �
𝐶𝐶0

1 𝑉𝑉
• Error in differential % error = � 𝑐𝑐 �× 100 %
CMRR 𝑉𝑉𝑑𝑑

Power Amplifiers :-
B 2 B21
• Fundamental power delivered to load P1 = � 21 � R L = RL
√ 2
𝐵𝐵12 𝐵𝐵22
• Total Harmonic power delivered to load PT = � 2 + 2
+ ⋯ . . � 𝑅𝑅𝐿𝐿

𝐵𝐵 2 𝐵𝐵 2
= P1 �1 + �𝐵𝐵2 � + �𝐵𝐵3 � + … … �
1 1
= [ 1+ D2 ] P1

B
Where D = �+D22 + ⋯ . . +D2n Dn = Bn
1
D = total harmonic Distortion .

Class A operation :-
• o/p IC flows for entire 3600
• ‘Q’ point located @ centre of DC load line i.e., Vce = Vcc / 2 ; η = 25 %
• Min Distortion , min noise interference , eliminates thermal run way
• Lowest power conversion efficiency & introduce power drain
• PT = IC VCE - ic Vce if ic = 0, it will consume more power
• PT is dissipated in single transistors only (single ended)

Class B:-

• IC flows for 1800 ; ‘Q’ located @ cutoff ; η = 78.5% ; eliminates power drain
• Higher Distortion , more noise interference , introduce cross over distortion
• Double ended . i.e ., 2 transistors . IC = 0 [ transistors are connected in that way ] PT = ic Vce
• PT = ic Vce = 0.4 P0 PT → power dissipated by 2 transistors .

Class AB operation :-

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• IC flows for more than 1800 & less than 3600

• ‘Q’ located in active region but near to cutoff ; η = 60%
• Distortion & Noise interference less compared to class ‘B’ but more in compared to class ‘A’
• Eliminates cross over Distortion

Class ‘C’ operation :-

• IC flows for < 180 ; ‘Q’ located just below cutoff ; η = 87.5%
• Very rich in Distortion ; noise interference is high .

Oscillators :-
1 29
• For RC-phase shift oscillator f = hfe ≥ 4k + 23 + where k = R c /R
2πRC √6+4K k

1
f= μ > 29
2πRC√6

1
• For op-amp RC oscillator f = | Af | ≥ 29 ⇒ R f ≥ 29 R1
2πRC√6

Wein Bridge Oscillator :-

1
f = ,
2π R1 R2C1C2
1 1
if R1=R2=R, C1=C2=C , f = ; A= =3
2π RC β

Hartley Oscillator :-
1 L
f= |hfe | ≥ L2
2π�(L1 +L2 )C 1
L
| μ | ≥ L2
1
L
|A| ≥ L2
1
↓
Rf
R1

Colpits Oscillator :-
1 C
f= C C
|hfe | ≥ C1
2π�L 1 2 2
C1 +C2
C
| μ | ≥ C1
2

C
| A | ≥ C1
2

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Phase shift oscillator:-
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FET MODEL
1
f = , A = 29 ,
2π 6 RC
Minimum RC sections 3

BJT MODEL
1
f = , A = 29 ,
⎛ 4R ⎞
2π RC 6 + ⎜ C ⎟
⎝ R ⎠
Minimum RC sections 3

Comparisons:
MOSFET JPET
BJT FET
High Ri = 10 −108
10
Current controlled Voltage controlled

High gain Med gain R0 = 50 kΩ ≥ 1mΩ

Bipolar Unipolar
Depletion Depletion
Temp sensitive Little effect of T
Enhancement Mode Mode
High GBWP Low GBWP
Delicate Rugged
Rectifiers:

Comparisons:
HW FW CT FW BR

VDC Vm 2Vm 2Vm

π π π
Vm Vm Vm
Vrms
2 2 2
γ
1.21 0.482 0.482
Ripple factor

η
40.6% 81% 81%
Rectification efficiency

PIV Vm 2 Vm Vm
Peak Inverse Voltage
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